Preparation method of MEMS bulk silicon structure and MEMS sensor

Abstract

The present application is applicable to the field of semiconductor device technology and provides a method for preparing a MEMS bulk silicon structure for a MEMS sensor. The MEMS bulk silicon structure includes a first silicon substrate and a second silicon substrate. The method includes: etching and filling a first blind hole on the front surface of the first silicon substrate; the first blind hole has a first preset depth; etching a second blind hole on the back surface of the first silicon substrate at a position opposite the first blind hole; the second blind hole has a second preset depth; the aperture of the second blind hole is larger than the aperture of the first blind hole; the sum of the first preset depth and the second preset depth is the thickness of the first silicon substrate; filling the second blind hole to form a filled silicon via structure with a goblet structure; and bonding the front surface of the first silicon substrate to the second silicon substrate to form the MEMS bulk silicon structure. The present application can avoid the "undercut" or footing effect at the bottom of the silicon substrate, improve the coverage quality of the silicon via metal seed layer, and thus improve the reliability of the silicon via electrical performance.

Description

Technical Field

[0001] The present application belongs to the technical field of semiconductor devices, and in particular relates to a method for preparing a MEMS bulk silicon structure MEMS sensor. Background Art

[0002] In the field of semiconductor technology, 3D stacked packaging technology has been considered the key to the ability to manufacture high-performance chips in a smaller size. In the application of 3D stacked packaging technology, the bulk silicon structure involved is generally a multi-layer structure of silicon substrates. By etching the bulk silicon structure, vertical conductions are created between chips and between silicon substrates, thereby achieving interconnection between chips. In most cases, the production of through-silicon vias (TSVs) requires opening up different material layers, and the resulting through-holes must meet profile control requirements. Therefore, the TSV etching process is the key to TSV production technology.

[0003] In the prior art, when one side of the silicon substrate is etched, an over-etching process is usually performed for a certain period of time at the end of the etching process to ensure that the silicon substrate is completely etched. Since the etching gas has a faster etching rate for silicon and a slower etching rate for the silicon oxide layer, the etching reaction will etch laterally at the bottom of the through silicon via (TSV), that is, the etched silicon substrate between the two silicon substrates. In addition, due to the influence of the oxide layer reflection between the two silicon substrates on the etching, the silicon wafer is prone to "undercutting" or footing effect at the bottom of the through silicon via and the bottom of the silicon substrate, such as Figure 1 As shown, this not only weakens the coverage quality of the TSV metal seed layer, but also reduces the reliability of its electrical performance. Summary of the Invention

[0004] To overcome the problems existing in the related art, the embodiment of the present application provides a method for preparing a MEMS bulk silicon structure MEMS sensor, which can solve the problem of "undercutting" or footing effect at the bottom of the silicon substrate, resulting in reduced reliability of silicon vias.

[0005] This application is achieved through the following technical solutions:

[0006] In a first aspect, an embodiment of the present application provides a method for fabricating a MEMS bulk silicon structure, the MEMS bulk silicon structure including a first silicon substrate and a second silicon substrate, the method comprising:

[0007] Etching a first blind hole on the front surface of the first silicon substrate; the first blind hole has a first preset depth;

[0008] filling the first blind hole;

[0009] Etching a second blind hole at a position opposite to the first blind hole on the back side of the first silicon substrate; the second blind hole has a second preset depth; the aperture of the second blind hole is larger than the aperture of the first blind hole; the sum of the first preset depth and the second preset depth is equal to the thickness of the first silicon substrate;

[0010] Filling the second blind hole to form a filled through silicon via structure with a goblet structure;

[0011] The front surface of the first silicon substrate having the filled through silicon via structure is bonded to one side of the second silicon substrate to form a MEMS bulk silicon structure.

[0012] In one embodiment, bonding a front surface of a first silicon substrate having a filled through silicon via structure to a side surface of a second silicon substrate includes:

[0013] forming an oxide layer on the front surface of the first silicon substrate having the filled through silicon via structure;

[0014] The oxide layer is bonded to one side of the second silicon substrate.

[0015] In one embodiment, bonding the front surface of the first silicon substrate having the filled through silicon via structure to one side of the second silicon substrate further comprises:

[0016] forming an oxide layer on one side of the second silicon substrate;

[0017] The front surface of the first silicon substrate having the filled through silicon via structure is bonded to the oxide layer.

[0018] In one embodiment, filling the first blind hole includes:

[0019] depositing a first initial barrier layer in the first blind hole;

[0020] etching away the bottom of the first initial barrier layer to form a first final barrier layer;

[0021] depositing a first seed layer on the first final barrier layer;

[0022] Based on the first seed layer, the first blind hole is filled by electroplating.

[0023] In one embodiment, filling the second blind hole includes:

[0024] depositing a second initial barrier layer in the second blind hole;

[0025] Opening a connecting hole at the bottom of the second initial barrier layer to form a second final barrier layer;

[0026] depositing a second seed layer on the second final barrier layer; the second seed layer fills the communicating holes;

[0027] Based on the second seed layer, the second blind hole is filled by electroplating.

[0028] In one embodiment, the communicating holes are formed on the bottom surface of the second initial barrier layer, comprising:

[0029] A preset method is used to open a communicating hole on the bottom surface of the second initial barrier layer; the preset method includes laser spot ablation, ion milling or electrical corrosion.

[0030] In one embodiment, the ratio of the second preset depth to the first preset depth is in the range of [3, 10].

[0031] In one embodiment, after filling the second blind hole, the method for preparing the MEMS bulk silicon structure further includes:

[0032] A fluorocarbon-based protective layer or a hydrocarbon-based protective layer is deposited on the back side of the first silicon substrate.

[0033] In one embodiment, the aperture ratio of the second blind hole to the first blind hole is in the range of [3, 10].

[0034] In a second aspect, the present application provides a MEMS sensor provided with a MEMS bulk silicon structure prepared by the method for preparing a MEMS bulk silicon structure according to the second aspect.

[0035] Compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0036] In the embodiment of the present application, since etching through the silicon substrate requires depositing an oxide layer, the oxide layer is bound to be a poor conductor, causing charge accumulation, and further causing reverse etching. The present invention first etches a first blind hole with the front side as a small hole, and then etches a second blind hole with the back side as a large hole. The etching falls directly on the silicon layer without involving the oxide layer, avoiding the phenomenon of ion reflection causing the bottom of the hole to expand due to the general TSV landing in the dielectric area. Therefore, the process morphology and metal filling are easy to control, avoiding the "undercut" or footing effect at the bottom of the first silicon substrate. The reverse etching falls on the metal and silicon layers, also avoiding the "undercut" or footing effect at the bottom of the first silicon substrate, thereby improving the coverage quality of the metal seed layer of the through-silicon via, thereby improving the reliability of the electrical performance of the through-silicon via.

[0037] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0039] Figure 1 Schematic diagram of the "undercut" or footing effect generated between silicon substrates according to one embodiment of the present application;

[0040] Figure 2 1 is a flow chart of a method for preparing a MEMS bulk silicon structure provided in one embodiment of the present application;

[0041] Figure 3 This is a schematic diagram of the structure of etching a first blind hole on the front side according to an embodiment of the present application;

[0042] Figure 4 This is a schematic diagram of the structure after the first blind hole is filled according to an embodiment of the present application;

[0043] Figure 5 This is a schematic diagram of the structure of etching a second blind hole provided in one embodiment of the present application;

[0044] Figure 6 This is a schematic diagram of the structure after the second blind hole is filled according to an embodiment of the present application;

[0045] Figure 7 Schematic diagram of the structure of a MEMS bulk silicon structure provided by an embodiment of the present application;

[0046] Figure 8 : is a structural diagram of the morphology of through silicon via etching provided in one embodiment of the present application; wherein, Figure 8 (a), (b) and (c) are schematic diagrams of the structure of silicon vias without footing effect. Figure 8 (d), (e) and (f) are schematic diagrams of the structures of through-silicon vias with footing effect;

[0047] Figure 9 : is a schematic diagram of a structure for filling a first blind hole provided by an embodiment of the present application; wherein, Figure 9 (a) is a schematic diagram of the structure of depositing the first initial barrier layer. Figure 9 (b) is a schematic diagram of the structure of forming the first final barrier layer. Figure 9 (c) is a schematic diagram of the structure of filling the first blind hole based on the first seed layer;

[0048] Figure 10 : is a schematic diagram of a structure for filling a second blind hole provided by an embodiment of the present application; wherein, Figure 10 (a) is a schematic diagram of the structure for depositing the second initial barrier layer. Figure 10 (b) is a schematic diagram of the structure of forming the second final barrier layer. Figure 10 (c) is a schematic diagram of the structure of filling the second blind hole based on the second seed layer. DETAILED DESCRIPTION

[0049] In the following description, specific details such as specific system structures and techniques are provided for purposes of illustration rather than limitation to facilitate a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid obscuring the description of the present application with unnecessary detail.

[0050] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or collections thereof.

[0051] It will also be understood that the term "and / or" used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0052] As used in this specification and the appended claims, the term "if" can be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0053] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0054] References to "one embodiment" or "some embodiments" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. The terms "including," "comprising," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized.

[0055] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0056] Figure 2 This is a flow chart of a method for preparing a MEMS bulk silicon structure according to an embodiment of the present application. Figure 2 , the preparation method of the MEMS bulk silicon structure is described in detail as follows:

[0057] An embodiment of the present application provides a method for fabricating a MEMS bulk silicon structure, wherein the MEMS bulk silicon structure includes a first silicon substrate and a second silicon substrate. The method includes:

[0058] Step 101: etching a first blind hole on the front surface of a first silicon substrate.

[0059] The first blind hole has a first preset depth H1, such as Figure 3 shown.

[0060] Step 102: Fill the first blind hole.

[0061] The structure after the first blind hole is filled is as follows Figure 4 shown.

[0062] Step 103: etching a second blind hole at a position on the back side of the first silicon substrate opposite to the first blind hole.

[0063] The second blind hole has a second preset depth H2; the aperture D2 of the second blind hole is larger than the aperture D1 of the first blind hole; the sum of the first preset depth and the second preset depth is the thickness of the first silicon substrate, such as Figure 5 shown.

[0064] Step 104 : Fill the second blind hole to form a filled through silicon via structure with a goblet structure.

[0065] The structure after the second blind hole is filled is as follows Figure 6 As shown, the through silicon via structure is mainly used to connect the internal circuit of the first silicon substrate with the outside, and then bonded with the second silicon substrate together with the first silicon substrate.

[0066] Step 105 : Bonding the front surface of the first silicon substrate having the filled through silicon via structure to one side of the second silicon substrate to form a MEMS bulk silicon structure.

[0067] Exemplarily, the front side of the first silicon substrate with the filled through silicon via structure is bonded to the second silicon substrate, an oxide layer is provided between the first silicon substrate and the second silicon substrate, the front side of the first silicon substrate is the surface adjacent to the oxide layer, and the back side of the first silicon substrate is the surface away from the oxide layer. During the bonding process, the oxide layer plays a key role in isolation and insulation. The front side of the first silicon substrate is bonded to the oxide layer, ensuring electrical isolation between the first silicon substrate and the second silicon substrate, preventing signal interference, and also providing stability for the entire structure to meet the performance requirements of MEMS sensors in different application scenarios, such as Figure 7 shown.

[0068] The MEMS bulk silicon structure in this embodiment is a part of a MEMS sensor. For example, in a micro acceleration sensor, a slight size change of the bulk silicon structure may cause a large fluctuation in the sensitivity of the sensor.

[0069] This embodiment takes into account that etching of a transparent silicon substrate requires deposition of an oxide layer, which is inevitably a poor conductor, causing charge accumulation and further causing etching reverse etching problems, such as Figure 8 As shown, Figure 8 (a) is the morphology of normal TSV etching. By adjusting the parameters, the angle can be changed within a certain range, for example Figure 8 (b) and (c) in the figure, but when there is a medium underneath, sputtering from top to bottom will occur, and the footing effect will definitely occur. Figure 8 In the case of the incision in (d), (e) and (f), the metal process is more difficult due to this small gap, and it is difficult to fully cover the metal seed layer, which will cause reliability problems later. In this application, by first engraving the first blind hole as a small hole on the front side and then engraving the second blind hole as a large hole on the back side, the etching falls directly on the silicon layer without involving the oxide layer, avoiding the phenomenon of ion reflection caused by the general TSV landing in the dielectric area and causing the bottom of the hole to expand, then the process morphology and metal filling are easy to control, avoiding the "undercut" or footing effect at the bottom of the first silicon substrate, and the reverse etching falls on the metal and silicon layers, also avoiding the "undercut" or footing effect at the bottom of the first silicon substrate, improving the coverage quality of the metal seed layer of the silicon via, thereby improving the reliability of the electrical performance of the silicon via.

[0070] In one embodiment, see Figure 9 , specifically introduce the detailed process of filling the first blind hole, step 102 includes:

[0071] First, a first initial barrier layer is deposited in the first blind hole, such as Figure 9As shown in (a), a preliminary barrier is formed inside the blind hole to prevent the material from penetrating into the unwanted area during the subsequent deposition or electroplating process, ensuring that it can effectively isolate and protect the inner wall of the hole.

[0072] Then, the bottom of the first initial barrier layer is etched away to form a first final barrier layer, such as Figure 9 As shown in (b) in the figure, the bottom portion of the initial barrier layer is removed through an etching process to prepare for the subsequent formation of a conductive connection with the second blind hole.

[0073] Next, a first seed layer is deposited on the first final barrier layer. Based on the first seed layer, the first blind hole is filled by electroplating, such as Figure 9 As shown in (c) of the figure, a conductive material, such as copper, is added to the blind via via electroplating, based on the seed layer. During the electroplating process, the conductive material precipitates from the plating solution under the influence of the electric field and deposits on the seed layer, gradually filling the entire blind via. This paves the way for a subsequent conductive connection with the second blind via, improving the overall performance and reliability of the sensor.

[0074] In one embodiment, see Figure 10 , specifically introduce the process of filling the second blind hole, including:

[0075] First, a second initial barrier layer is deposited in the second blind hole, such as Figure 10 As shown in (a) in .

[0076] Then, a connecting hole is opened at the bottom of the second initial barrier layer to form a second final barrier layer, such as Figure 10 As shown in (b) in .

[0077] Next, a second seed layer is deposited on the second final barrier layer. Based on the second seed layer, the second blind hole is filled by electroplating, as shown in FIG. Figure 10 As shown in (c) in the figure.

[0078] The second seed layer fills the connecting holes.

[0079] Exemplarily, the method of opening a connecting hole on the bottom surface of the second initial barrier layer includes:

[0080] A preset method is used to open a communicating hole on the bottom surface of the second initial barrier layer; the preset method includes laser spot ablation, ion milling or electrical corrosion.

[0081] By opening a connecting hole on the bottom surface of the second initial barrier layer and filling it with metal, a conductive connection between the first blind hole and the second blind hole can be achieved.

[0082] For example, the dielectric on the bottom of the first blind hole has been etched away before filling, and the second blind hole is entirely covered with an oxide layer, that is, an oxide layer. When achieving a conductive connection between the first blind hole and the second blind hole, if a general etching method is used, the oxide layer covering the second blind hole will be etched away, resulting in leakage. Therefore, how to achieve a conductive connection between the first blind hole and the second blind hole requires consideration of special means. This embodiment uses laser point ablation, ion milling to connect the hole dielectric, or back-side electrification to accelerate corrosion to achieve a hole in the dielectric area above the metal. Only a small hole is opened at the connection between the first blind hole and the second blind hole without affecting the oxide layer covering the inside of the second blind hole. Then, copper is deposited on the front side for metallization to achieve a conductive connection between the first blind hole and the second blind hole while avoiding leakage.

[0083] In one embodiment, TSVs primarily provide signal connectivity for the product. Therefore, these interlayer vias offer lower resistance and the shortest possible links compared to in-plane wiring. This effectively reduces signal interference and increases power capacity, making them an ideal solution for 2.5D and 3D packaging. The provision of a first blind via effectively reduces chip area and increases density. However, ensuring the isolation layer and seed layer coverage and filling of the first blind via present significant challenges.

[0084] The ratio of the second preset depth to the first preset depth ranges from [3, 10]. By setting this ratio, the depth of the second blind via, which functions as a larger hole, is reduced while maintaining the required total depth of the through-silicon via. This reduces undercutting and avoids coverage issues with the metal seed layer during the subsequent via filling process. Furthermore, by setting the aperture and depth ratio of the first and second blind vias, the isolation layer seed layer coverage and filling of the first blind via are controlled.

[0085] The aperture of the first blind via, which serves as a small hole, can be set to 8 to 10 microns, demonstrating the advantages of a small pitch. The bottom of the single-sided etched hole is entirely silicon, devoid of dielectric material, eliminating reflective etching caused by charge accumulation. Coverage and filling with an isolation layer with a 10:1 ratio of the second preset depth to the first preset depth are easily achieved, and controlling the hole depth between 60 and 80 microns ensures quality.

[0086] The upper reverse side of the first silicon substrate does not involve the internal structure of the sensor, so the aperture of the large hole can be relatively large. For example, based on a TSV with a total thickness of 300 microns, the depth of the large hole can be set to 240 microns, and the depth of the small hole is 40 microns. The ratio of the second preset depth to the first preset depth is 4:1. The aperture of the large hole can be designed to be between 40 microns and 60 microns, which is consistent with the aperture ratio of the second blind hole to the first blind hole being in the range of [3,10]. In the process of etching the large hole, the small hole has already been filled, and the bottom of the large hole is all silicon, and there is no dielectric. Therefore, reverse etching will not occur, and filling layer coverage and filling are easy to achieve.

[0087] In one embodiment, after filling the first blind hole, before etching the second blind hole on the back side of the first silicon substrate at a position opposite to the first blind hole, the front side of the first silicon substrate having the filled through-silicon via structure and one side of the second silicon substrate are bonded, including: preparing an oxide layer on the front side of the first silicon substrate having the filled through-silicon via structure; and bonding the oxide layer to one side of the second silicon substrate.

[0088] Alternatively, bonding the front surface of the first silicon substrate having the filled through silicon via structure to one side of the second silicon substrate further includes: preparing an oxide layer on one side of the second silicon substrate; and bonding the front surface of the first silicon substrate having the filled through silicon via structure to the oxide layer.

[0089] For example, since bonding the front surface of the first silicon substrate to the oxide layer after filling the first blind hole does not involve the problem of oxide layer reflection when etching the hole, both of the above bonding times are possible, providing greater flexibility and operating space for the process flow.

[0090] In one embodiment, after filling the second blind hole, the method for preparing the MEMS bulk silicon structure further includes:

[0091] A fluorocarbon-based protective layer or a hydrocarbon-based protective layer is deposited on the back side of the first silicon substrate.

[0092] Fluorocarbon- and hydrocarbon-based protective layers offer excellent chemical stability and hydrophobicity, effectively protecting the pore walls from chemical corrosion, moisture erosion, and physical damage that may occur during subsequent processing steps. These protective layers adhere tightly to the pore walls, forming a robust barrier that protects the pore's structural integrity and functionality. Depositing these protective layers using dry film deposition or other automated deposition techniques typically offers faster deposition rates and a high degree of automation, significantly improving production efficiency.

[0093] The preparation method of the MEMS bulk silicon structure of the embodiment of the present application is to first etch a first blind hole as a small hole on the front side and then etch a second blind hole as a large hole on the back side. The etching falls directly on the silicon layer without involving the oxide layer, avoiding the phenomenon of ion reflection causing the bottom of the hole to expand due to the landing of the general TSV in the dielectric area. Therefore, the process morphology and metal filling are easy to control, avoiding the "undercut" or footing effect at the bottom of the first silicon substrate. The reverse etching falls on the metal and silicon layers, also avoiding the "undercut" or footing effect at the bottom of the first silicon substrate, improving the coverage quality of the metal seed layer of the silicon via, thereby improving the reliability of the electrical performance of the silicon via.

[0094] The present application provides a MEMS sensor provided with a MEMS bulk silicon structure prepared by the method for preparing the MEMS bulk silicon structure of the above embodiment.

[0095] The beneficial effects of a through silicon via and a MEMS sensor refer to the beneficial effects of a method for preparing a MEMS bulk silicon structure.

[0096] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0097] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A method for preparing a MEMS bulk silicon structure, characterized in that: The MEMS bulk silicon structure includes a first silicon substrate and a second silicon substrate, wherein an oxide layer is provided between the first silicon substrate and the second silicon substrate, the front surface of the first silicon substrate is a surface adjacent to the oxide layer, and the back surface of the first silicon substrate is a surface away from the oxide layer; the method includes: Etching a first blind hole on the front surface of the first silicon substrate; the first blind hole has a first preset depth; filling the first blind hole; Etching a second blind hole on the back side of the first silicon substrate at a position opposite to the first blind hole; the second blind hole has a second preset depth; the aperture of the second blind hole is larger than the aperture of the first blind hole; the sum of the first preset depth and the second preset depth is equal to the thickness of the first silicon substrate; filling the second blind hole to form a filled through silicon via structure with a goblet structure; Bonding the front surface of the first silicon substrate having the filled through-silicon via structure to one side of the second silicon substrate to form a MEMS bulk silicon structure; wherein the through-silicon via structure is used to connect the internal circuit of the first silicon substrate to the outside; Bonding the front surface of the first silicon substrate having the filled through silicon via structure to one side of the second silicon substrate comprises: preparing an oxide layer on the front surface of the first silicon substrate having the filled through silicon via structure; bonding the oxide layer to one side of the second silicon substrate; Alternatively, an oxide layer is prepared on one side of the second silicon substrate; and the front side of the first silicon substrate having the filled through silicon via structure is bonded to the oxide layer.

2. The method for preparing a MEMS bulk silicon structure according to claim 1, wherein: Filling the first blind hole comprises: depositing a first initial barrier layer in the first blind hole; Etching away the bottom of the first initial barrier layer to form a first final barrier layer; depositing a first seed layer on the first final barrier layer; Based on the first seed layer, the first blind hole is filled by electroplating.

3. The method for preparing a MEMS bulk silicon structure according to claim 1, wherein: Filling the second blind hole comprises: depositing a second initial barrier layer in the second blind hole; Opening a connecting hole at the bottom of the second initial barrier layer to form a second final barrier layer; depositing a second seed layer on the second final barrier layer; the second seed layer filling the communicating holes; Based on the second seed layer, the second blind hole is filled by electroplating.

4. The method for preparing a MEMS bulk silicon structure according to claim 3, wherein: The step of opening a communicating hole on the bottom surface of the second initial barrier layer comprises: A connecting hole is opened on the bottom surface of the second initial barrier layer by a preset method; the preset method includes laser spot ablation, ion milling or electrochemical corrosion.

5. The method for preparing a MEMS bulk silicon structure according to claim 1, wherein: A ratio of the second preset depth to the first preset depth is in a range of [3, 10].

6. The method for preparing a MEMS bulk silicon structure according to any one of claims 1 to 5, wherein: After filling the second blind hole, the method for preparing the MEMS bulk silicon structure further includes: A fluorocarbon-based protective layer or a hydrocarbon-based protective layer is deposited on the back side of the first silicon substrate.

7. The method for preparing a MEMS bulk silicon structure according to any one of claims 1 to 5, wherein: An aperture ratio between the second blind hole and the first blind hole is in a range of [3, 10].

8. A MEMS sensor, characterized in that: A MEMS bulk silicon structure prepared by the method for preparing a MEMS bulk silicon structure according to any one of claims 1 to 7 is provided.

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