Method and system for improving chip parallel measurement DUT (Device Under Test) number

Abstract

The invention discloses a method and a system for improving chip parallel test DUT (Device Under Test) number, and belongs to the technical field of chip test. Comprising the following steps: performing peripheral circuit relay analysis according to a chip test schematic diagram; obtaining the number of digital input and output channels according to the digital board card configuration resources of the automatic test equipment; and according to the channel resources of the power board card of the automatic test equipment and the obtained number of the digital input and output channels, calculating to obtain the number of the tested chips of the parallel test. Compared with the prior art, the method has the beneficial effects that the whole test time is greatly shortened by optimizing the simultaneous test number of the tested chips, so that the test efficiency of the automatic test equipment is improved; due to the improvement of the test efficiency, the same number of chips can be tested in a shorter time, so that the use time and the labor cost of test equipment are reduced, and the batch test cost of the chips is further reduced.

Description

Technical Field

[0001] The present invention relates to the field of chip testing technology, and more specifically to a method and system for improving the number of chip DUTs tested. Background Art

[0002] In the ATE (Automatic Test Equipment) testing process of semiconductor integrated circuit chips, increasing the number of DUTs (Device Under Test) is one of the key factors for optimizing test efficiency, shortening test cycles, reducing costs and increasing production, which helps to improve the efficiency and economy of the test process, and is particularly important for supporting large-scale mass production. However, the design of FT (Final Test) test load board (LB for short) and CP (Chip Probe) probe card (PC for short) faces multiple challenges in achieving a high number of DUTs. These limiting factors not only cover the channel capacity limitations of ATE internal boards (such as power boards, digital boards, relay control boards, etc.), but also involve the layout density, size adaptability and manufacturer's production process level of electronic components on LB or PC.

[0003] In traditional design practice, TE (Test Engineer) plans the test schematic diagram of LB or PC based on the chip's ATE test peripheral circuit diagram at the beginning of the project. It is necessary to carefully consider the types and quantities of components in the schematic diagram, as well as the chip's digital signal IO pins (Input / Output) and DPS pins (Device Power Supply) requirements, and combine the ATE's board channel resources to comprehensively determine the number of parallel-test DUTs of LB or PC. However, when the demand for relays (referred to as Relay) in the chip ATE test peripheral circuit increases significantly, the design challenge is particularly prominent. Especially when designing the probe card PCB peripheral circuit, since the area on the probe card PCB that can be used to place various electronic components is very limited, it is impossible to place the required large number of relays, which will severely limit the number of parallel-test DUTs that can be designed, and thus cannot effectively improve the ATE's parallel-test efficiency.

[0004] In the related art, for example, Chinese patent CN118299220A provides a method for extending relay control signals. The scheme implements combined control through ATE relay control signals to achieve the expansion of relay control signals to solve the problem of insufficient relay control signals. The specific method is to use a channel selection module including a shift register on the interface board to achieve the expansion of the number of channels of the relay control signal, redistribute multiple relay signals, connect each two relay control signals as a group of combined control signals to the channel selection module, control different ports of the channel selection module with different combinations of signals, and then transmit to multiple relays and assign the test channels connected to the relays to the probe card to achieve the expansion of the relay control signal. However, the shortcoming of this scheme is that it does not provide a technical invention solution or inspiration on how to design more chips in a limited PCB space and measure the number of DUTs to improve the chip testing efficiency. Summary of the invention

[0005] 1. Technical problems to be solved

[0006] In view of the problem in the prior art of how to achieve more efficient layout design within a limited PCB space to maximize the number of DUTs that can be tested in parallel on a chip, thereby improving chip testing efficiency, the present invention provides a method and system for increasing the number of DUTs that can be tested in parallel on a chip, which can reduce the placement space of physical relay components, thereby saving PCB space to achieve the design of more chips and test more DUTs, thereby effectively improving chip testing efficiency.

[0007] 2. Technical solution

[0008] The purpose of the present invention is achieved through the following technical solutions.

[0009] The content of this application is used to introduce concepts in a brief form, which will be described in detail in the detailed implementation section below. The content of this application is not intended to identify the key features or essential features of the technical solution claimed for protection, nor is it intended to limit the scope of the technical solution claimed for protection.

[0010] Some embodiments of the present application propose a method and system for increasing the number of DUTs that can be measured simultaneously on a chip to solve the technical problems mentioned in the above background technology section.

[0011] As the first aspect of the present application, some embodiments of the present application provide a method for increasing the number of DUTs that can be tested in parallel on a chip, comprising the following steps: performing peripheral circuit relay analysis based on a chip test schematic; obtaining the number of digital input and output channels based on the digital board configuration resources of an automatic test device; and calculating the number of chips to be tested in parallel based on the channel resources of a power board of the automatic test device and the obtained number of digital input and output channels.

[0012] Furthermore, the peripheral circuit relay analysis is to analyze the relay signal control of the chip test schematic circuit in the peripheral circuit using the programmable relay on the digital board of the automatic test equipment.

[0013] Furthermore, the process of peripheral circuit relay analysis is: according to the chip test schematic diagram and the peripheral circuit analysis, to find out the peripheral local circuit that uses the most relay components.

[0014] Furthermore, the process of obtaining the number of digital input and output channels of the automatic test equipment is:

[0015] Get the total number of digital input and output channels of automatic test equipment;

[0016] The number of digital input and output channels is obtained by subtracting the number of input and output channels of the physical relays required for each chip under test on the load board or probe card in the chip test design from the total number of digital input and output channels.

[0017] Furthermore, the process of obtaining the total number of digital input and output channels of the automatic test equipment is as follows:

[0018] According to the digital board configuration resources of the automatic test equipment, the number of input and output channels on each digital board is accumulated to obtain the total number of digital input and output channels of the automatic test equipment.

[0019] Furthermore, the digital board configuration resources of the automatic test equipment include the models and quantity of the digital boards equipped by the automatic test equipment and the quantity of input and output channels configured on each digital board.

[0020] Furthermore, the number of chips tested in parallel is calculated based on the resources that can be tested simultaneously on the load board or probe card; the resources include the number of input and output channels provided by the digital board and the channel resources of the dynamic power supply board.

[0021] Furthermore, the steps of obtaining the number of chips to be tested in parallel include:

[0022] The number of input and output channels required for other test tasks and the number of redundant input and output channels reserved to cope with potential demands are subtracted from the total number of digital input and output channels of the automatic test equipment to obtain the number of remaining digital input and output channels of the automatic test equipment.

[0023] Furthermore, the steps of obtaining the number of chips to be tested in parallel include:

[0024] Based on the obtained number of remaining digital input and output channels of the automatic test equipment and the number of digital input and output channels required to be occupied by each chip under test during the test process, the number of chips under test that can be tested in parallel is calculated;

[0025] The calculation process is as follows: determine the number of input and output channels of the automatic test equipment that each chip under test needs to occupy during the test; obtain the number of remaining digital input and output channels of the automatic test equipment; divide the number of remaining digital input and output channels of the automatic test equipment by the number of input and output channels required for each chip under test, and take the integer result to obtain the number of chips under test for parallel testing.

[0026] As the second aspect of the present application, some embodiments of the present application provide a system for increasing the number of DUTs that can be tested in parallel on a chip, including: an analysis module: analyzing the peripheral circuit structure to perform peripheral circuit relay analysis based on the chip test schematic; a calculation module: obtaining the number of digital input and output channels based on the resources of the automatic test equipment; and calculating the number of chips to be tested in parallel based on the power resources of the automatic test equipment and the obtained number of digital input and output channels.

[0027] 3. Beneficial effects

[0028] Compared with the prior art, the advantages of the present invention are as follows: This solution significantly shortens the overall test time by optimizing the number of chips to be tested in parallel, thereby improving the test efficiency of ATE (automatic test equipment). Due to the improvement in test efficiency, the same number of chips can be tested in a shorter time, thereby reducing the use time and labor costs of the test equipment, and further reducing the batch testing costs of the chips. Higher test efficiency means that more chips can be tested in the same amount of time, thereby increasing the test output of the chip, which is of great significance for meeting market demand and accelerating the time to market for products. By improving test efficiency and reducing test costs, this technical solution achieves the goal of reducing costs and increasing efficiency in ATE testing of integrated circuit chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A schematic flow chart of a method for increasing the number of chips and DUTs measured in one embodiment of the present invention;

[0030] Figure 2 This is a schematic diagram of the placement of electronic components in one embodiment of the present invention;

[0031] Figure 3 The peripheral circuit of the chip schematic diagram in one embodiment of the present invention requires a local circuit diagram of 16 physical relays;

[0032] Figure 4 FIG. 1 is a wiring diagram of an ATE PPMU IO Channel Relay replacing a physical relay in an embodiment of the present invention.

[0033] Explanation of reference numerals in the figure: 100, probe card PCB; 101, electronic components. DETAILED DESCRIPTION

[0034] The present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0035] Combination Figures 1 to 4 A method for improving the number of DUTs measured by a chip according to the present invention comprises the following steps:

[0036] According to the chip test schematic, analyze the peripheral circuit structure to perform peripheral circuit relay analysis;

[0037] Get the number of digital input and output channels according to the automatic test equipment resources;

[0038] The number of chips to be tested in parallel is calculated based on the power resources of the automatic test equipment and the number of digital input and output channels obtained.

[0039] Specifically, the peripheral circuit relay analysis is to analyze the relay signal control of the chip test schematic circuit in the peripheral circuit using the programmable power unit relay on the digital board of the automatic test equipment.

[0040] The process of peripheral circuit relay analysis is: according to the chip test schematic diagram and the peripheral circuit analysis, to find out the peripheral local circuit that uses the most relay components.

[0041] Specifically, the process of obtaining the number of digital input and output channels of the automatic test equipment is:

[0042] Get the total number of digital input and output channels of automatic test equipment;

[0043] The number of digital input and output channels is obtained by subtracting the number of input and output channels of the physical relays required for each chip under test on the load board or probe card in the chip test design from the total number of digital input and output channels.

[0044] The process of obtaining the total number of digital input and output channels of automatic test equipment is as follows:

[0045] According to the digital board configuration resources of the automatic test equipment, the number of input and output channels on each digital board is accumulated to obtain the total number of digital input and output channels of the automatic test equipment.

[0046] The digital board configuration resources of the automatic test equipment include the model and quantity of the digital boards equipped by the automatic test equipment and the number of input and output channels configured on each digital board.

[0047] More specifically, the number of chips tested in parallel is calculated based on the resources that can be tested simultaneously on the load board or probe card; the resources include the number of input and output channels provided by the digital board and the channel resources of the dynamic power supply board.

[0048] The steps to obtain the number of chips under test for parallel testing include:

[0049] The number of input and output channels required for other test tasks and the number of redundant input and output channels reserved to cope with potential demands are subtracted from the total number of digital input and output channels of the automatic test equipment to obtain the number of remaining digital input and output channels of the automatic test equipment.

[0050] The steps to obtain the number of chips under test for parallel testing include:

[0051] Based on the obtained number of remaining digital input and output channels of the automatic test equipment and the number of digital input and output channels required to be occupied by each chip under test during the test process, the number of chips under test that can be tested in parallel is calculated;

[0052] The process of calculating the number of chips under test that can be tested in parallel is as follows:

[0053] Determine the number of automatic test equipment input and output channels that each chip under test needs to occupy during testing; obtain the number of remaining digital input and output channels of the automatic test equipment; divide the number of remaining digital input and output channels of the automatic test equipment by the number of input and output channels required for each chip under test, and take the integer result to obtain the number of chips under test for parallel testing.

[0054] In a specific embodiment, the method flow of increasing the number of chips and measuring DUTs is as follows:

[0055] S1. Analysis of peripheral circuit relays

[0056] First, according to the chip test schematic, analyze the peripheral circuit structure, find out the peripheral local circuit that uses the most relay components and perform peripheral circuit relay analysis.

[0057] Specifically, peripheral circuit relay analysis, or relay replacement analysis, refers to the analysis of whether the peripheral circuit can use the PPMU Relay (Programmable Power Unit Relay) of the ATE digital board to replace the physical relay in the peripheral circuit. PPMU is Per Pin PMU Measurement Unit. PPMU Relay refers to the relay used to control the power supply and signal on and off in this module.

[0058] Typically, the physical relays in the pull-up circuits connected to the chip's digital IO pins are potential replacements. The core of this step is to identify which relay components can be replaced by the PPMURelay on the ATE digital board.

[0059] During chip testing, the peripheral circuits are analyzed according to the chip test schematic to find the peripheral local circuits that use the most relay components. Specifically, the physical relays in the pull-up circuits connected to the chip digital IO pins can usually be replaced.

[0060] After determining the peripheral local circuits that use the most relays, PPMURelay on the ATE digital board is used to replace the physical relays in these peripheral circuits. This replacement can reduce the number of physical relays, reduce the complexity of the test system, and greatly increase the number of DUTs tested and the efficiency of ATE testing.

[0061] Specifically, the physical relay in the pull-up circuit connected to the digital IO (Input / Output) pin of the chip is replaced with the PPMU Relay of the ATE digital board.

[0062] The pull-up circuit plays an important role in digital circuits. It ensures that the circuit can maintain a certain level when the input signal is unstable or missing. The PPMU Relay of the ATE digital board is highly accurate, programmable, and easy to control, which can well meet the functional requirements of the relay in the pull-up circuit. Therefore, when performing relay replacement analysis, it is preferred to replace the physical relay in the pull-up circuit connected to the chip digital IO pin with the PPMU Relay of the ATE digital board.

[0063] PPMU Relay refers to the relay in the Per Pin Parameter Measurement Unit on the ATE digital board. PPMU is an important functional module on the ATE board, which provides programmable digital IO pin parameter measurement function. PPMU can accurately control voltage and current, and measure the current and voltage response of the device under test at the same time. This capability enables PPMU to provide stable test conditions during the test process and accurately measure the performance of the device under test. In the PPMU of the ATE digital board, Relay is used to switch the connection state of the circuit. It can open or close the circuit according to the test requirements, thereby achieving precise control of the device under test.

[0064] In addition, the chip digital IO pins are the key interface for the chip to communicate and control with external devices. These pins usually have bidirectional functions, which can output digital signals to external devices and receive digital signal inputs from external devices. The pull-up circuit is a circuit that clamps an uncertain signal at a high level through a resistor. This circuit is usually used to improve the stability and reliability of the signal. The resistor in the pull-up circuit plays the role of current limiting and clamping. The pull-up resistor pulls the IO pin to VDD when it is not driven, ensuring that it is in a high-level state, preventing the pin from being suspended and causing an unstable or unpredictable level state, and improving the circuit's anti-interference ability, reducing the impact of external noise on the IO signal pin.

[0065] A physical relay is an electrical device used to control a circuit. It can convert a small current into a large current, thereby controlling the on and off of the circuit. A physical relay is mainly composed of an electromagnet and a switch. When the electromagnet is energized, a magnetic field is generated, causing the switch to close, thereby controlling the on and off of the circuit. It is worth noting that physical relays have the advantages of simple and reliable operation and strong anti-interference ability; but they also have disadvantages such as large size, high power consumption, and high noise.

[0066] During the chip testing process, using the PPMU Relay of the ATE digital board to replace the physical relays in the peripheral circuit can improve the test accuracy. Since the PPMU Relay has higher control accuracy and measurement accuracy, it can provide more stable test conditions, thereby improving the accuracy of the test; and it can reduce costs. Using the PPMU Relay of the ATE digital board can reduce the demand for physical relays, thereby reducing the test cost; secondly, it can also improve the test efficiency. Since the ATE digital board has a large number of digital IO channels, it can replace enough physical relays in the peripheral circuit to achieve more parallel measurement of DUTs, which can significantly improve the test efficiency.

[0067] In a specific embodiment, Figure 3 As shown in the figure, in the pull-up circuit of the digital IO pin of the chip, if the original digital IO pins Out0 to Out15 use 16 physical relays in the pull-up circuit, each DUT needs to use 16 physical relay components without replacement. In this embodiment, the ATE's PPMU Relay can be used for replacement, thereby significantly reducing the space occupied by the physical relay components on the LB (load board) or PC (probe card) PCB, thereby increasing the maximum number of DUTs (devices under test, in this embodiment, the chips under test) that can be designed and tested.

[0068] DUT is the core object in the test process, that is, the device or component to be tested. In chip testing, DUT usually refers to the chip or chip module to be tested.

[0069] S2. Evaluation and Allocation

[0070] Through the process of evaluation and allocation, the number of digital IO channels is obtained and determined according to the digital board configuration resources of ATE.

[0071] The total number of digital IO channels is obtained based on the digital board configuration resources of the ATE, and then the number of IO channels used by each DUT of the design chip test LB or PC to replace the actual physical relay is subtracted.

[0072] Digital IO channels are digital input and output channels. Digital IO channels refer to the channels used for digital signal input and output in ATE. These channels can receive and send digital signals, thereby establishing digital communication between ATE and DUT.

[0073] Specifically, after completing the relay analysis step, the total number of digital IO channels is obtained according to the ATE's digital board configuration resources. However, when calculating the total number of digital IO channels, a key factor needs to be taken into account, namely: when designing a chip test LB or PC, each DUT will use a certain number of PPMU IO channel Relays (programmable power management IO channel relays) to replace the actual physical relays, thereby reducing dependence on physical relays. The PPMU IO channel Relay here refers to a programmable relay channel on the ATE's digital board that is used to replace the actual physical relays to achieve power management and signal on / off control. Each PPMU IO channel Relay can be independently controlled and can accurately adjust the voltage and current to meet the needs of different test scenarios.

[0074] More specifically, first clarify the models and quantities of all digital boards in the ATE, as well as the number of IO channels on each board. Based on the recorded digital board information, add up the number of IO channels on each board to get the total number of ATE digital IO channels; when calculating the total number, consider the redundant or spare resources that the ATE may reserve and subtract these redundant resources. These resources are usually used to deal with possible IO channel failures or future expansion needs, and can be used to replace failed or damaged IO channels in emergency situations.

[0075] Digital IO channel is a key resource on the ATE digital board PPMU, used to transmit digital signals to the DUT. Each digital IO channel can be used as an independent signal channel to send or receive digital signals.

[0076] FT (Functional Test) verifies the functions of the device under test to ensure that it can work normally according to the design requirements. PC (Performance Test) evaluates the performance of the device under test, including speed, power consumption, stability and other aspects. In actual testing, FT and PC may be performed at the same time, or one of them may be selected according to the test requirements.

[0077] In a specific embodiment, in the pull-up circuit of the digital IO pin of the chip, if the original digital IO pins Out0 to Out15 use 16 physical relays in the pull-up circuit. In this embodiment, each DUT will reduce the IO channel requirements corresponding to 16 physical relays, that is, deduct the corresponding digital IO channel signal channels from the total number. Each DUT needs to subtract 16 digital IO channel signal channels to replace the physical relays.

[0078] Specifically, assuming that each DUT needs to subtract 16 digital IO channel signal channels during the test, this means that when testing, the ATE digital board needs to reserve these 16 IO channels for each DUT to replace physical relays. Therefore, when obtaining the number of digital IO channels that ATE can use for other test tasks, the number of IO channels used to replace physical relays needs to be deducted from the total number.

[0079] Through the above detailed steps, the digital IO channel resources of ATE can be evaluated more accurately and efficiently, and the number of IO channels used by each DUT to replace the actual physical relays can be deducted, ensuring that the evaluation and allocation of ATE resources are more accurate and efficient, providing strong support for subsequent testing work.

[0080] S3. Design and Optimization

[0081] The number of DUTs to be measured in parallel by LB or PC is obtained based on the number of remaining IO channel resources of the ATE digital board and the number of channel resources of the DPS power board.

[0082] Specifically, in the design of the test carrier board PCB of ATE (automatic test equipment), the maximum number of DUTs (devices under test) that can be tested simultaneously in the LB (Load Board, FT test carrier) or PC (Probe Card, wafer test probe card) is obtained based on the resources. These resources mainly include the IO channels (input and output channels) on the digital board and the channels of the DPS (Device Power Supply) power board.

[0083] More specifically, the total number of digital IO channels available to the ATE is determined based on the digital board configuration of the ATE. Consider the number of digital IO channels required for each DUT, which includes the IO channels used to connect the digital signal IO pins of the chip and the IO channels used to replace physical relays. Subtract the number of IO channels that have been allocated to other test tasks or reserved as redundant resources from the total number of digital IO channels available to the ATE to obtain the number of digital IO channels remaining in the ATE that can be used for the current test task.

[0084] Determine the number of channels and total power provided by each power board based on the ATE's DPS power board configuration. Analyze the power supply voltage, current, and power required for each DUT, as well as the number of possible power supply channels. Ensure that the number of channels and total power of the DPS power board can meet the power supply requirements of all DUTs under test.

[0085] Calculate the number of DUTs that can be tested in parallel based on the number of digital IO channels remaining in the ATE and the number of digital IO channels required for each DUT.

[0086] In the prior art, according to the design of the peripheral circuit of the schematic diagram, if each DUT needs to use 16 relays to control, then correspondingly, ATE needs to provide 16 relay control signals. Assuming that ATE has a total of 128 relay control signals, then it is calculated that at most 8 DUTs can be tested simultaneously (128 control signals divided by the 16 relays required for each DUT equals 8 DUTs). If each DUT needs to use 16 relays according to the peripheral circuit of the schematic diagram, 16 relay control signals are required. If there are a total of 128 relay control signals, then a total of up to 8 DUTs can be designed (128 control signals / 16 relays = 8 DUTs).

[0087] However, if the method of increasing the number of DUTs that can be tested in parallel on a chip according to the present invention is adopted and the physical relays in the peripheral circuit of the schematic diagram are replaced by the digital IO channel of ATE, a greater number of DUTs that can be tested in parallel can be designed.

[0088] In a specific embodiment, when the method of increasing the number of DUTs to be tested on a chip is used, assuming that the chip has a total of 22 digital signal IO pins, each DUT needs to be connected to 22 ATE digital IO channels during testing. In addition, since the ATE IO channels are also needed to replace the physical relays, each DUT also needs an additional 16 IO channel signals. In this way, each DUT needs a total of 38 ATE IO channels during testing.

[0089] If the ATE has a total of 1024 IO channels, then 26 parallel-measured DUTs can be designed based on this number (1024 IO channels divided by 38 IO channels required for each DUT equals 26 DUTs, and an integer is taken here because there cannot be partial DUTs). In this way, there is no need to be limited by the placement area of ​​the physical relay components in the schematic peripheral circuit on the probe card PCB, so more parallel-measured DUTs can be designed.

[0090] By adopting the method of increasing the number of DUTs that can be measured in parallel on a chip according to the present embodiment, it is possible to achieve that the area of ​​the physical relay components in the peripheral circuit of the schematic diagram on the probe card PCB (printed circuit board) is no longer limited. Since the digital IO channel of the ATE is integrated internally, more DUTs can be designed and measured in parallel more accurately and efficiently, and the resources of the ATE can be fully utilized, thereby improving the test efficiency and accuracy. Specifically, by accurately calculating the ATE resources (such as IO channel) required for each DUT (unit under test) and fully utilizing the resources of the ATE, a higher parallel processing capability is achieved. This solution allows the number of DUTs that can be measured to be flexibly adjusted according to the test requirements, thereby achieving optimal test efficiency in different test scenarios. Since more DUTs can be tested at the same time, the test cycle is significantly shortened and the test capacity is improved.

[0091] By increasing the number of chips and measuring DUTs, the effective connection between ATE (automatic test equipment) and Waferdie (wafer die) can be achieved, so as to perform CP testing (chip probe testing). Specifically, the probe tail of each DUT (device under test) on the CP probe card PCB (printed circuit board) will lead to a PAD (pad), and these PADs are connected to the corresponding board signal resources of ATE through PogoTower (Pogo Pin Tower).

[0092] When the probe is inserted into the corresponding PAD of the wafer die, an electrical connection is established between the ATE and the wafer die. In this way, the ATE can perform CP test (chip probe test) on the wafer die by sending and receiving signals to verify whether its functions and performance meet the design requirements.

[0093] Specifically, the ATE board provides the signal resources required for various tests, including IO (input and output) signals, DPS (programmable power supply) signals, and Relay control (relay control) signals.

[0094] It is worth noting that the more DUTs are designed on the probe card, the more efficient the ATE is in implementing chip parallel testing. Because ATE can test multiple DUTs simultaneously, increasing the number of DUTs can significantly increase test throughput, thereby shortening test time.

[0095] In addition, as test efficiency improves and test time decreases, the required test equipment and labor costs will also be reduced accordingly, thereby reducing the overall test cost.

[0096] Among them, CP stands for Chip Probe (wafer test), and the CP probe card is a special device for chip testing. It directly connects with the chip on the wafer through the probe to realize the chip testing. PCB stands for Printed Circuit Board (printed circuit board), which is the carrier for electrical connection between various components in electronic equipment.

[0097] On the probe card, each DUT (chip under test) has a corresponding probe, and the tail of these probes will be connected to the PAD (pad) on the PCB. The PAD is used to make an electrical connection with the PogoTower (Pogo Pin Tower) or other test equipment. The PogoTower is a connection device that establishes an electrical connection with the ATE at one end and the PAD on the probe card at the other end through a series of Pogo Pins (spring pins), thereby establishing an electrical connection between the ATE and the DUT.

[0098] Board signal resources refer to: ATE is composed of multiple boards, which provide signal resources required for various tests, such as IO (input and output) signals, DPS (programmable power supply) signals, Relay control (relay control) signals, etc. Wafer die refers to: Wafer (wafer) is a basic material in the semiconductor manufacturing process, and die (crystal) is a single chip obtained after cutting on the wafer.

[0099] The corresponding PAD of the wafer die means that each chip (die) on the wafer has a corresponding PAD, which is used to establish an electrical connection with the probes on the probe card for testing.

[0100] This solution achieves a number of significant technical effects through innovative relay replacement strategies and efficient use of ATE (automatic test equipment) resources. It not only optimizes hardware design, but also greatly improves the parallel processing capability and overall efficiency of chip testing. Directly connecting chip signal pins through digital IO channels reduces interference and attenuation in the signal transmission path, and improves test accuracy and stability. Due to the shortened test cycle and increased test capacity, the test cost of each DUT is reduced.

[0101] In a specific embodiment, a system for increasing the number of DUTs measured by a chip of the present invention includes:

[0102] Analysis module: According to the chip test schematic diagram, analyze the peripheral circuit structure to perform peripheral circuit relay analysis;

[0103] Calculation module: obtain the number of digital input and output channels according to the resources of the automatic test equipment;

[0104] The number of chips to be tested in parallel is calculated based on the power resources of the automatic test equipment and the number of digital input and output channels obtained.

[0105] In terms of saving PCB space, this solution uses a digital IO channel to directly connect the chip signal pins, replacing the traditional physical relay array, significantly reducing the number of components and space occupied on the probe card PCB. Due to the reduction of components such as relays, the layout of the probe card is more compact, which is conducive to achieving higher probe density and smaller probe spacing, thereby supporting smaller chip testing. The saved PCB space means that smaller probe cards can be used, reducing material costs and production costs. In short, the present invention saves PCB space, improves parallel processing capabilities, improves overall efficiency, and reduces testing costs through a clever relay replacement strategy and efficient use of ATE resources, thereby promoting the advancement of chip testing technology and injecting new vitality into the development of the chip industry.

[0106] The above schematically describes the invention and its implementation methods, which is not restrictive. Without departing from the spirit or basic features of the invention, the invention can be implemented in other specific forms. What is shown in the accompanying drawings is only one of the implementation methods of the invention. The actual structure is not limited to this, and any figure mark in the claims should not limit the claims involved. Therefore, if a person of ordinary skill in the art is inspired by it, without departing from the purpose of the invention, a structural method and an embodiment similar to the technical solution are designed without creativity, which should all fall within the scope of protection of this patent. In addition, the word "including" does not exclude other elements or steps, and the word "one" before the element does not exclude the inclusion of "multiple" elements. The multiple elements stated in the product claim can also be implemented by one element through software or hardware. The words first, second, etc. are used to indicate names, and do not indicate any specific order.

Claims

1. A method for improving the number of chips and measuring DUTs, comprising the following steps: Conduct peripheral circuit relay analysis based on chip test schematics; Obtain the number of digital input and output channels according to the configuration resources of the digital board of the automatic test equipment; The number of chips to be tested in parallel is calculated based on the channel resources of the power board of the automatic test equipment and the number of digital input and output channels obtained.

2. The method for increasing the number of DUTs measured by a chip according to claim 1, characterized in that: The peripheral circuit relay analysis is to analyze the relay signal control of the chip test schematic circuit in the peripheral circuit by using the programmable relay on the digital board of the automatic test equipment.

3. The method for increasing the number of DUTs measured by a chip according to claim 2, characterized in that: The process of the peripheral circuit relay analysis is: analyzing the peripheral circuit according to the chip test schematic diagram to find out the peripheral local circuit that uses the most relay components.

4. The method for increasing the number of DUTs measured by a chip according to claim 1, characterized in that: The process of obtaining the number of digital input and output channels of the automatic test equipment is as follows: Get the total number of digital input and output channels of automatic test equipment; The number of digital input and output channels is obtained by subtracting the number of input and output channels of the physical relays required for each chip under test on the load board or probe card in the chip test design from the total number of digital input and output channels.

5. The method for increasing the number of DUTs measured by a chip according to claim 4, characterized in that: The process of obtaining the total number of digital input and output channels of the automatic test equipment is as follows: According to the digital board configuration resources of the automatic test equipment, the number of input and output channels on each digital board is accumulated to obtain the total number of digital input and output channels of the automatic test equipment.

6. The method for increasing the number of DUTs measured by a chip according to claim 5, characterized in that: The digital board configuration resources of the automatic test equipment include the models and quantities of the digital boards equipped by the automatic test equipment and the quantities of input and output channels configured on each digital board.

7. The method for increasing the number of DUTs measured by a chip according to claim 1, characterized in that: The number of chips tested in parallel is the number of chips that can be tested simultaneously on a load board or a probe card, calculated based on the resources; the resources include the number of input and output channels provided by the digital board and the channel resources of the dynamic power supply board.

8. The method for increasing the number of DUTs measured by a chip according to claim 7, characterized in that: The step of obtaining the number of chips to be tested in parallel comprises: The number of input and output channels required for other test tasks and the number of redundant input and output channels reserved to cope with potential demands are subtracted from the total number of digital input and output channels of the automatic test equipment to obtain the number of remaining digital input and output channels of the automatic test equipment.

9. The method for increasing the number of DUTs measured by a chip according to claim 8, characterized in that: The step of obtaining the number of chips to be tested in parallel comprises: Based on the obtained number of remaining digital input and output channels of the automatic test equipment and the number of digital input and output channels required to be occupied by each chip under test during the test process, the number of chips under test that can be tested in parallel is calculated; The calculation process is as follows: determine the number of input and output channels of the automatic test equipment that each chip under test needs to occupy during the test; obtain the number of remaining digital input and output channels of the automatic test equipment; divide the number of remaining digital input and output channels of the automatic test equipment by the number of input and output channels required for each chip under test, and take the integer result to obtain the number of chips under test for parallel testing.

10. A system for improving chip and DUT number measurement, comprising: Analysis module: According to the chip test schematic diagram, analyze the peripheral circuit structure to perform peripheral circuit relay analysis; Calculation module: obtain the number of digital input and output channels according to the resources of the automatic test equipment; calculate the number of chips to be tested in parallel according to the power resources of the automatic test equipment and the obtained number of digital input and output channels.

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