Clock taming method and device, time-frequency equipment and storage medium

Abstract

The present application is applicable to the field of communication technology and provides a clock taming method, apparatus, time-frequency device and storage medium, wherein the method comprises: obtaining a first-second pulse signal from a satellite; using the first-second pulse signal as a reference source, employing a first taming method to tame a local second-second pulse signal until the accuracy reaches a first threshold; employing a second taming method to tame the second-second pulse signal until the accuracy reaches a second threshold, wherein the speed of the first taming method is greater than that of the second taming method, and the accuracy of the first taming method is less than that of the second taming method.

Description

Technical Field

[0001] The present application relates to the field of communications, and in particular to a clock taming method and apparatus, a time-frequency device, and a computer-readable storage medium. Background Art

[0002] Clock discipline is a technique that uses an external reference signal to correct a local clock. For example, a time-frequency device can receive a high-accuracy pulse-per-second (PPS) signal from a satellite and compare it with the clock signal generated by a local clock source to ensure that the local clock signal is consistent with the PPS signal from the satellite.

[0003] During the clock taming process, there is often a conflict between the taming speed and accuracy, making it difficult to achieve fast and highly accurate clock taming. Summary of the Invention

[0004] The embodiments of the present application provide a clock taming method and apparatus, a time-frequency device, and a computer-readable storage medium, which can solve the problem in related technologies of difficulty in achieving fast and highly accurate clock taming.

[0005] In a first aspect, an embodiment of the present application provides a clock taming method, which includes: obtaining a first-second pulse signal from a satellite; using the first-second pulse signal as a reference source, using a first taming method to tame a local second-second pulse signal until the accuracy reaches a first threshold; using a second taming method to tame the second-second pulse signal until the accuracy reaches a second threshold, the speed of the first taming method is greater than that of the second taming method, and the accuracy of the first taming method is less than that of the second taming method.

[0006] In a second aspect, an embodiment of the present application provides a clock taming device, which includes: an acquisition module for acquiring a first-second pulse signal from a satellite; a first taming module for taming a local second-second pulse signal using a first taming method with the first-second pulse signal as a reference source until the accuracy reaches a first threshold; a second taming module for taming the second-second pulse signal using a second taming method until the accuracy reaches a second threshold, the speed of the first taming method is greater than that of the second taming method, and the resolution of the first taming method is less than that of the second taming method.

[0007] In a third aspect, an embodiment of the present application provides a time-frequency device, comprising a memory, a processor, and a computer program stored in the memory and executable by the processor. When the processor executes the computer program, the clock taming method described in the first aspect above is implemented.

[0008] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the clock taming method described in the first aspect above.

[0009] In a fifth aspect, an embodiment of the present application provides a computer program product. When the computer program product is run on a time-frequency device, the time-frequency device executes the clock taming method described in the first aspect above.

[0010] Compared with the prior art, the embodiments of the present application have the following advantages: by combining two different taming methods, in the initial stage of taming, the accuracy requirement is not high, and the first taming method with faster speed but lower accuracy is used to tame the clock until the accuracy reaches a first threshold and enters the subsequent stage of taming. In the subsequent stage, the accuracy requirement becomes higher, and the second taming method with slower speed but higher accuracy is used to tame the clock until the accuracy reaches a second threshold and the taming is completed, thereby taking advantage of the strengths of the two taming methods and compensating for their weaknesses, thereby achieving fast and accurate clock taming. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0012] Figure 1 This is a schematic diagram of the structure of a time-frequency device provided in one embodiment of the present application;

[0013] Figure 2 This is a flowchart of a clock taming method provided in one embodiment of the present application;

[0014] Figure 3 It is a schematic diagram of the taming curve of the successive approximation method in the related art;

[0015] Figure 4 It is a schematic diagram of the taming curve of the slow adjustment of the PID method in the related art;

[0016] Figure 5 It is a schematic diagram of the taming curve of overshoot generated by the PID method in the related art;

[0017] Figure 6 This is a schematic diagram of a taming curve of a clock taming method provided in an example of this application;

[0018] Figure 7 Schematic diagram of the structure of a clock taming device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0019] In the following description, specific details such as specific system structures and techniques are provided for purposes of illustration rather than limitation to facilitate a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid obscuring the description of the present application with unnecessary detail.

[0020] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or collections thereof.

[0021] It will also be understood that the term "and / or" used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0022] As used in this specification and the appended claims, the term "if" can be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0023] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0024] References to "one embodiment" or "some embodiments" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. The terms "including," "comprising," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized.

[0025] Figure 1 FIG2 shows a block diagram of a partial structure of a time-frequency device provided by an embodiment of the present application. Figure 1 The time and frequency device includes: a processor 10, a memory 20, a satellite receiver 30 and a local clock source 40. The processor 10 is connected to the memory 20, the satellite receiver 30 and the local clock source 40. It can be understood by those skilled in the art that Figure 1 The structure of the time-frequency device shown in the figure does not constitute a limitation on the time-frequency device, and may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.

[0026] The following combination Figure 1 A detailed introduction to the various components of the time-frequency equipment:

[0027] The processor 10 is the control center of the time-frequency device and can execute various functions and process data by running programs stored in the memory 20. The processor 10 can be a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a microcontroller unit (MCU), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0028] The memory 20 is used to store an operating system, application programs, a boot loader, data, and other programs, such as the program code of a computer program. The memory 20 can also be used to temporarily store data required for and generated by executing the program. The memory 20 can include high-speed random access memory and non-volatile memory, such as a flash memory, a hard disk, a multimedia card, a card-type memory, etc.

[0029] In some embodiments, the processor 10 and the memory 20 may be integrated together.

[0030] Satellite receiver 30 is used to receive satellite signals. Satellite receiver 30 can directly output the satellite signals to processor 10, which then decodes the satellite signals to obtain the message information and pulse-second signals. Alternatively, satellite receiver 30 can independently decode the satellite signals to obtain the message information and pulse-second signals, and then output the message information and pulse-second signals to processor 10.

[0031] The local clock source 40 generally includes a crystal oscillator, and is used to generate a local clock signal.

[0032] The clock taming method provided in the embodiments of the present application can be implemented as a computer software program. For example, the embodiments of the present application provide a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for executing the method shown in the flowchart. When the computer program is executed by the processor 10, the various functions defined in the clock taming method provided in the embodiments of the present application are implemented.

[0033] Figure 2 A schematic flow chart of a clock taming method provided in an embodiment of the present application is shown. As an example but not a limitation, the method can be applied to the above-mentioned time and frequency device.

[0034] S1: Get the first second pulse signal from the satellite.

[0035] The first second pulse signal from the satellite can be received by a satellite receiver, and then the first second pulse signal can be obtained from the satellite receiver.

[0036] S2: Using the first pulse per second signal as a reference source, a first training method is used to train the local second pulse per second signal until the accuracy reaches a first threshold.

[0037] S3: Using a second training method to train the second pulse per second signal until the accuracy reaches a second threshold.

[0038] The first training method has a higher speed than the second training method, and a lower accuracy than the second training method. Specifically, the first training method may be a successive approximation method, and the second training method may be a proportional-integral-derivative (PID) method.

[0039] The ultimate goal of clock training is to align the second-second pulse signal with the first-second pulse signal. This is achieved by calculating the deviation between the second and first pulse signals. Using a specific training method, a corresponding control variable is output to the local clock source generating the second-second pulse signal, controlling the local clock source to adjust the second-second pulse signal. This process is repeated until the deviation meets the preset requirements. This deviation value can also be referred to as the accuracy of clock training. In theory, the target for clock training should be 0. In practice, the target is typically set to a very small value, also known as the lock threshold or design accuracy. When the accuracy reaches the lock threshold, clock training is considered complete, and a lock flag is output.

[0040] Clock taming methods include successive approximation method and PID method.

[0041] The schematic diagram of the taming curve of the successive approximation method is as follows Figure 3 As shown, the advantage of this method is that it is fast and can accurately reach the locking threshold according to the set time; Figure 3 As can be seen from the right half of the middle curve, even after the accuracy has reached the lock threshold and the clock is tamed, the actual deviation value still jumps slightly, giving a sense of "stepping", resulting in low resolution and accuracy.

[0042] The schematic diagram of the taming curve of the PID method is as follows Figure 4 As shown in the figure, the advantages of this method are high resolution and accuracy, and the deviation value is smooth without "step feeling". The disadvantage is that it is slow. If it is necessary to complete the taming quickly, the control coefficient (including at least one of the proportional coefficient, integral coefficient and differential coefficient) is often set to a large value, resulting in overshoot. The corresponding taming curve is shown in the figure. Figure 5 As shown, the device may be damaged, and the overshoot itself takes a while to disappear, making it impossible to tame it quickly.

[0043] In this embodiment, two different training methods are combined. In the initial training phase, when accuracy requirements are low, the clock is trained using the first training method, which is faster but less accurate, until the accuracy reaches a first threshold, and then the training phase begins. In the subsequent phase, when accuracy requirements become higher, the clock is trained using the second training method, which is slower but more accurate, until the accuracy reaches a second threshold (i.e., the locking threshold), completing the training phase.

[0044] The first threshold can be determined based on the second threshold and at least one of the parameters of the second training method. The correction value can be determined based on at least one of the proportional coefficient, integral coefficient, and differential coefficient of the second training method. Specifically, a preset threshold corresponding to the control coefficient can be determined based on experiments, experience, calculations, etc., and the control coefficient used in the clock training PID method can be compared with the preset threshold to obtain a comparison result; the correction value can be determined based on the comparison result. After determining the correction value, the first threshold can be calculated based on the correction value and the second threshold. For example, the first threshold can be obtained by adding the exponent of the second threshold to the correction value.

[0045] Alternatively, a weighted sum of the second threshold and the free oscillation accuracy of the crystal may be calculated as the first threshold. The crystal is used to generate a local second pulse signal, and its free oscillation accuracy may be obtained according to its specification data.

[0046] The weighted sum calculation can be performed directly using the second threshold and the free-run accuracy itself. Because precision / accuracy values ​​are very small, they are typically expressed in scientific notation, with the exponent being more important than the significand. For example, the significand is often set to 1. Therefore, to simplify the calculation, the weighted sum of the second threshold and the exponent of the free-run accuracy can be calculated, and the result can be rounded to obtain the exponent of the first threshold. The significand is then set to 1 to obtain the first threshold.

[0047] The weight of the second threshold is calculated using the proportional coefficient of the second taming method. Specifically, the weight of the second threshold can be a weighted sum of a fixed value and the proportional coefficient of the second taming method, or the product of the proportional coefficient and the preset weight can be calculated as the weight of the second threshold.

[0048] For example, the calculation formula of the first threshold may be: second threshold*(0.1*60%+proportional coefficient*20%)+free oscillation accuracy of the crystal / 100*20%.

[0049] For example, the second threshold is 1e-11. Using any of the above methods, the first threshold is calculated to be 1e-10. The corresponding taming curve is as follows: Figure 6 shown.

[0050] Through the implementation of this embodiment, two different training methods are combined, thereby taking advantage of the strengths of the two training methods and making up for their weaknesses, thereby achieving fast and accurate clock training.

[0051] Figure 7 A schematic structural diagram of a clock training device provided in an embodiment of the present application is shown. The clock training device includes an acquisition module 11 , a first training module 12 and a second training module 13 .

[0052] The acquisition module 11 is used to acquire the first pulse second signal from the satellite.

[0053] The first taming module 12 is configured to tame the local second pulse per second signal using the first pulse per second signal as a reference source and a first taming method until the accuracy reaches a first threshold.

[0054] The second taming module 13 is used to tame the second pulse per second signal using a second taming method until the accuracy reaches a second threshold. The speed of the first taming method is greater than that of the second taming method, and the resolution of the first taming method is less than that of the second taming method.

[0055] It should be noted that the information interaction, execution process, etc. between the above-mentioned devices / modules / units are based on the same concept as the method embodiment of this application. Their specific functions and technical effects can be found in the method embodiment section and will not be repeated here.

[0056] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0057] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0058] An embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in the above-mentioned various method embodiments can be implemented.

[0059] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the process of the above-mentioned embodiment method by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by a processor, it can implement the steps of each of the above-mentioned method embodiments. The computer program includes computer program code, which can be in source code form, object code form, executable file, or some intermediate form. The computer-readable medium can at least include: any entity or device capable of carrying computer program code to the camera / time-frequency device, recording medium, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal, and software distribution medium. For example, a USB flash drive, mobile hard drive, magnetic disk, or optical disk. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electric carrier signals or telecommunication signals.

[0060] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0061] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0062] In the embodiments provided in this application, it should be understood that the disclosed devices / network equipment and methods can be implemented in other ways. For example, the device / network equipment embodiments described above are merely illustrative. For example, the division of the modules or units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0063] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0064] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A clock taming method, characterized in that: The method comprises: Acquire the first second pulse signal from the satellite; Using the first pulse per second signal as a reference source, a first training method is used to train the local second pulse per second signal until the accuracy reaches a first threshold; Using a second training method to train the second pulse per second signal until the accuracy reaches a second threshold, the speed of the first training method is greater than that of the second training method, and the accuracy of the first training method is less than that of the second training method; Wherein, the second taming method is the proportional-integral-differential method; The method of taming the local second pulse second signal using the first pulse second signal as a reference source and the first taming method until the accuracy reaches a first threshold further includes: The first threshold is determined according to at least one of the second threshold and a parameter of the second training method.

2. The method according to claim 1, wherein The first taming method is a successive approximation method.

3. The method according to claim 1, wherein The determining the first threshold according to the second threshold and at least one of the parameters of the second taming method includes: determining a correction value according to at least one of a proportional coefficient, an integral coefficient, and a differential coefficient of the second taming method; The first threshold is calculated according to the correction value and the second threshold.

4. The method according to claim 1, wherein The determining the first threshold according to the second threshold and at least one of the parameters of the second taming method includes: A weighted sum of the second threshold and the free oscillation accuracy of the crystal is calculated as the first threshold, wherein the weight of the second threshold is calculated using the proportional coefficient of the second taming method.

5. The method according to claim 4, wherein The weight of the second threshold is a weighted sum of a fixed value and a proportional coefficient of the second taming method.

6. A clock taming device, characterized in that: The device comprises: An acquisition module, used for acquiring the first second pulse signal from the satellite; a first taming module, configured to tame the local second pulse signal using the first pulse signal as a reference source and a first taming method until the accuracy reaches a first threshold; a second taming module, configured to tame the second pulse per second signal using a second taming method until the accuracy reaches a second threshold, wherein the speed of the first taming method is greater than that of the second taming method, and the resolution of the first taming method is less than that of the second taming method; Wherein, the second taming method is the proportional-integral-differential method; The method of taming the local second pulse second signal using the first pulse second signal as a reference source and the first taming method until the accuracy reaches a first threshold further includes: The first threshold is determined according to at least one of the second threshold and a parameter of the second training method.

7. A time-frequency device comprising a memory, a processor, and a computer program stored in the memory and executable by the processor, characterized in that: When the processor executes the computer program, the method according to any one of claims 1 to 5 is implemented.

8. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 5 is implemented.

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