Memory management method and storage device

Abstract

The invention provides a memory management method and a storage device. The method comprises the following steps: determining a read voltage level according to an offset; reading a first entity unit based on the read voltage level to obtain first data; obtaining first quality evaluation information corresponding to the first entity unit according to the first data; judging whether the first entity unit meets a preset condition or not according to the first quality evaluation information; if the first entity unit meets the preset condition, determining the first entity unit as a first type of entity unit; and storing the system data in the first class entity unit. Therefore, the operation stability of the storage device can be effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a memory management method and a storage device. Background Art

[0002] As the usage time and frequency of use increase, the storage units in the storage device will gradually wear out, which may cause the reliability of the data stored in the physical block to decrease, and may even cause a read failure. Generally speaking, if a read error occurs in a physical block used to store user data in a storage device, since the system is still in a normal operating state, the memory controller can try to correct the error by adjusting the read voltage level, etc. However, when a read error occurs in a physical block used to store system data in a storage device, since the system data cannot be read smoothly, the memory controller will not be able to operate normally, resulting in a system crash.

[0003] Therefore, how to improve the reliability of storing system data in a storage device, and thus improve the stability of the operation of the storage device, is a problem that needs to be solved urgently. Summary of the invention

[0004] The present invention provides a memory management method and a storage device, which can solve the above problems and effectively improve the operation stability of the storage device.

[0005] An embodiment of the present invention provides a memory management method, which is used for a storage device, wherein the storage device includes a memory module, the memory module includes a plurality of physical units, and the memory management method includes: determining a read voltage level according to an offset; reading a first physical unit among the plurality of physical units based on the read voltage level to obtain first data; obtaining first quality assessment information corresponding to the first physical unit according to the first data, wherein the first quality assessment information reflects a quality status of the first physical unit assessed based on the read voltage level; judging whether the first physical unit meets a preset condition according to the first quality assessment information; determining the first physical unit as a first-type physical unit if the first physical unit meets the preset condition; and storing system data in the first-type physical unit.

[0006] An embodiment of the present invention further provides a storage device, which includes a connection interface, a memory module and a memory controller. The connection interface is used to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory module includes a plurality of physical units, and the memory controller is used to perform: step a: determining a read voltage level according to an offset; step b: reading a first physical unit among the plurality of physical units based on the read voltage level to obtain first data; step c: obtaining first quality assessment information corresponding to the first physical unit according to the first data, wherein the first quality assessment information reflects the quality status of the first physical unit assessed based on the read voltage level; step d: judging whether the first physical unit meets a preset condition according to the first quality assessment information; step e: determining the first physical unit as a first-class physical unit if the first physical unit meets the preset condition; and step f: storing system data in the first-class physical unit.

[0007] Based on the above, after determining the read voltage level according to the offset, the read voltage level can be used to read the first physical unit to obtain the first data. According to the first data, the first quality assessment information corresponding to the first physical unit can be obtained. In particular, the first quality assessment information can reflect the quality state of the first physical unit evaluated based on the read voltage level. According to the first quality assessment information, if the first physical unit is determined to meet the preset condition, the first physical unit can be determined as a first-class physical unit. Thereafter, the system data can be stored in the first-class physical unit. In this way, the operational stability of the storage device can be effectively improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic diagram of a data storage system according to an embodiment of the present invention;

[0009] Figure 2 is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0010] Figure 3 is a schematic diagram of a management memory module according to an embodiment of the present invention;

[0011] Figure 4 is a schematic diagram showing a shift in the threshold voltage of a memory cell according to an embodiment of the present invention;

[0012] Figure 5 is a schematic diagram of critical voltage distribution corresponding to sub-entity units of different masses according to an embodiment of the present invention;

[0013] Figure 6is a schematic diagram of obtaining a read voltage level according to an offset according to an embodiment of the present invention;

[0014] Figure 7 is a schematic diagram showing distribution of threshold voltages of a plurality of first memory cells compared to a read voltage level according to an embodiment of the present invention;

[0015] Figure 8 is a schematic diagram of determining a first type of entity unit from a plurality of candidate entity units according to an embodiment of the present invention;

[0016] Fig. 9 is a flowchart of a memory management method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0017] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0018] Figure 1 is a schematic diagram of a data storage system according to an embodiment of the present invention. Figure 1 , the data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smart phone, a tablet computer, a notebook computer, a desktop computer, an industrial computer, a game console, a server, or a computer system disposed in a specific carrier (such as a vehicle, an aircraft, or a ship), and the type of the host system 11 is not limited thereto. In addition, the storage device 12 may include a solid state drive, a USB flash drive, a memory card, or other types of non-volatile storage devices.

[0019] The storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the storage device 12 to the host system 11. For example, the connection interface 121 can support an embedded Multi-Media Card (eMMC), a Universal Flash Storage (UFS), a Peripheral Component Interconnect Express (PCI Express), a Non-Volatile Memory Express (NVM express), a Serial Advanced Technology Attachment (SATA), a Universal Serial Bus (USB), or other types of connection interface standards. Therefore, the storage device 12 can communicate with the host system 11 via the connection interface 121 (e.g., exchange signals, instructions, and / or data).

[0020] The memory module 122 is used to store data. For example, the memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also called threshold voltage). For example, the memory module 122 may include a single level cell (SLC) NAND type flash memory module, a multi level cell (MLC) NAND type flash memory module, a triple level cell (TLC) NAND type flash memory module, a quad level cell (QLC) NAND type flash memory module and / or other memory modules having the same or similar characteristics.

[0021] The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 can be regarded as the control core of the storage device 12 and is used to control the storage device 12. For example, the memory controller 123 can be used to control or manage the entire or partial operation of the storage device 12. For example, the memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSP), programmable controllers, application-specific integrated circuits (ASIC), programmable logic devices (PLD) or other similar devices or combinations of these devices. In one embodiment, the memory controller 123 may include a flash memory controller.

[0022] The memory controller 123 may send a command sequence to the memory module 122 to access the memory module 122. For example, the memory controller 123 may send a write command sequence to the memory module 122 to instruct the memory module 122 to store data in a specific storage unit. For example, the memory controller 123 may send a read command sequence to the memory module 122 to instruct the memory module 122 to read data from a specific storage unit. For example, the memory controller 123 may send an erase command sequence to the memory module 122 to instruct the memory module 122 to erase the data stored in a specific storage unit. In addition, the memory controller 123 may also send other types of command sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations, which are not limited by the present invention. The memory module 122 may receive the command sequence from the memory controller 123 and access the storage unit inside the memory module 122 according to the command sequence.

[0023] Figure 2 FIG. 1 is a schematic diagram of a memory controller according to an embodiment of the present invention. Figure 1 and Figure 2 The memory controller 123 includes a host interface 21, a memory interface 22 and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 through the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0024] The memory control circuit 23 is connected to the host interface 21 and the memory interface 22. The memory control circuit 23 may be used to control or manage the whole or part of the operation of the memory controller 123. For example, the memory control circuit 23 may communicate with the host system 11 through the host interface 21 and access the memory module 122 through the memory interface 22. For example, the memory control circuit 23 may include a control circuit such as an embedded controller or a microcontroller. In the following embodiments, the description of the memory control circuit 23 is equivalent to the description of the memory controller 123.

[0025] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuit 23 and used to cache data. For example, the buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122.

[0026] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to perform encoding and decoding on the data to ensure the correctness of the data. For example, the decoding circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check Code (LDPC code), BCH code, Reed-Solomon code (RS code), Exclusive OR (XOR) code, etc. In one embodiment, the memory controller 123 may also include various other types of circuit modules (such as power management circuits, etc.), which are not limited by the present invention.

[0027] Figure 3 FIG. 1 is a schematic diagram of a management memory module according to an embodiment of the present invention. Figures 1 to 3 The memory module 122 includes a plurality of physical units 301 ( 1 ) to 301 (B). Each physical unit includes a plurality of storage cells and is used to store data in a non-volatile manner.

[0028] In one embodiment, a physical unit may include one or more physical erase units. In addition, a physical unit may include multiple sub-physical units. For example, a sub-physical unit may include one or more physical programming units.

[0029] In one embodiment, a physical programming unit may include multiple physical sectors. For example, the data capacity of a physical sector may be 512 bytes (Bytes, B), and a physical programming unit may include 32 physical sectors. However, the data capacity of a physical sector and / or the total number of physical sectors included in a physical programming unit can be adjusted according to practical needs, and the present invention is not limited thereto. In one embodiment, a physical programming unit can be regarded as a physical page. For example, the storage capacity of a physical programming unit may be 16 kilobytes, and the present invention is not limited thereto.

[0030] In one embodiment, a physical programming unit is a minimum unit for synchronously writing data in the memory module 122. For example, when a programming operation (also referred to as a write operation) is performed on a physical programming unit to write data to the physical programming unit, multiple memory cells in the physical programming unit may be synchronously programmed to store corresponding data. For example, when programming a physical programming unit, a write voltage may be applied to the physical programming unit to change the threshold voltage of at least some of the memory cells in the physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in the memory cell.

[0031] In one embodiment, a physical erase unit may include a plurality of physical programming units. The plurality of physical programming units in a physical erase unit may be erased synchronously. For example, when performing an erase operation on a physical erase unit, an erase voltage may be applied to the plurality of physical programming units in the physical erase unit to change the threshold voltage of at least some of the storage cells in the physical programming units. By performing an erase operation on a physical erase unit, the data stored in the physical erase unit may be cleared.

[0032] In one embodiment, the memory control circuit 23 can logically associate the physical units 301(1)-301(A), 301(A+1)-301(B), and 301(B+1)-301(C) with the data area 31, the idle area 32, and the system area 33, respectively. The physical units 301(1)-301(A) in the data area 31 all store data (also called user data) from the host system 11. For example, any physical unit in the data area 31 can store valid data and / or invalid data. The physical units 301(A+1)-301(B) in the idle area 32 do not store data (e.g., valid data).

[0033] In one embodiment, if a physical unit does not store valid data, the physical unit can be associated with the idle area 32. In addition, the physical unit in the idle area 32 can be erased to clear the data in the physical unit. In one embodiment, the physical unit in the idle area 32 is also called an idle physical unit. In one embodiment, the idle area 32 is also called an idle pool.

[0034] In one embodiment, when data is to be stored, the memory control circuit 23 may select one or more physical cells from the idle area 32 and instruct the memory module 122 to store the data in the selected physical cells. After the data is stored in the physical cell, the physical cell may be associated with the data area 31. In other words, one or more physical cells may be used alternately between the data area 31 and the idle area 32.

[0035] In one embodiment, the memory control circuit 23 may configure a plurality of logical units 302(1)-302(D) to map the physical units (i.e., the physical units 301(1)-301(A)) in the data area 31. For example, one logical unit may correspond to one logical block address (LBA) or other logical management unit. One logical unit may be mapped to one or more physical units.

[0036] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in the physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that the physical unit does not currently store any valid data.

[0037] In one embodiment, the memory control circuit 23 may record the mapping relationship between the logical unit and the physical unit in at least one management table (also referred to as a logical-to-physical mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data reading, writing or erasing according to the information in the management table (i.e., the logical-to-physical mapping table).

[0038] In one embodiment, the physical units 301 (B+1) to 301 (C) in the system area 33 can be used to store system data. For example, the system data may include at least one of a boot firmware, a voltage adjustment table (also called a retry table), a logic-to-physical mapping table, a bad block management table, and a valid data management table. The boot firmware may include a boot code or other types of firmware. The memory control circuit 23 may run the boot firmware to enable the storage device 12 to operate normally. The voltage adjustment table may be used to record information related to the adjustment or setting of the read voltage level. For example, the voltage adjustment table may record an offset for adjusting the read voltage level. The memory control circuit 23 may determine or adjust the read voltage level based on the information (e.g., offset) in the voltage adjustment table. The bad block management table may be used to record information for managing damaged physical units (i.e., bad blocks). For example, the memory control circuit 23 may confirm that some physical units in the memory module 122 are damaged physical units (i.e., bad blocks) based on the information in the bad block management table. In one embodiment, the valid data management table may be used to record information related to valid data. For example, the memory control circuit 23 can obtain the amount of valid data or similar information stored in at least some physical units in the memory module 122 according to the valid data management table. In addition, the system data can also include other data or information for maintaining or managing the storage device 12, which is not limited by the present invention.

[0039] In one embodiment, after the memory module 122 is used for a period of time and / or the ambient temperature changes significantly, the memory cells in the memory module 122 may age and / or wear out. In response to the aging and / or wear of the memory cells, the threshold voltage of the memory cells may shift.

[0040] Specifically, the shift of the critical voltage of a memory cell refers to the change of the critical voltage of the memory cell, for example, from a certain voltage position to another voltage position. The shift of the critical voltage of the memory cell may affect the correctness of the data read from the memory cell. For example, suppose that the critical voltage of a memory cell that was originally programmed is greater than a read voltage level (also called a preset read voltage level). However, due to aging and / or wear, the critical voltage of this memory cell may shift to less than the preset read voltage level. Therefore, if this preset read voltage level is continuously used to read this memory cell, an erroneous bit may be read from this memory cell. Alternatively, suppose that the critical voltage of a memory cell that was originally programmed is less than a preset read voltage level. However, due to aging and / or wear, the critical voltage of this memory cell may shift to greater than the preset read voltage level. Therefore, if this preset read voltage level is used to read this memory cell, an erroneous bit may also be read from this memory cell.

[0041] Figure 4FIG. 1 is a schematic diagram showing a shift in the threshold voltage of a memory cell according to an embodiment of the present invention. Figure 4 , assuming that a certain sub-entity unit (also referred to as a target sub-entity unit) in the memory module 122 includes a plurality of memory cells. After programming the memory cells in the target sub-entity unit, the threshold voltage distribution of the plurality of memory cells may include states 401 and 402. For example, the memory cells belonging to state 401 may be regarded as storing a bit "1", and the memory cells belonging to state 402 may be regarded as storing a bit "0". In addition, in one embodiment, the memory cells belonging to states 401 and / or 402 may also be regarded as storing other bits or a combination of multiple bits, which is not limited by the present invention.

[0042] In one embodiment, it is assumed that the read voltage level 41 is a preset read voltage level corresponding to the target sub-physical unit. In the early stage of the use of the target sub-physical unit, since the health of the memory cells in the target sub-physical unit is very good, the read voltage level 41 can be used to accurately distinguish the memory cells belonging to the state 401 and 402. For example, after the read voltage level 41 is applied to the target sub-physical unit, if the critical voltage of a certain memory cell in the target sub-physical unit is less than the read voltage level 41, the memory control circuit 23 can read the bit "1" from the memory module 122 and determine that the memory cell belongs to the state 401. Alternatively, if the critical voltage of a certain memory cell in the target sub-physical unit is greater than the read voltage level 41, the memory control circuit 23 can read the bit "0" from the memory module 122 and determine that the memory cell belongs to the state 402.

[0043] However, after the memory cells in the target sub-physical unit age and / or wear out, the threshold voltages of at least some of the memory cells in the target sub-physical unit may shift. For example, states 411 and 412 may be used to represent the shifted states 401 and 402. Compared to states 401 and 402, the distance between states 411 and 412 is closer and may even overlap each other, thereby increasing the difficulty of identifying whether a memory cell belongs to state 411 or 412.

[0044] by Figure 4 For example, assume that a certain memory cell in the target sub-physical unit belongs to state 412 and is used to store a bit "0". After the voltage shift occurs, the threshold voltage of the memory cell may shift to be less than the read voltage level 41 (e.g. Figure 4In this case, if the read voltage level 41 is continuously used to read data from the target sub-physical unit, the storage unit may be mistakenly identified as belonging to the state 411 and used to store the bit "1". In particular, as the aging and / or wear degree of the storage unit increases, if the read voltage level 41 (i.e., the preset read voltage level corresponding to the target sub-physical unit) is continuously used to read data from the target sub-physical unit, the read data may contain more and more error bits.

[0045] Generally speaking, when subordinate Figure 3 When the data read from the physical unit of the data area 31 or the idle area 32 contains error data (such as an error bit), the memory control circuit 23 can handle the error by using a preset error correction or error handling means. Figure 4 For example, in one embodiment, the memory control circuit 23 can query the memory stored in Figure 3 The memory control circuit 23 can obtain information related to the adjustment or setting of the read voltage level by using the system data (e.g., voltage adjustment table) of the system area 33. The memory control circuit 23 can adjust the read voltage level 41 according to this information, for example, by adding an offset to the read voltage level 41 to obtain the read voltage level 42. Then, the memory control circuit 23 can re-read the target sub-entity unit based on the read voltage level 42 to reduce errors in the read data. Alternatively, more error handling means can also be used to reduce or correct errors in the read data, and the present invention is not limited thereto.

[0046] However, when subordinate to Figure 3 When the data (e.g., system data) read from the physical unit of the system area 33 contains erroneous data (e.g., erroneous bits), the memory control circuit 23 may not be able to read the required system data completely, which may cause the memory control circuit 23 to fail to operate normally. For example, when the memory control circuit 23 is unable to read the correct voltage adjustment table (i.e., system data) from the physical unit of the system area 33, the memory control circuit 23 will not be able to perform the following operations. Figure 4 Similarly, since the voltage adjustment table cannot be obtained, the memory control circuit 23 cannot adjust the read voltage level currently used to read the voltage adjustment table. In this case, it may even cause the storage device 12 to crash.

[0047] In one embodiment, the memory control circuit 23 can screen out the physical units that meet the preset conditions from the memory module 122 through a unique screening mechanism. In particular, the physical units that meet the preset conditions may include physical units with relatively good quality in the memory module 122. In one embodiment, the quality of the physical unit may be positively correlated with the durability and / or reliability of the physical unit. That is, assuming that the quality of a certain physical unit is relatively high in the memory module 122, it means that the durability and / or reliability of this physical unit is also relatively high in the memory module 122. Then, the memory control circuit 23 can store the system data in the physical units that meet the preset conditions (i.e., the physical units with relatively good quality). In this way, the operational stability of the storage device 12 can be effectively improved.

[0048] Figure 5 is a schematic diagram of the critical voltage distribution corresponding to the sub-entity units of different masses according to an embodiment of the present invention. Figure 5 , assuming that after a certain sub-entity unit (also referred to as the first target sub-entity unit) in the programmed memory module 122, the critical voltage distribution corresponding to the memory cells in the first target sub-entity unit includes states 501 and 502. Assume that after another sub-entity unit (also referred to as the second target sub-entity unit) in the programmed memory module 122, the critical voltage distribution corresponding to the memory cells in the second target sub-entity unit includes states 511 and 512. In addition, assume that after another sub-entity unit (also referred to as the third target sub-entity unit) in the programmed memory module 122, the critical voltage distribution corresponding to the memory cells in the third target sub-entity unit includes states 521 and 522. In one embodiment, the distance (i.e., spacing) between states 501 and 502 is greater than the distance (i.e., spacing) between states 511 and 512, and the distance (i.e., spacing) between states 511 and 512 is greater than the distance (i.e., spacing) between states 521 and 522, such as Figure 5 In one embodiment, the distance (i.e., spacing) between state 502 and read voltage level 51 is greater than the distance (i.e., spacing) between state 512 and read voltage level 51, and the distance (i.e., spacing) between state 512 and read voltage level 51 is greater than the distance (i.e., spacing) between state 522 and read voltage level 51, as shown in FIG. Figure 5 shown.

[0049] In one embodiment, after the first target sub-physical unit, the second target sub-physical unit, and the third target sub-physical unit are continuously used (e.g., accessed), even if any two adjacent states in the critical voltage distribution are close to each other due to aging and / or wear of the memory cell (e.g., states 502, 512, and / or 522 are continuously shifted to the left as the memory cell ages and / or wears), the correctness of the data read from the first target sub-physical unit by continuously using the read voltage level 51 may be higher than the correctness of the data read from the second target sub-physical unit by continuously using the read voltage level 51, and the correctness of the data read from the second target sub-physical unit by continuously using the read voltage level 51 may be higher than the correctness of the data read from the third target sub-physical unit by continuously using the read voltage level 51. Therefore, in one embodiment, the memory control circuit 23 may determine that the quality of the first target sub-physical unit is higher than the quality of the second target sub-physical unit, and the quality of the second target sub-physical unit is higher than the quality of the third target sub-physical unit according to the critical voltage distributions corresponding to the first target sub-physical unit, the second target sub-physical unit, and the third target sub-physical unit, respectively.

[0050] In one embodiment, the memory control circuit 23 may preferentially select a physical unit including relatively more physical sub-units with relatively higher quality from the memory module 122 as a physical unit that meets the preset condition. In one embodiment, the memory control circuit 23 may screen out the physical unit that meets the preset condition from the memory module 122 through a unique screening process. Thus, the operation stability of the storage device 12 may be effectively improved.

[0051] In one embodiment, the memory control circuit 23 may determine a read voltage level according to an offset. Then, the memory control circuit 23 may read a certain physical unit (also referred to as a first physical unit) in the memory module 122 based on the read voltage level to obtain data (also referred to as first data). For example, the memory control circuit 23 may add the offset to the preset read voltage level corresponding to the first physical unit to obtain the read voltage level. Then, the memory control circuit 23 may read the first physical unit based on the read voltage level to obtain the first data. The first data may reflect the reading result of reading the first physical unit based on the read voltage level.

[0052] Figure 6 is a schematic diagram showing how to obtain a read voltage level according to an offset according to an embodiment of the present invention. Figure 6, assuming that the read voltage level 61 is a preset read voltage level corresponding to the first physical unit. The memory control circuit 23 may adjust the read voltage level 61 according to the offset ΔV to obtain one of the read voltage levels 62 to 64. For example, the memory control circuit 23 may add the offset ΔV to the read voltage level 61 to obtain the read voltage level 62. Alternatively, the memory control circuit 23 may add twice the offset ΔV (i.e., 2×ΔV) to the read voltage level 61 to obtain the read voltage level 63. Alternatively, the memory control circuit 23 may add three times the offset ΔV (i.e., 3×ΔV) to the read voltage level 61 to obtain the read voltage level 64. It should be noted that the memory control circuit 23 may also adjust the read voltage level 61 according to different offsets to obtain other read voltage levels, and the present invention is not limited thereto.

[0053] In one embodiment, the memory control circuit 23 may obtain quality assessment information (also referred to as first quality assessment information) corresponding to the first physical unit according to the first data. The first quality assessment information may reflect the quality status of the first physical unit assessed based on the read voltage level. For example, the quality status of the first physical unit may reflect the quality of the first physical unit. In addition, the quality of the first physical unit may be positively correlated to the durability and / or reliability of the first physical unit.

[0054] In one embodiment, the memory control circuit 23 may determine whether the first physical unit meets the preset condition according to the first quality evaluation information. If the first physical unit meets the preset condition, the memory control circuit 23 may determine the first physical unit as a specific type of physical unit (also referred to as a first-class physical unit). For example, the first-class physical unit refers to a physical unit with relatively good quality in the memory module 122. Alternatively, in one embodiment, the first-class physical unit refers to a physical unit with relatively high durability and / or reliability in the memory module 122.

[0055] In one embodiment, after determining at least one first-class physical unit, the memory control circuit 23 may store the system data in the first-class physical unit. However, if the first physical unit does not meet the preset condition, the memory control circuit 23 may not determine the first physical unit as the first-class physical unit. In one embodiment, by centrally storing the system data in the selected physical units with relatively good quality (i.e., the first-class physical units), the operation stability of the storage device 12 can be effectively improved.

[0056] In one embodiment, the first quality assessment information may include a count value. In particular, the count value may reflect the total number of sub-entities of a specific type (also referred to as first-class sub-entities) in the first entity unit. In one embodiment, the first-class sub-entities refer to sub-entities of relatively low quality in the first entity unit. Alternatively, in one embodiment, the first-class sub-entities refer to sub-entities of relatively high quality in the first entity unit, depending on practical needs.

[0057] In one embodiment, the memory control circuit 23 may compare the first quality evaluation information (eg, the count value) with a preset value, and then determine whether the first physical unit meets a preset condition according to the comparison result.

[0058] In one embodiment, if the first type of sub-entity unit refers to a sub-entity unit with relatively low quality among the first entity units, and the comparison result reflects that the total number of the first type of sub-entity units is not greater than (e.g., less than or equal to) a preset value, the memory control circuit 23 may determine that the first entity unit meets the preset condition. However, if the first type of sub-entity unit refers to a sub-entity unit with relatively low quality among the first entity units, and the comparison result reflects that the total number of the first type of sub-entity units is greater than the preset value, the memory control circuit 23 may determine that the first entity unit does not meet the preset condition.

[0059] In one embodiment, if the first type of sub-entity unit refers to a sub-entity unit with relatively high quality among the first entity units, and the comparison result reflects that the total number of the first type of sub-entity units is not greater than (e.g., less than or equal to) a preset value, the memory control circuit 23 may determine that the first entity unit does not meet the preset condition. However, if the first type of sub-entity unit refers to a sub-entity unit with relatively high quality among the first entity units, and the comparison result reflects that the total number of the first type of sub-entity units is greater than the preset value, the memory control circuit 23 may determine that the first entity unit meets the preset condition.

[0060] In one embodiment, assuming that the first physical unit includes a sub-physical unit (also referred to as a first sub-physical unit), and the first sub-physical unit includes a plurality of memory cells (also referred to as first memory cells), the memory control circuit 23 can determine whether the first sub-physical unit belongs to the first type of sub-physical unit according to the distribution of the threshold voltages of the plurality of first memory cells compared to the read voltage level.

[0061] In one embodiment, after reading the first physical subunit based on the read voltage level, the memory control circuit 23 may obtain data (also referred to as first sub-data) from the memory module 122. The first sub-data may reflect the reading result of the first physical subunit based on the read voltage level.

[0062] In one embodiment, the memory control circuit 23 may decode the first sub-data through the decoding circuit 25. For example, the decoding circuit 25 may decode the first sub-data based on a low-density parity check code (LDPC code) or other types of decoding algorithms to try to detect and correct errors (i.e., error bits) in the first sub-data. In one embodiment, the memory control circuit 23 may determine whether the first sub-entity unit belongs to the first type of sub-entity unit based on the decoding result of the decoding circuit 25 on the first sub-data.

[0063] In one embodiment, if the first type of sub-entity unit refers to a sub-entity unit of relatively low quality among the first entity units, and the decoding result of the first sub-data by the decoding circuit 25 is a decoding failure (i.e., all error bits in the first sub-data cannot be completely corrected), the memory control circuit 23 may determine that the first sub-entity unit belongs to the first type of sub-entity unit. However, if the first type of sub-entity unit refers to a sub-entity unit of relatively low quality among the first entity units, and the decoding result of the first sub-data by the decoding circuit 25 is a decoding success (i.e., all error bits in the first sub-data can be completely corrected), the memory control circuit 23 may determine that the first sub-entity unit does not belong to the first type of sub-entity unit.

[0064] In one embodiment, if the first type of sub-entity unit refers to a sub-entity unit with relatively high quality among the first entity units, and the decoding result of the decoding circuit 25 on the first sub-data is a decoding failure, the memory control circuit 23 may determine that the first sub-entity unit does not belong to the first type of sub-entity unit. However, if the first type of sub-entity unit refers to a sub-entity unit with relatively high quality among the first entity units, and the decoding result of the decoding circuit 25 on the first sub-data is a decoding success, the memory control circuit 23 may determine that the first sub-entity unit belongs to the first type of sub-entity unit.

[0065] In one embodiment, the decoding result of the first sub-data by the decoding circuit 25 may be affected by the offset. Alternatively, from another perspective, the decoding result of the first sub-data by the decoding circuit 25 may roughly reflect the distribution of the threshold voltages of the plurality of first memory cells compared to the read voltage level.

[0066] Figure 7 is a schematic diagram showing the distribution of the threshold voltages of a plurality of first memory cells compared to the read voltage level according to an embodiment of the present invention. Figure 7 Assuming that the read voltage level 71 is a preset read voltage level corresponding to the first sub-sub-unit, the memory control circuit 23 may add an offset (eg, n×ΔV, where n may be any value) to the read voltage level 71 to obtain a read voltage level 72 .

[0067] In one embodiment, it is assumed that the critical voltage distribution of the plurality of memory cells in the first sub-physical unit (i.e., the first memory cell) includes states 701 and 702. After the first sub-physical unit is read based on the read voltage level 72 and the first sub-data is decoded, the first sub-data can be successfully decoded. Therefore, in this embodiment, the memory control circuit 23 can determine that the distance between states 701 and 702 is relatively far (or the distance between state 702 and the read voltage level 71 is relatively far) according to the decoding result of the first sub-data, and the quality of the first sub-physical unit is relatively high.

[0068] In one embodiment, it is assumed that the critical voltage distribution of the plurality of memory cells in the first sub-physical unit (i.e., the first memory cell) includes states 711 and 712. After the first sub-physical unit is read and the first sub-data is decoded based on the read voltage level 72, the first sub-data cannot be successfully decoded. Therefore, in this embodiment, the memory control circuit 23 can determine that the distance between the states 711 and 712 is relatively close (or the distance between the state 712 and the read voltage level 71 is relatively close) according to the decoding result of the first sub-data, and the quality of the first sub-physical unit is relatively low.

[0069] In one embodiment, it is assumed that the critical voltage distribution of the plurality of memory cells in the first sub-physical unit (i.e., the first memory cell) includes states 721 and 722. After the first sub-physical unit is read based on the read voltage level 72 and the first sub-data is decoded, the first sub-data cannot be successfully decoded. Therefore, in this embodiment, the memory control circuit 23 can determine that the distance between the states 721 and 722 is relatively close (or the distance between the state 722 and the read voltage level 71 is relatively close) according to the decoding result of the first sub-data, and the quality of the first sub-physical unit is relatively low.

[0070] It should be noted that in Figure 7 In the embodiment, regardless of whether the quality of the first physical subunit is relatively low or relatively high, after the data (also referred to as the second sub-data) is read from the first physical subunit based on the read voltage level 71, the decoding circuit 25 can successfully decode the second sub-data (i.e., completely correct all error bits in the second sub-data). It can be seen that compared with the shifted read voltage level 72, the read voltage level 71 may not be directly used to detect the quality (e.g., durability and / or reliability) of the first physical subunit.

[0071] In one embodiment, after obtaining the first sub-data, the memory control circuit 23 may count the total number of specific bits (also referred to as first bits) in the first sub-data. Then, the memory control circuit 23 may determine whether the first sub-entity unit belongs to the first type of sub-entity unit according to the total number of first bits. In particular, the total number of first bits may also be affected by the offset.

[0072] by Figure 7 For example, the first bit may refer to all bits "1" in the first sub-data read. Figure 7 In the states 701 and 702, the total number of bits "1" (i.e., the first bit) in the first sub-data read based on the read voltage level 72 is relatively small. Figure 7 In the states 711 and 712 (and states 721 and 722), the total number of bits "1" (i.e., the first bit) in the first sub-data read based on the read voltage level 72 is relatively large. The reason is that when the states 711 and 712 (and states 721 and 722) are closer, Figure 7 The slashed area in will expand, resulting in an increase in the total number of bits "1" (i.e., first bits) read by applying the read voltage level 72. Therefore, in one embodiment, the distribution of the critical voltages of the plurality of first memory cells compared to the read voltage level can be roughly determined by detecting the total number of first bits read based on the read voltage level.

[0073] In one embodiment, the memory control circuit 23 may determine whether the total number of the first bits is greater than a decision value. If the first-class sub-entity unit refers to a sub-entity unit with relatively low quality among the first entity units, and the total number of the first bits is greater than the decision value, the memory control circuit 23 may determine that the first sub-entity unit belongs to the first-class sub-entity unit. However, if the first-class sub-entity unit refers to a sub-entity unit with relatively low quality among the first entity units, and the total number of the first bits is not greater than (e.g., less than or equal to) the decision value, the memory control circuit 23 may determine that the first sub-entity unit does not belong to the first-class sub-entity unit.

[0074] In one embodiment, if the first type of sub-entity unit refers to a sub-entity unit with relatively high quality among the first entity units, and the total number of the first bits is greater than the decision value, the memory control circuit 23 may determine that the first sub-entity unit does not belong to the first type of sub-entity unit. However, if the first type of sub-entity unit refers to a sub-entity unit with relatively high quality among the first entity units, and the total number of the first bits is not greater than (e.g., less than or equal to) the decision value, the memory control circuit 23 may determine that the first sub-entity unit belongs to the first type of sub-entity unit.

[0075] It should be noted that, in one embodiment, the memory control circuit 23 may also scan the first memory cell to directly obtain the threshold voltage distribution of the first memory cell to confirm whether the first sub-entity unit belongs to the first type of sub-entity unit, and the present invention is not limited thereto.

[0076] In one embodiment, the memory control circuit 23 may also compare the total number of the first type of physical cells currently detected with a preset number. Then, the memory control circuit 23 may adjust the offset according to the comparison result to change the read voltage level. Figure 6 For example, according to the comparison result between the total number of the first type of physical cells currently detected and the preset number, the memory control circuit 23 may adjust the offset between 1×ΔV, 2×ΔV, 3×ΔV and / or other offsets. Then, the memory control circuit 23 may instead obtain a read voltage level (e.g., one of the read voltage levels 62-64) based on the adjusted offset and re-detect the first type of physical cells in the memory module 122 based on the adjusted read voltage level.

[0077] In one embodiment, based on the comparison result between the total number of the first type of physical cells currently detected and the preset number, the memory control circuit 23 can determine whether the total number of the first type of physical cells currently detected reaches the preset number. If the total number of the first type of physical cells currently detected does not reach the preset number, the memory control circuit 23 can adjust the offset to change the read voltage level. Figure 6 For example, assume that the read voltage level 64 previously used to detect the first type of physical cells is obtained based on the offset 3×ΔV. After determining that the total number of the first type of physical cells currently detected based on the read voltage level 64 is insufficient (e.g., less than the preset number), the memory control circuit 23 may instead obtain the read voltage level 63 (or 62) based on the offset 2×ΔV (or 1×ΔV). Then, the memory control circuit 23 may re-detect the first type of physical cells in the memory module 122 based on the adjusted read voltage level to try to increase the total number of the first type of physical cells subsequently detected.

[0078] exist Figure 6 In one embodiment, the total number of first-type physical cells detected from the memory module 122 based on the read voltage level 62 may be greater than the total number of first-type physical cells detected from the memory module 122 based on the read voltage level 63, and / or the total number of first-type physical cells detected from the memory module 122 based on the read voltage level 63 may be greater than the total number of first-type physical cells detected from the memory module 122 based on the read voltage level 64. However, the overall quality of the first-type physical cells detected from the memory module 122 based on the read voltage level 62 may be lower than the overall quality of the first-type physical cells detected from the memory module 122 based on the read voltage level 63, and / or the overall quality of the first-type physical cells detected from the memory module 122 based on the read voltage level 63 may be lower than the overall quality of the first-type physical cells detected from the memory module 122 based on the read voltage level 64.

[0079] In one embodiment, the memory control circuit 23 may use a plurality of offsets in order from small to large (eg Figure 6 The corresponding read voltage levels (e.g. Figure 6 The memory control circuit 23 can detect the first type of physical cells in the memory module 122 in sequence based on the obtained read voltage levels. In one embodiment, it is assumed that the preset number is "5", and the total number of the first type of physical cells detected in sequence based on the read voltage levels 62, 63 and 64 are "50", "10" and "3" respectively. In this case, the memory control circuit 23 can ignore the first type of physical cells detected based on the read voltage levels 62 and 64, and retain the first type of physical cells detected based on the read voltage level 63. In this way, a balance can be achieved between the accuracy of the quality detection of the first type of physical cells and the total number of the first type of physical cells detected at that time.

[0080] In one embodiment, the memory control circuit 23 may determine the preset number according to the amount of system data to be stored. For example, assuming that the amount of system data currently required to be stored is less than or equal to the capacity of n physical units, the memory control circuit 23 may determine the preset number as "n". Thereafter, according to the above-mentioned adjustment mechanism for the offset and the detection mechanism for the first type of physical units, the memory control circuit 23 may obtain a sufficient number of first type physical units with relatively high quality from the memory module 122, and then store the system data in the first type of physical units.

[0081] In one embodiment, after determining that the first entity unit meets the preset condition (i.e., the first entity unit is an entity unit with relatively high quality), the memory control circuit 23 may first determine the first entity unit as one of a plurality of candidate entity units. Then, the memory control circuit 23 may determine the first type of entity unit from the plurality of candidate entity units according to the distribution of the first type of sub-entity units in the plurality of candidate entity units. For example, according to the distribution, the memory control circuit 23 may determine the first type of entity unit with relatively high distribution consistency among the plurality of candidate entity units as the first type of entity unit.

[0082] Figure 8 FIG. 1 is a schematic diagram of determining a first type of entity unit from a plurality of candidate entity units according to an embodiment of the present invention. Figure 8 In one embodiment, assuming that the physical units 81-85 are all determined to meet the preset conditions, the memory control circuit 23 may first determine the physical units 81-85 as candidate physical units.

[0083] In one embodiment, it is assumed that the i-th sub-entity element 811(i), the j-th sub-entity element 811(j), and the k-th sub-entity element 811(k) in the entity element 81 are first-type sub-entity elements in the entity element 81 (i.e., sub-entity elements with relatively high mass in the entity element 81). The i-th sub-entity element 821(i), the j-th sub-entity element 821(j), and the k-th sub-entity element 821(k) in the entity element 82 are first-type sub-entity elements in the entity element 82 (i.e., sub-entity elements with relatively high mass in the entity element 82). The s-th sub-entity element 831(s) and the k-th sub-entity element 831(k) in the entity element 83 are first-type sub-entity elements in the entity element 83 (i.e., sub-entity elements with relatively high mass in the entity element 83). The i-th sub-entity element 841(i), the j-th sub-entity element 841(j), and the k-th sub-entity element 841(k) in the entity element 84 are first-type sub-entity elements in the entity element 84 (i.e., sub-entity elements with relatively high mass in the entity element 84). The q-th sub-entity element 851(q) and the p-th sub-entity element 851(p) in the entity element 85 are first-type sub-entity elements in the entity element 85 (i.e., sub-entity elements with relatively high mass in the entity element 85).

[0084] In one embodiment, the memory control circuit 23 may determine the physical units 81-85 that have a relatively high distribution consistency of the first-type sub-physical units (i.e., the physical units 81, 82, and 84) as the first-type physical units. For example, the memory control circuit 23 may add the physical units 81, 82, and 84 to the group 86 to wait for being used to store system data. The physical units 86(1)-86(n) in the group 86 are all confirmed first-type sub-physical units.

[0085] In one embodiment, the memory control circuit 23 may record the distribution of the first-category sub-entity units in the plurality of candidate entity units in a single management table. Based on the information in the management table, the memory control circuit 23 may count how many of the candidate entity units have the m-th sub-entity units belonging to the first-category sub-entity units, where m may be any integer. Figure 8For example, the memory control circuit 23 can count, based on the information in this management table, among the entity units 81 to 85, the i-th sub-entity unit among "3" entity units belongs to the first type of sub-entity unit, the j-th sub-entity unit among "3" entity units belongs to the first type of sub-entity unit, the k-th sub-entity unit among "4" entity units belongs to the first type of sub-entity unit, the s-th sub-entity unit among "1" entity unit belongs to the first type of sub-entity unit, the q-th sub-entity unit among "1" entity unit belongs to the first type of sub-entity unit, and the p-th sub-entity unit among "1" entity unit belongs to the first type of sub-entity unit. Then, based on the information in this management table, the memory control circuit 23 can determine the entity units 81 to 85 with relatively high distribution consistency of the first type of sub-entity units (i.e., entity units 81, 82, and 84) as the first type of entity units.

[0086] In one embodiment, by further selecting the candidate entity units with relatively high distribution consistency of the first-category sub-entity units as the first-category entity units, the subsequent management and / or use efficiency of the first-category entity units can be improved.

[0087] Fig. 9 is a flow chart of a memory management method according to an embodiment of the present invention. Fig. 9 In step S901, a read voltage level is determined according to the offset. In step S902, a first physical unit is read based on the read voltage level to obtain first data. In step S903, first quality assessment information corresponding to the first physical unit is obtained according to the first data, wherein the first quality assessment information reflects the quality state of the first physical unit assessed based on the read voltage level. In step S904, whether the first physical unit meets the preset condition is determined according to the first quality assessment information. If the first physical unit meets the preset condition, in step S905, the first physical unit is determined as a first-class physical unit. In step S906, the system data is stored in the first-class physical unit. However, if the first physical unit does not meet the preset condition, in step S907, the first physical unit is not determined as a first-class physical unit.

[0088] However, Fig. 9 The steps in the above are described in detail, so I will not repeat them here. It is worth noting that Fig. 9 Each step in the above process can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. Fig. 9 The method can be used in conjunction with the above exemplary embodiments or can be used alone, and the present invention is not limited thereto.

[0089] In summary, the memory management method and storage device proposed in the embodiment of the present invention can select physical units with relatively high quality, durability and / or reliability from the memory module through a unique screening mechanism, and preferentially use these physical units to store system data. This can solve the technical problem that once a read error occurs in the physical block used to store system data in the storage device, the storage device cannot operate normally, thereby improving the operation stability of the storage device.

[0090] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method, characterized in that: For use in a storage device, wherein the storage device comprises a memory module, the memory module comprises a plurality of entity units, and the memory management method comprises: Step a: Determine the read voltage level according to the offset; Step b: reading a first physical cell among the plurality of physical cells based on the read voltage level to obtain first data; Step c: obtaining first quality assessment information corresponding to the first physical unit according to the first data, wherein the first quality assessment information reflects the quality status of the first physical unit assessed based on the read voltage level; Step d: judging whether the first entity unit meets a preset condition according to the first quality evaluation information; Step e: if the first entity unit meets the preset condition, determining the first entity unit as a first type entity unit; and Step f: storing the system data in the first type of entity units. 2 . The memory management method according to claim 1 , wherein the first quality assessment information comprises a count value, and the count value reflects the total number of the first type of sub-physical units in the first physical unit.

3. The memory management method according to claim 1, wherein the step of judging whether the first entity unit meets the preset condition according to the first quality evaluation information comprises: Comparing the first quality assessment information with a preset value; as well as According to the comparison result, it is determined whether the first entity unit meets the preset condition.

4. The memory management method according to claim 2, wherein the first entity unit includes a first sub-entity unit, the first sub-entity unit includes a plurality of first storage units, and the step of obtaining the first quality assessment information corresponding to the first entity unit according to the first data comprises: According to the distribution of the threshold voltages of the plurality of first memory cells compared to the read voltage level, it is determined whether the first physical sub-unit belongs to the first type of physical sub-unit.

5. The memory management method according to claim 4, wherein the first data comprises first sub-data, the first sub-data reflects a reading result of the first sub-entity unit based on the read voltage level, and the step of determining whether the first sub-entity unit belongs to the first type of sub-entity unit according to the distribution of the critical voltages of the plurality of first storage units compared to the read voltage level comprises: decoding the first sub-data; as well as It is determined whether the first sub-entity unit belongs to the first type of sub-entity unit according to a decoding result of the first sub-data, wherein the decoding result of the first sub-data is affected by the offset.

6. The memory management method according to claim 4, wherein the first data comprises first sub-data, the first sub-data reflects a reading result of the first sub-entity unit based on the read voltage level, and the step of determining whether the first sub-entity unit belongs to the first type of sub-entity unit according to the distribution of the critical voltages of the plurality of first storage units compared to the read voltage level comprises: Counting the total number of first bits in the first sub-data, wherein the total number of the first bits is affected by the offset; as well as Whether the first sub-entity unit belongs to the first type of sub-entity unit is determined according to the total number of the first bits.

7. The memory management method according to claim 1, further comprising: comparing the total number of the first type of entity elements with a preset number; as well as According to the comparison result, the offset is adjusted and steps a to d are repeated.

8. The memory management method according to claim 7, further comprising: The preset number is determined according to the data volume of the system data.

9. The memory management method according to claim 1, wherein the step of determining the first entity unit as the first type of entity unit comprises: Determine the first entity unit as one of a plurality of candidate entity units; as well as According to the distribution of the first type of sub-entity units in the plurality of candidate entity units, the first type of entity unit is determined from the plurality of candidate entity units, The distribution status of the first type of sub-entity units in the plurality of candidate entity units is recorded in a single management table. 10 . The memory management method according to claim 1 , wherein the system data comprises at least one of a boot firmware, a voltage adjustment table, a logic-to-physical mapping table, a bad block management table, and a valid data management table.

11. A storage device, characterized in that: include: A connection interface for connecting to a host system; Memory module; as well as a memory controller connected to the connection interface and the memory module, The memory module includes a plurality of physical units, and the memory controller is used to execute: Step a: Determine the read voltage level according to the offset; Step b: reading a first physical cell among the plurality of physical cells based on the read voltage level to obtain first data; Step c: obtaining first quality assessment information corresponding to the first physical unit according to the first data, wherein the first quality assessment information reflects the quality status of the first physical unit assessed based on the read voltage level; Step d: judging whether the first entity unit meets a preset condition according to the first quality evaluation information; Step e: if the first entity unit meets the preset condition, determining the first entity unit as a first type entity unit; as well as Step f: storing the system data in the first type of entity units. 12 . The storage device according to claim 11 , wherein the first quality assessment information comprises a count value, and the count value reflects a total number of first-type sub-entity units in the first entity unit.

13. The storage device according to claim 11, wherein the operation of the memory controller judging whether the first physical unit meets the preset condition according to the first quality evaluation information comprises: Comparing the first quality assessment information with a preset value; as well as According to the comparison result, it is determined whether the first entity unit meets the preset condition.

14. The storage device according to claim 12, wherein the first physical unit includes a first sub-physical unit, the first sub-physical unit includes a plurality of first storage units, and the operation of the memory controller obtaining the first quality assessment information corresponding to the first physical unit according to the first data comprises: According to the distribution of the threshold voltages of the plurality of first memory cells compared to the read voltage level, it is determined whether the first physical sub-unit belongs to the first type of physical sub-unit.

15. The storage device according to claim 14, wherein the first data includes first sub-data, the first sub-data reflects a reading result of the first sub-entity unit based on the read voltage level, and the memory controller determines whether the first sub-entity unit belongs to the first type of sub-entity unit according to the distribution of the critical voltages of the plurality of first storage units compared to the read voltage level, comprising: decoding the first sub-data; as well as It is determined whether the first sub-entity unit belongs to the first type of sub-entity unit according to a decoding result of the first sub-data, wherein the decoding result of the first sub-data is affected by the offset.

16. The storage device according to claim 14, wherein the first data comprises first sub-data, the first sub-data reflects a reading result of the first sub-entity unit based on the read voltage level, and the memory controller determines whether the first sub-entity unit belongs to the first type of sub-entity unit according to the distribution of the critical voltages of the plurality of first storage units compared to the read voltage level, comprising: Counting the total number of first bits in the first sub-data, wherein the total number of the first bits is affected by the offset; as well as Whether the first sub-entity unit belongs to the first type of sub-entity unit is determined according to the total number of the first bits.

17. The storage device according to claim 11, wherein the memory controller is further configured to: Comparing the total number of the first type of entity elements with a preset number; and According to the comparison result, the offset is adjusted and steps a to d are repeated.

18. The storage device according to claim 17, wherein the memory controller is further configured to: The preset number is determined according to the data volume of the system data.

19. The storage device according to claim 11, wherein the operation of the memory controller determining the first physical unit as the first type of physical unit comprises: Determine the first entity unit as one of a plurality of candidate entity units; as well as According to the distribution of the first type of sub-entity units in the plurality of candidate entity units, the first type of entity unit is determined from the plurality of candidate entity units, The distribution status of the first type of sub-entity units in the plurality of candidate entity units is recorded in a single management table. 20 . The storage device of claim 11 , wherein the system data comprises at least one of a boot firmware, a voltage adjustment table, a logical to physical mapping table, a bad block management table, and a valid data management table.

Images