Communication mode configuration system and method of chip

Abstract

The invention provides a chip communication mode configuration system and method. The chip communication mode configuration system comprises a detection module, a state machine module, a mode register and a mode control module. Wherein the mode register is used for storing a communication mode configured by the FLASH; the detection module is used for detecting the state of the chip and sending the state of the chip to the state machine module; the state machine module is used for storing the state of the chip and sending the state to the mode control module; and the mode control module is used for setting the communication mode of the chip according to the state of the chip and / or the communication mode of the FLASH stored in the mode register. According to the method provided by the embodiment of the invention, the accurate and flexible setting of the chip communication mode is realized, the successful starting and normal communication of the chip and the FLASH in various modes are ensured, the design of FLASH reset pins is reduced, and the board-level design complexity is reduced.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a chip communication mode configuration system and method. Background Art

[0002] FLASH is a flash memory that is connected to the system on chip (SoC) through the serial peripheral interface (SPI) / extended SPI (Quad SPI, QSPI) interface. The communication between FLASH and SoC chips follows the standard interface protocol. FLASH has various modes, such as 1bit, 2bit, 4bit communication modes, etc. When designing SoC chips, it is also necessary to design consistent modes, and the modes of FLASH and SoC chips must match in order to start and communicate normally.

[0003] In the related art, after power failure or when in software reset state, the SoC chip and FLASH may be in different modes, for example, the SoC chip is in 1-bit communication mode, while the FLASH is in 4-bit communication mode. Due to the mode mismatch, the chip cannot start and communicate normally. Summary of the invention

[0004] The present invention provides a chip communication mode configuration system and method, which are used to realize accurate and flexible setting of chip communication mode, ensure successful startup and normal communication of chip and FLASH in various modes, reduce the design of FLASH reset pin, and reduce the complexity of board-level design.

[0005] The present invention provides a chip communication mode configuration system, comprising: Detection module, state machine module, mode register and mode control module; wherein,

[0006] The mode register is used to store the communication mode configured by FLASH; The detection module is used to detect the state of the chip and send the state of the chip to the state machine module; The state machine module is used to store the state of the chip and send it to the mode control module; The mode control module is used to set the communication mode of the chip according to the state of the chip and / or the FALSH communication mode stored in the mode register.

[0007] According to a chip communication mode configuration system provided by the present invention, the state of the chip includes at least one of the following: Power-on reset state, software reset state and working state.

[0008] According to a chip communication mode configuration system provided by the present invention, when the chip is in a power-on reset state, the mode control module is used to set the communication mode of the chip to a preset first communication mode.

[0009] According to a chip communication mode configuration system provided by the present invention, the mode control module is used to set the communication mode of the chip to a preset first communication mode, including: The mode control module is used to set the communication mode of the chip to a 3-Byte mode and a 1-bit mode.

[0010] According to a chip communication mode configuration system provided by the present invention, when the chip is in a software reset state or a working state, the mode control module is used to obtain the communication mode configured by FLASH from the mode register, and set the communication mode of the chip to be consistent with the communication mode of the FLASH.

[0011] The present invention also provides a chip, comprising the communication mode configuration system of the chip as described in the first aspect.

[0012] The present invention also provides a method for configuring a communication mode of a chip, comprising: The communication mode of the chip is set according to the state of the chip and / or the communication mode of FALSH stored in the mode register.

[0013] The present invention also provides a communication mode configuration device for a chip, comprising: The setting module is used to set the communication mode of the chip according to the state of the chip and / or the FALSH communication mode stored in the mode register.

[0014] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the communication mode configuration method of the chip as described above when executing the program.

[0015] The present invention also provides a non-transitory computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the communication mode configuration method of the chip as described above is implemented.

[0016] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the communication mode configuration method of the chip as described above is implemented.

[0017] The chip communication mode configuration system and method provided by the present invention detects the state of the chip and sets the chip communication mode according to the chip state and / or the communication mode of the FLASH stored in the mode register, thereby achieving accurate and flexible setting of the chip communication mode, ensuring successful startup and normal communication between the chip and FLASH in various modes, reducing the design of the FLASH reset pin, and reducing the complexity of board-level design. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 It is a schematic diagram of a chip communication mode configuration system in the prior art provided by the present invention.

[0020] Figure 2 It is a schematic diagram of the communication mode configuration system of the chip provided by the present invention.

[0021] Figure 3 It is one of the flow charts of the communication mode configuration provided by the present invention.

[0022] Figure 4 This is the second flow chart of the communication mode configuration provided by the present invention.

[0023] Figure 5 This is the third flow chart of the communication mode configuration provided by the present invention.

[0024] Figure 6 It is a schematic diagram of a communication mode configuration device of a chip provided by the present invention.

[0025] Figure 7 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] Combine the following Figure 1-Figure 7 The communication mode configuration system and method of the chip of the present invention are described.

[0028] In order to facilitate a clearer understanding of the technical solutions of the embodiments of the present application, some technical contents related to the embodiments of the present application are first introduced.

[0029] The most common startup method for SoC chips is FLASH startup. The startup program of the chip is burned into FLASH. After power-on, the processor module in the chip reads the startup program from FLASH and executes it.

[0030] FLASH is a flash memory that is connected to the SoC chip through the SPI / QSPI interface. The communication between FLASH and the SoC chip follows the standard interface protocol. FLASH is generally produced by FLASH manufacturers. The FLASH models of different manufacturers vary, mainly reflected in the differences in FLASH capacity, speed, voltage, etc. However, because it uses standard protocol communication, SoC chips are compatible with multiple FLASHs at the beginning of their design. After the software driver of the SoC chip is adapted, multiple FLASHs can be used.

[0031] FLASH has various modes, such as 1-bit, 2-bit, and 4-bit communication modes. When designing SoC chips, consistent modes must also be designed, and the modes of FLASH and SoC chips must match in order to start and communicate normally.

[0032] After power failure, FLASH will be in default mode. When powered on, both SoC chip and FLASH are in default mode. When in software reset state, SoC chip is reset to default mode. Since power failure has not occurred, FLASH will be in the last configured mode. At this time, SoC chip and FLASH may be in different modes. For example, SoC chip is in 1-bit communication mode, while FLASH is in 4-bit communication mode. The mode mismatch may cause incorrect data read from FLASH after software reset and startup failure.

[0033] like Figure 1 As shown, the prior art solves this problem by adding a signal line to reset the FLASH chip. The SoC chip leads to a dedicated reset RST pin connected to the FLASH, and the FLASH is reset in the case of software reset, so that the mode matches. On the one hand, this technical solution will increase the pins of the chip design, further affecting the board-level design; on the other hand, not all FLASHes have a reset pin, so this technology is no longer applicable when using such FLASHes.

[0034] Figure 2 is a schematic diagram of the communication mode configuration system of the chip provided by the present invention, such as Figure 2 As shown, including the following: Detection module, state machine module, mode register and mode control module; wherein,

[0035] The mode register is used to store the communication mode configured by FLASH; The detection module is used to detect the state of the chip and send the state of the chip to the state machine module; The state machine module is used to store the state of the chip and send it to the mode control module; The mode control module is used to set the communication mode of the chip according to the state of the chip and / or the FALSH communication mode stored in the mode register.

[0036] Specifically, the detection module is used to detect the state of the SoC chip, that is, the detection module can determine whether the chip is in a power-on reset state, a software reset state or a working state. Optionally, when the chip is in a power-on reset state or a software reset state, the chip needs to be configured with the same communication mode as the FLASH when it is started, so as to accurately read the startup program from the FLASH. When the chip is in a normal working state, the chip needs to be configured with the same communication mode as the FLASH, so that the chip and the FLASH can communicate and read and write normally.

[0037] The state machine module is used to receive the detection results of the detection module and send them to the mode control module to perform logic control. Different state control logics will be executed in different chip states to make the communication mode of the chip and the communication mode of FLASH consistent.

[0038] The mode register is used to store the communication mode configured by FLASH; that is, after the user configures the communication mode of FLASH, the communication mode of FLASH will be written into the mode register, so that the chip can obtain the communication mode of FLASH from the mode register, and configure the communication mode of the chip based on the obtained communication mode of FLASH. Optionally, the mode register in the embodiment of the present application includes: 3 / 4Byte mode register: used to store the 3Byte or 4Byte address mode configuration value of FLASH. 1 / 2 / 4bit mode register: used to store the 1bit, 2bit or 4bit IO mode configuration value of FLASH.

[0039] The mode control module is used to set the communication mode of the chip according to the state of the chip and / or the communication mode of FALSH stored in the mode register. Optionally, the mode control module can set the chip to the default communication mode based on the state of the chip; it can also determine the communication mode required for the chip to be configured in combination with the state of the chip and the communication mode of FALSH stored in the mode register, thereby achieving accurate and flexible setting of the chip communication mode, so that the chip can start normally and communicate with FLASH. Optionally, the mode control module in the embodiment of the present application includes: 3 / 4Byte mode control module: used to receive the logic control of the state machine module, and select the 3Byte or 4Byte address mode according to the logic control. 1 / 2 / 4bit mode control module: used to receive the logic control of the state machine module, and select the 1bit, 2bit or 4bit IO mode according to the logic control.

[0040] Optionally, the communication mode configuration system in the embodiment of the present application may also include: an interface module for the SoC chip to send and receive FLASH clock, commands, data, etc. PAD, used to connect the signal pins between the chip and FLASH. clk, cs, data: FLASH clock, chip select, data signal lines, which are universal standard designs. Optionally, the technical solution is not limited to the proposed FLASH device, and the relevant technical ideas can also be applied to SoC chip startup devices or media such as SD, eMMC, ethernet, etc.

[0041] It should be noted that the communication mode configuration system of the chip in the embodiment of the present application realizes accurate configuration of the communication mode of the chip based on the detection module, the state machine module, the mode register and the mode control module. Compared with the prior art, the design of the FLASH reset pin is reduced, the complexity of the board-level design is reduced, and multiple and multiple types of FLASH startup are supported to ensure successful startup in various modes and avoid system downtime. That is, in the present application, by designing the detection module, the state machine, the mode control and other modules inside the SoC chip, there is no need to change the connection between the SoC chip and the FLASH device and the board-level design, so that the chip communication mode can be accurately configured in various chip startup scenarios such as power-on and reset, so that the startup program can be correctly read from the FLASH device for execution, simplifying the complexity of chip and board design, being compatible with multiple types of FLASH devices, and ensuring the successful startup and communication of the SoC chip.

[0042] The communication mode configuration system of the above embodiment detects the state of the chip and sets the communication mode of the chip according to the state of the chip and / or the communication mode of FALSH stored in the mode register, thereby realizing accurate and flexible setting of the chip communication mode, ensuring the successful startup and normal communication of the chip and FLASH in various modes, reducing the design of the FLASH reset pin, and reducing the complexity of board-level design.

[0043] In one embodiment, the state of the chip includes at least one of the following: Power-on reset state, software reset state and working state.

[0044] Specifically, the detection module in the embodiment of the present application can accurately detect the state of the chip, that is, it can accurately detect whether the chip is in a power-on reset state, a software reset state or a working state, and adopt different communication mode configuration methods for the chip in different states, thereby realizing accurate and flexible setting of the chip communication mode in different states, and ensuring the successful startup and normal communication of the chip and FLASH in various modes.

[0045] In one embodiment, when the chip is in a power-on reset state, the mode control module is used to set the communication mode of the chip to a preset first communication mode.

[0046] Specifically, in the power-on reset state, FALSH will be initialized and set to the first communication mode. Therefore, the mode control module can directly set the communication mode of the chip to the preset first communication mode, and no longer needs to obtain the communication mode of FALSH from the register, so that the communication mode of the chip can be configured more quickly, thereby improving the configuration efficiency of the communication mode of the chip in the power-on reset state.

[0047] For example, Figure 3 As shown, the detection module first detects the state of the chip. If it is a power-on reset scenario, the detection module outputs a power-on reset mode. After the state machine module receives the mode, it sets the current state to the power-on reset state.

[0048] In the power-on reset state, the state machine module controls the 3 / 4Byte mode control module to complete initialization. At this time, the 3 / 4Byte mode register is set to the 3Byte mode value, and the FLASH device defaults to the 3Byte mode value in this state. The two mode values ​​are consistent, that is, the 3Byte mode will be used for correct communication between the SoC chip and the FLASH device.

[0049] In the power-on reset state, the state machine module controls the 1 / 2 / 4-bit mode control module to complete initialization. At this time, the 1 / 2 / 4-bit mode register is set to a 1-bit mode value. The FLASH device defaults to a 1-bit mode value in this state. The two mode values ​​are consistent, that is, the 1-bit mode will be used for correct communication between the SoC chip and the FLASH device.

[0050] In the communication mode configuration system of the above embodiment, when the chip is in the power-on reset state, the mode control module can directly set the communication mode of the chip to the preset first communication mode, and there is no need to obtain the FALSH communication mode from the register, so that the chip communication mode can be configured more quickly, thereby improving the configuration efficiency of the chip communication mode in the power-on reset state.

[0051] The mode control module is used to set the communication mode of the chip to a preset first communication mode, including: The mode control module is used to set the communication mode of the chip to 3Byte mode and 1bit mode.

[0052] Specifically, in an embodiment of the present application, based on the setting of the actual application scenario, the 3Byte mode and the 1bit mode can be used as the first communication mode of the chip in the power-on reset state, so that the communication mode of the chip and the communication mode of FLASH are consistent, so that the startup program can be accurately read from FLASH.

[0053] In the communication mode configuration system of the above embodiment, when the chip is powered on and reset, the mode control module can directly set the communication mode of the chip to 3Byte mode and 1bit mode, so that the communication mode of the chip is consistent with the communication mode of FLASH, so that the startup program can be accurately read from FLASH.

[0054] In one implementation, when the chip is in a software reset state or a working state, the mode control module is used to obtain the communication mode configured by the FLASH from the mode register, and set the chip communication mode to be consistent with the FLASH communication mode.

[0055] Specifically, when the chip is in a software reset state or a working state, the communication mode of FLASH will not be initialized, but the user may change the communication mode of FLASH according to their own needs. Therefore, in order to make the communication mode of the chip consistent with the communication mode of FLASH, the mode control module needs to obtain the communication mode configured by FLASH from the mode register, and set the communication mode of the chip to be consistent with the communication mode of FLASH. Optionally, when the chip is in a software reset state or a working state, the mode control module can periodically obtain the communication mode configured by FLASH from the mode register, or obtain the FLASH communication mode when the chip needs to communicate with FLASH, which is not specifically limited in the embodiments of the present application.

[0056] For example, Figure 4 As shown, the detection module first detects the state of the chip. If it is a software reset scenario, the detection module outputs a software reset mode. After the state machine module receives the mode, it sets the current state to the software reset state.

[0057] In the software reset state, the state machine module controls the 3 / 4Byte mode control module to maintain the state, and the value of the 3 / 4Byte mode register will maintain the last configuration value. If the FLASH device was set to the 3Byte mode value last time, the 3 / 4Byte mode register will maintain the 3Byte mode value, and the two mode values ​​are consistent, that is, the 3Byte mode will be used for the correct communication between the SoC chip and the FLASH device; if the FLASH device was set to the 4Byte mode value last time, the 3 / 4Byte mode register will maintain the 4Byte mode value, and the two mode values ​​are consistent, that is, the 4Byte mode will be used for the correct communication between the SoC chip and the FLASH device.

[0058] In the software reset state, the state machine module controls the 1 / 2 / 4bit mode control module to maintain the state, and the 1 / 2 / 4bit mode register will maintain the last configuration value. If the FLASH device was set to a 1bit mode value last time, the 1 / 2 / 4bit mode register will maintain a 1bit mode value at this time, and the two mode values ​​are consistent, that is, the 1bit mode will be used for the correct communication between the SoC chip and the FLASH device at this time; if the FLASH device was set to a 2bit mode value last time, the 1 / 2 / 4bit mode register will maintain a 2bit mode value at this time, and the two mode values ​​are consistent, that is, the 2bit mode will be used for the correct communication between the SoC chip and the FLASH device at this time; if the FLASH device was set to a 4bit mode value last time, the 1 / 2 / 4bit mode register will maintain a 4bit mode value at this time, and the two mode values ​​are consistent, that is, the 4bit mode will be used for the correct communication between the SoC chip and the FLASH device at this time.

[0059] For example, Figure 5 As shown, the detection module first detects the state of the chip. If it is a working state scenario, the detection module outputs a working state mode. After the state machine module receives the mode, it sets the current state to the working state.

[0060] In the configuration state, the state machine module controls the 3 / 4Byte mode control module to perform state configuration. At this time, the value of the 3 / 4Byte mode register will be set to the 3Byte or 4Byte mode value according to the user's configuration value, and the FLASH device will be set to the 3Byte or 4Byte mode value according to the user's configuration value. The two mode values ​​are consistent, that is, the 3Byte or 4Byte mode will be used accordingly for correct communication between the SoC chip and the FLASH device.

[0061] In the configuration state, the state machine module controls the 1 / 2 / 4bit mode control module to perform state configuration. At this time, the value of the 1 / 2 / 4bit mode register will be set to 1bit, 2bit or 4bit mode value according to the user's configuration value, and the FLASH device will be set to 1bit, 2bit or 4bit mode value according to the user's configuration value. The mode values ​​of the two are consistent, that is, the corresponding 1bit, 2bit or 4bit mode will be used for correct communication between the SoC chip and the FLASH device.

[0062] That is, this application can adapt to various SoC chip startup scenarios such as power-on reset, software reset and non-reset without introducing additional chip pins and supporting multiple types of FLASH. It can realize the successful startup and communication of SoC chips from FLASH in various scenarios, avoid the startup failure caused by inconsistent FLASH mode, and simplify the complexity of chip and hardware board system design.

[0063] In the communication mode configuration system of the above embodiment, when the chip is in a software reset state or a working state, the mode control module is used to obtain the communication mode configured by the FLASH from the mode register, and set the communication mode of the chip to be consistent with the communication mode of the FLASH, thereby achieving accurate setting of the chip communication mode, ensuring the successful startup and normal communication of the chip and FLASH in various modes, effectively reducing the design of the FLASH reset pin, and reducing the complexity of board-level design.

[0064] Exemplarily, an embodiment of the present application further provides a communication mode configuration method of a chip, which is applied to a mode control module in a communication mode configuration system, including: Set the communication mode of the chip according to the communication mode of FALSH stored in the chip's status and / or mode register.

[0065] Specifically, when the chip is in the power-on reset state or software reset state, the chip needs to be configured with the same communication mode as the FLASH when it starts up, so as to accurately read the startup program from the FLASH. When the chip is in the normal working state, the chip needs to be configured with the same communication mode as the FLASH, so that the chip and the FLASH can communicate and read and write normally.

[0066] After detecting the state of the SoC chip and determining the state of the chip, the mode control module can set the communication mode of the chip according to the state of the chip and / or the communication mode of FALSH stored in the mode register. Optionally, the mode control module can set the chip to the default communication mode based on the state of the chip; it can also determine the communication mode that the chip needs to configure in combination with the state of the chip and the communication mode of FALSH stored in the mode register, thereby achieving accurate and flexible setting of the chip communication mode, so that the chip can start normally and communicate with FLASH.

[0067] In the embodiment of the present application, the communication mode of the chip is accurately configured through the mode control module. Compared with the prior art, the design of the FLASH reset pin is reduced, the complexity of the board-level design is reduced, and multiple types of FLASH startup are supported to ensure successful startup in various modes and avoid system downtime.

[0068] The communication mode configuration method of the above embodiment sets the communication mode of the chip according to the communication mode of FALSH stored in the chip status and / or mode register, thereby realizing accurate and flexible setting of the chip communication mode, ensuring the successful startup and normal communication of the chip and FLASH in various modes, effectively reducing the design of the FLASH reset pin, and reducing the complexity of board-level design.

[0069] In one embodiment, if Figure 6 As shown, in an embodiment of the present application, a communication mode configuration device of a chip is also provided, including: The setting module 610 is used to set the communication mode of the chip according to the state of the chip and / or the communication mode of FALSH stored in the mode register.

[0070] Optionally, the setting module 610 is specifically configured to set the communication mode of the chip to a preset first communication mode when the chip is in a power-on reset state.

[0071] Optionally, the setting module 610 is specifically configured to set the communication mode of the chip to a 3-Byte mode and a 1-bit mode when the chip is in a power-on reset state.

[0072] Optionally, the setting module 610 is specifically used to obtain the communication mode configured by FLASH from the mode register when the chip is in a software reset state or a working state, and set the communication mode of the chip to be consistent with the communication mode of FLASH.

[0073] Figure 7 An example of a physical structure diagram of an electronic device is provided, and the electronic device may include: a processor (processor) 710, a communication interface (Communications Interface) 720, a memory (memory) 730 and a communication bus 740, wherein the processor 710, the communication interface 720, and the memory 730 communicate with each other through the communication bus 740. The processor 710 may call the logic instructions in the memory 730 to execute a communication mode configuration method of a chip, and the method includes: setting the communication mode of the chip according to the communication mode of FALSH stored in the state and / or mode register of the chip.

[0074] In addition, the logic instructions in the above-mentioned memory 730 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on this understanding, the technical solution of the present invention can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0075] On the other hand, the present invention also provides a computer program product, which includes a computer program. The computer program can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the chip communication mode configuration method provided by the above methods, and the method includes: setting the chip communication mode according to the FALSH communication mode stored in the chip status and / or mode register.

[0076] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the communication mode configuration method of the chip provided by the above methods is implemented. The method includes: setting the communication mode of the chip according to the communication mode of FALSH stored in the chip status and / or mode register.

[0077] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0078] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0079] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A chip communication mode configuration system, characterized in that: include: Detection module, state machine module, mode register and mode control module; wherein, The mode register is used to store the communication mode configured by FLASH; The detection module is used to detect the state of the chip and send the state of the chip to the state machine module; The state machine module is used to store the state of the chip and send it to the mode control module; The mode control module is used to set the communication mode of the chip according to the state of the chip and / or the FALSH communication mode stored in the mode register.

2. The chip communication mode configuration system according to claim 1, characterized in that: The chip status includes at least one of the following: Power-on reset state, software reset state and working state.

3. The chip communication mode configuration system according to claim 2, characterized in that: When the chip is in a power-on reset state, the mode control module is used to set the communication mode of the chip to a preset first communication mode.

4. The chip communication mode configuration system according to claim 3, characterized in that: The mode control module is used to set the communication mode of the chip to a preset first communication mode, including: The mode control module is used to set the communication mode of the chip to 3Byte mode and 1bit mode.

5. The chip communication mode configuration system according to claim 2, characterized in that: When the chip is in a software reset state or a working state, the mode control module is used to obtain the communication mode configured by the FLASH from the mode register, and set the communication mode of the chip to be consistent with the communication mode of the FLASH.

6. A chip, characterized in that: A communication mode configuration system comprising a chip as described in any one of claims 1-5.

7. A method for configuring a communication mode of a chip, characterized in that: A mode control module used in a communication mode configuration system of a chip according to any one of claims 1 to 5, comprising: The communication mode of the chip is set according to the state of the chip and / or the communication mode of FALSH stored in the mode register.

8. A communication mode configuration device for a chip, characterized in that: include: The setting module is used to set the communication mode of the chip according to the state of the chip and / or the FALSH communication mode stored in the mode register.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the program, the communication mode configuration method of the chip as claimed in claim 6 is implemented.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the communication mode configuration method of the chip as claimed in claim 6 is implemented.

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