Multi-core CPU working time sequence self-adjusting method and system and multi-core CPU

Abstract

The invention provides a multi-core CPU working time sequence self-adjusting method and system and a multi-core CPU. The CPU comprises a plurality of CPU cores and an on-chip network, and the on-chip network comprises a plurality of communication nodes used for being connected with the CPU cores respectively; inserting a delay adjustment circuit in the key communication node to obtain a feature node; the delay adjustment circuit comprises a plurality of network channels, and each network channel comprises a plurality of multiplexers which are connected in series; for any feature node, generating test data and pre-response data corresponding to the test data, and sending the test data to the CPU for operation; collecting actual response data output by the other corresponding feature node; and comparing the actual response data with the pre-response data, and generating a selection control signal for adjusting the working state of the multiplexer according to a comparison result. Based on the self-adjusting method, the time delay of the data and the clock signal can be dynamically adjusted according to the actual PVT condition of each CPU, it is ensured that the working time sequence meets the requirement, and therefore the chip yield is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of CPU design, and in particular to a multi-core CPU working timing self-adjustment method, system and multi-core CPU. Background Art

[0002] As chip manufacturing enters the sub-nanometer era, transistor performance is increasingly sensitive to changes in process (P), voltage (V), and temperature (T) (PVT). However, traditional digital circuit design is static, and the circuit structure cannot be changed after the chip is produced. Timing analysis and verification are also limited to static analysis. This method cannot be adjusted in real time according to the actual PVT conditions of each chip, and can only adopt a conservative design strategy to cover the worst case.

[0003] This conservative strategy leads to:

[0004] Performance limitation: To ensure that all chips can work properly under the worst PVT conditions, some performance will be sacrificed during the design.

[0005] Yield loss: Since it is impossible to dynamically optimize the PVT differences of each chip, some chips may fail to achieve the expected performance and be eliminated, resulting in a decrease in yield.

[0006] This problem is particularly prominent for ultra-large-scale chips such as multi-core CPUs and GPUs.

[0007] At present, dynamic adaptive design of digital circuits is mainly used in high-speed analog IO interfaces, such as PCIe. In the field of digital circuits, although there are some attempts, the application scope and effect are limited, mainly in the following two aspects.

[0008] 1. Dynamic adjustment of high-end CPU clock network: Some high-end CPUs use analog phase-locked loop (DLL) circuits to adjust the delay of clock signals reaching registers in real time according to the PVT differences of adjacent CPU subsystems to improve yield. However, this can only blindly align the clock signal delay and cannot confirm the correctness of the data flow in real time. In addition, the design and verification of analog DLL circuits are complex, time-consuming and labor-intensive.

[0009] 2. Chip node asynchronization: The important nodes of the chip are completely asynchronous, and data is exchanged through handshake, which can avoid the timing problems caused by PVT changes and improve the yield. However, the handshake process will increase the total delay of the data flow, resulting in a serious performance degradation.

[0010] In general, traditional static circuit design methods are unable to cope with the challenges of sub-nanometer chips becoming increasingly sensitive to PVT changes. Existing dynamic adaptive design methods have limitations and cannot take into account both high performance and high yield. Therefore, a new digital circuit design method is needed. Summary of the invention

[0011] The purpose of the present invention is to provide a multi-core CPU working timing self-adjustment method, system and multi-core CPU that can be dynamically adjusted according to the actual PVT conditions of the chip to optimize chip performance and yield.

[0012] In order to achieve the above object, the present invention provides a multi-core CPU working timing self-adjustment method, wherein the CPU comprises a plurality of CPU cores and an on-chip network, wherein the on-chip network comprises a plurality of communication nodes respectively used to connect to each of the CPU cores; the self-adjustment method comprises:

[0013] Acquire a critical path formed by two adjacent communication nodes on the on-chip network in the CPU, wherein the critical path is a path with a minimum delay time margin for data signal transmission on the on-chip network;

[0014] Inserting a delay adaptation circuit into the communication nodes of the critical path and several segments of paths adjacent to the critical path to obtain a characteristic node;

[0015] The delay adaptation circuit includes a plurality of network channels for processing each bit of data signal or clock signal respectively, and the network channels include a plurality of multiplexers connected in series, and the multiplexers are used to perform delay processing of different lengths on the data signal or clock signal passing therethrough according to different selection control signals;

[0016] For any of the characteristic nodes, generating test data and pre-response data corresponding to the test data, and sending the test data to the CPU for execution;

[0017] Collecting actual response data outputted by another corresponding characteristic node;

[0018] The actual response data is compared with the pre-response data, and a selection control signal for adjusting the working state of the multiplexer is generated according to the comparison result.

[0019] Preferably, the critical path includes a first critical path related to the setup time of the data signal and a second critical path related to the hold time of the data signal;

[0020] Inserting a delay adaptation circuit into communication nodes of the first critical path and several adjacent paths behind it;

[0021] A delay adaptation circuit is inserted into the communication nodes of the second critical path and several adjacent paths in front of the second critical path.

[0022] Preferably, a pull-through adaptation mode is included, in which any of the characteristic nodes are adapted one by one by a first method, and the first method includes:

[0023] For any of the characteristic nodes, use the current selection control signal to configure a number of the multiplexers in the network channel;

[0024] The actual response data is compared with the pre-response data, and if the two are consistent, the current selection control signal is saved; if the two are inconsistent, the selection control signal is adjusted according to a preset unit amplitude to generate a new selection control signal, and the test data and the pre-response data corresponding to the test data are regenerated to perform iterative testing until the actual response data is consistent with the pre-response data;

[0025] For any feature node, if the number of iterative tests exceeds the preset value, the test will be exited and a prompt signal will be issued.

[0026] Preferably, after the pull-through adaptation mode is executed, the characteristic nodes are optimized and adjusted through an optimization adaptation mode. In the optimization adaptation mode, any of the characteristic nodes are adapted one by one through a second method, and the second method includes:

[0027] For any of the characteristic nodes, the current selection control signal is adjusted according to a preset unit amplitude to improve the working timing margin of the path where the current characteristic node is located, and the adjusted selection control signal is used to configure the multiplexer;

[0028] The actual response data is compared with the pre-response data. If the two are consistent, the current selection control signal is adjusted again according to the preset unit amplitude to improve the working timing margin of the path where the current feature node is located, and the test data and the pre-response data corresponding to the test data are regenerated to perform iterative testing; if the two are inconsistent, the current selection control signal is reversely adjusted by a unit amplitude to reduce the working timing margin of the path where the current feature node is located, so as to obtain and save the final selection control signal.

[0029] Preferably, the number N of the characteristic nodes satisfies the following conditions:

[0030] 3≤N≤T1 / T2

[0031] Wherein, T1 is the clock period of the clock signal configured in the CPU, and T2 is the unit amplitude adopted by the single adjustment selection control signal.

[0032] Preferably, the multiplexer comprises a first channel and a second channel for transmitting a data signal or a clock signal, the first channel is directly connected to a high-speed signal line connected between a signal input point and an output point, and the second channels between a plurality of the multiplexers in the same transmission network channel are connected in series;

[0033] The selection control signal is used to select the multiplexer at each stage to transmit a bit data signal or a clock signal arriving therein through one of the first channel and the second channel.

[0034] Preferably, based on the comparison result of the actual response data and the pre-response data, if it is confirmed that the establishment time of the data signal is insufficient, the selection control signal is adjusted to increase the delay of the clock signal; if it is confirmed that the holding time of the data signal is insufficient, the selection control signal is adjusted to increase the delay of the data signal.

[0035] The present invention also provides a multi-core CPU, which includes a plurality of CPU cores and an on-chip network, wherein the on-chip network includes a plurality of communication nodes respectively used to connect to each of the CPU cores, and a delay adaptation circuit is inserted into the communication nodes of a critical path formed by two adjacent communication nodes in the on-chip network and a plurality of path segments adjacent to the critical path, wherein the critical path is a path with the minimum delay time margin for data signal transmission on the on-chip network;

[0036] The delay adaptation circuit includes a plurality of network channels for processing each bit of data signal or clock signal respectively. The network channels include a plurality of multiplexers connected in series. The multiplexers are used to perform delay processing of different lengths on the data signal or clock signal passing therethrough according to different selection control signals.

[0037] Preferably, the critical path includes a first critical path related to the setup time of the data signal and a second critical path related to the hold time of the data signal;

[0038] The delay adaptation circuit is inserted into the communication nodes of the first critical path and several adjacent paths behind it;

[0039] The delay adaptation circuit is inserted into the communication nodes of the second critical path and several adjacent paths in front of it.

[0040] Preferably, the multiplexer comprises a first channel and a second channel for transmitting a data signal or a clock signal, the first channel is directly connected to a high-speed signal line connected between a signal input point and an output point, and the second channels between a plurality of the multiplexers in the same transmission network channel are connected in series;

[0041] The selection control signal is used to select the multiplexer at each stage to transmit a bit data signal or a clock signal arriving therein through one of the first channel and the second channel.

[0042] The present invention also provides a multi-core CPU working timing self-adaptive system for adjusting the working timing of the CPU, wherein the CPU is as described in any one of claims 8 to 10, and the adaptation system comprises a test controller, a test data generator, and a response analyzer, wherein the test controller is communicatively connected with the test data generator, the response analyzer, and an on-chip network in the CPU to be tested;

[0043] The test data generator is communicatively connected with a feature node in the on-chip network, the feature node is a communication node having the delay adaptation circuit, the feature node includes a first feature node and a second feature node adjacent to each other, the test data generator is used to generate test data and pre-response data corresponding to the test data according to an instruction of the test controller, and provide the test data to the first feature node;

[0044] The response analyzer is communicatively connected to the feature node in the on-chip network, and is used to obtain actual response data corresponding to the test data output by the second feature node, and compare the actual response data with the pre-response data;

[0045] The test controller is used to control the actions of the test data generator and the response analyzer, generate a selection control signal according to the analysis result of the response analyzer, and configure the state of the corresponding multiplexer based on the selection control signal.

[0046] Preferably, the test controller is provided with a first control module, and the first control module is configured by the following first method, the first method comprising:

[0047] For any of the characteristic nodes, use the current selection control signal to configure a number of the multiplexers in the network channel;

[0048] The actual response data is compared with the pre-response data, and if the two are consistent, the current selection control signal is saved; if the two are inconsistent, the selection control signal is adjusted according to a preset unit amplitude to generate a new selection control signal, and the test data and the pre-response data corresponding to the test data are regenerated to perform iterative testing until the actual response data is consistent with the pre-response data;

[0049] For any feature node, if the number of iterative tests exceeds the preset value, the test will be exited and a prompt signal will be issued.

[0050] Preferably, the test controller is provided with a second control module, and the second control module is configured by the following second method, the second method comprising:

[0051] For any of the characteristic nodes, the current selection control signal is adjusted according to a preset unit amplitude to improve the working timing margin of the path where the current characteristic node is located, and the adjusted selection control signal is used to configure the multiplexer;

[0052] The actual response data is compared with the pre-response data. If the two are consistent, the current selection control signal is adjusted again according to the preset unit amplitude to improve the working timing margin of the path where the current feature node is located, and the test data and the pre-response data corresponding to the test data are regenerated to perform iterative testing; if the two are inconsistent, the current selection control signal is reversely adjusted by a unit amplitude to reduce the working timing margin of the path where the current feature node is located, so as to obtain and save the final selection control signal.

[0053] The present invention also provides a multi-core CPU working timing self-adjustment system, which includes:

[0054] one or more processors;

[0055] Memory;

[0056] and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the programs including instructions for executing the multi-core CPU working timing self-adaptation method as described above.

[0057] The present invention also provides a computer-readable storage medium, which includes a computer program, and the computer program can be executed by a processor to complete the multi-core CPU working timing self-adjustment method as described above.

[0058] Compared with the prior art, the multi-core CPU working timing self-adaptation method provided by the above technical solution of the present invention inserts a delay adaptation circuit on the communication nodes on the critical path and its adjacent paths. Through the delay adaptation circuit, the delay time of the communication nodes in the CPU under the actual operating conditions can be dynamically adjusted, that is, the delay of the data and clock signals can be dynamically adjusted according to the actual PVT situation of each CPU to ensure that the working timing meets the requirements, thereby improving the chip yield; in addition, by accurately adjusting the characteristic nodes, the data transmission efficiency in the on-chip network can be optimized, the data transmission delay can be reduced, and the overall performance can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 It is a planar structural diagram of the CPU in an embodiment of the present invention.

[0060] Figure 2 FIG. 4 is a planar structural diagram of a delay adaptation circuit in an embodiment of the present invention.

[0061] Figure 3 for Figure 2 A zoomed-in view of one of the network channels.

[0062] Figure 4 Figure 2 Diagram of the working principle of the network channel.

[0063] Figure 5 4 is a flow chart of the self-adaptation method in an embodiment of the present invention.

[0064] Figure 6 4 is an execution flow chart of the first method in an embodiment of the present invention.

[0065] Figure 7 This is an execution example of the pull-through mode in the embodiment of the present invention.

[0066] Figure 8 4 is an execution flow chart of the second method in an embodiment of the present invention.

[0067] Fig. 9 This is an execution example of the optimization adaptation mode in the embodiment of the present invention.

[0068] Fig.10 1 is a schematic diagram of the principle structure of the self-adaptive system in an embodiment of the present invention.

[0069] Fig.11 This is a connection diagram of the usage status of the self-adaptive system in an embodiment of the present invention. DETAILED DESCRIPTION

[0070] In order to explain the technical content, structural features, achieved objectives and effects of the present invention in detail, the following is a detailed description in conjunction with the implementation methods and the accompanying drawings.

[0071] For digital chips (such as CPUs), data is transmitted along a specific path through various circuit units, such as registers, logic gates, etc. It takes a certain amount of time for each circuit unit to process the signal, which is called "delay".

[0072] To this end, data transmission must meet certain timing requirements. For example, the data must be stable within a certain time period of the clock signal CKin in order to be correctly received by the next circuit unit.

[0073] In addition, the chip's process (P), voltage (V) and temperature (T) will affect the delay of the circuit unit. If "data adaptation" is not performed, the chip may have data transmission errors under certain PVT conditions, resulting in functional abnormalities.

[0074] Based on this, this embodiment discloses a multi-core CPU with a working timing self-adaptation function. The working timing adaptation refers to ensuring that data can be correctly transmitted in different situations by adjusting the delay on the data path.

[0075] like Figure 1 The CPU in this embodiment includes several CPU cores, on-chip networks, and interface modules. The CPU core is responsible for processing various data and instructions, and the interface module is responsible for exchanging data with external devices (such as memory, hard disk, etc.). The on-chip network is used to ensure that data can be transmitted quickly and efficiently within the CPU.

[0076] The on-chip network includes several communication nodes XP respectively used to connect to each CPU core. These communication nodes XP are responsible for forwarding and routing data to ensure that the data can reach the correct destination.

[0077] A delay adaptation circuit is inserted into the critical path formed by two adjacent communication nodes XP in the on-chip network and the communication nodes XP of several segments of paths adjacent to the critical path. The critical path is the path with the smallest delay time margin for the data signal Din transmitted on the on-chip network. In this embodiment, the critical path in the on-chip network can be obtained through the pre-silicon simulation process. That is, before the CPU chip is manufactured, the designer will perform a lot of simulation verification, including static timing analysis (STA). Potential critical paths in the design can be found through STA. Therefore, the critical path in the CPU can be obtained through STA.

[0078] like Figure 2 and Figure 3 The delay adaptation circuit includes a plurality of network channels W respectively used to process each bit of the data signal Din or the clock signal CKin. The network channel W includes a plurality of multiplexers F connected in series. The multiplexers F are used to perform delay processing of different lengths on the data signal Din or the clock signal CKin passing therethrough according to different selection control signals.

[0079] Specifically, in Figure 2 In the embodiment, since the data signal Din has n bits, there is one network channel W1 for transmitting the clock signal CKin and n network channels W2 for transmitting the data signal Din.

[0080] The network channel W1 has two input terminals and one output terminal. The two input terminals are used to receive the clock signal CKin and the selection control signal CKS respectively. The output terminal is used to provide the delayed clock signal CKin to the sending unit S corresponding to each data signal Din.

[0081] Any network channel W2 for transmitting a data signal Din has two input terminals and one output terminal. The two input terminals are used to receive the data signal Din and the selection control signal DS respectively, and the output terminal is used to provide the delayed data signal Din to the sending unit S to which it currently belongs.

[0082] The transmission unit S generates an output signal Dout which is transmitted to the next communication node XP from the received data signal Din based on the clock signal CKin.

[0083] In the multi-core CPU based on the above structure, since some communication nodes XP at key positions therein are inserted with delay adaptation circuits, the working timing of the CPU can be dynamically configured by selecting control signals based on the on-site environmental conditions where the CPU is located.

[0084] There are two timing parameters that affect the CPU's data transmission, one is the setup time and the other is the hold time. In digital circuits, the data signal Din cannot change infinitely fast in one clock cycle. In order to ensure that the data is sampled correctly, the setup time and hold time requirements must be met.

[0085] The setup time refers to the minimum time that the data signal Din must remain stable before the rising edge of the clock arrives; while the hold time refers to the minimum time that the data signal Din must remain stable after the rising edge of the clock arrives. If the delay of the clock signal CKin and the data signal Din does not match, it may lead to insufficient setup time or hold time, resulting in data sampling errors.

[0086] Based on this, the critical path includes a first critical path related to the setup time of the data signal Din and a second critical path related to the hold time of the data signal Din.

[0087] Then, a delay adaptation circuit is inserted into the communication nodes XP of the first critical path and several adjacent paths behind it; and a delay adaptation circuit is inserted into the communication nodes XP of the second critical path and several adjacent paths in front of it.

[0088] When configuring each multiplexer F in the network channel W by selecting the control signal to solve the CPU's working timing problem, if the setup time is insufficient (the data may not be ready in time, resulting in errors), this can be solved by increasing the delay time of the clock signal CKin; if the hold time is insufficient (the data may not be ready, also resulting in errors), this can be solved by increasing the delay time of the data signal Din.

[0089] like Figure 3The multiplexer F includes a first channel 0 and a second channel 1 for transmitting a data signal Din or a clock signal CKin. The first channel 0 is directly connected to a high-speed signal line connected between a signal input point and an output point, and the second channel 1 between multiple multiplexers F in the same transmission network channel W is connected in series.

[0090] The selection control signal is used to select each stage of the multiplexer F to transmit the data signal Din or the clock signal CKin thereto via one of the first channel 0 and the second channel 1 .

[0091] Specifically, the first channel 0 is a fast channel, and the second channel 1 is a delayed channel.

[0092] Multiplexer F is used as a fork in the signal transmission path, and different paths can be selected. Each fork has a "selection signal", that is, a selection control signal, which instructs the signal passing through the multiplexer F to select one of the paths. When the first channel 0 is selected, the signal goes directly to the next multiplexer F. When the second channel 1 is selected, since each multiplexer F has its own delay, the transmission time of the signal will be increased.

[0093] like Figure 4 , the selection control signal CKS for controlling the network channel W1 for processing the clock signal CKin is 00111, and the selection control signal DS for controlling the network channel W2 for processing the data signal Din is 00000. "0" is used to control the multiplexer F to select the first channel 0, and "1" is used to control the multiplexer F to select the second channel 1. Based on CKS "00111", the clock signal CKin is delayed by 200ps (picoseconds), and based on DS "00000", the data signal Din is delayed by 50ps.

[0094] In another preferred embodiment of the present invention, based on the multi-core CPU of the above structure, a multi-core CPU working timing self-adjustment method is also disclosed, such as Figure 5 , and refer to Figures 1 to 4 , the self-adaptation method includes the following process:

[0095] S10: For ease of description, the communication node XP inserted with the delay adaptation circuit is defined as a feature node. For any feature node, test data and pre-response data corresponding to the test data are generated, and the test data is sent to the current feature node.

[0096] S11: collecting actual response data of another corresponding characteristic node; for example, sending test data to characteristic node A, collecting actual response data of characteristic node B adjacent to characteristic node A;

[0097] S12: comparing the actual response data with the pre-response data;

[0098] S13: generating a selection control signal for adjusting the working state of the multiplexer F according to the comparison result.

[0099] On the other hand, the number of feature nodes N satisfies the following conditions:

[0100] 3≤N≤T1 / T2

[0101] Wherein, T1 is the clock period of the clock signal CKin configured in the CPU, and T2 is the unit amplitude.

[0102] For example, T1=500ps, T2=50ps, then the maximum value of the number of characteristic nodes N is 10, the minimum value is 3, and the preferred value is 5.

[0103] On the other hand, the self-adaptation method has two working modes, one is the pull-through adaptation mode, and the other is the optimization adaptation mode.

[0104] Through the pull-through mode, it is ensured that the CPU chip can correctly transmit data between each communication node XP in the current PVT environment, that is, to ensure the correctness of the function.

[0105] In this regard, in the pull-through adaptation mode, any feature node is adapted one by one by the first method, such as Figure 6 , the first method includes the following process:

[0106] S20: For any characteristic node, the current selection control signal is used to configure a plurality of multiplexers F in the network channel W; it should be noted that the default selection control signal is used to configure the network channel W for the first time;

[0107] S21: Generate test data and pre-response data corresponding to the test data, and send the test data to the current feature node;

[0108] S22: Collecting actual response data of another characteristic node adjacent to the characteristic node;

[0109] S23: Compare the actual response data with the pre-response data. If the two are consistent, proceed to S24. If the two are inconsistent, proceed to S25.

[0110] S24: Save the current selected control signal;

[0111] S25: The number of iteration tests K increases by 1;

[0112] S26: Is K equal to the preset threshold Max? If yes, proceed to S28; if no, proceed to S27;

[0113] S27: adjusting the selection control signal according to the preset unit amplitude to generate a new selection control signal, and returning to step S20;

[0114] S28: Exit the test and send a prompt signal, indicating that the current CPU is a defective product.

[0115] like Figure 7 , showing the iterative process of testing and timing adaptation of the CPU in pull-through mode. This example shows a critical path related to setup time detected in the pre-silicon timing simulation flow. This path is located between the communication nodes XP1 and XP2, which means that the timing margin of this path is small and is easily affected by PVT changes. To solve potential timing problems, delay adaptation circuits are also inserted on the three subsequent nodes (XP3, XP4, XP5) of this critical path.

[0116] After entering the pull-through mode, the following iterative steps will be performed:

[0117] (1) Start the test process using the default selection control signal configuration, and use steps S21 to S23 in the first method to detect that the timing of the critical path XP1=>XP2 does not meet the standard, such as Figure 7 The first line in shows that the timing margin of the path is not sufficient to meet the performance requirements in the current PVT environment.

[0118] (2) Use the first method above to start adjusting the delay of the XP2 node by gradually increasing the delay until the timing of the path reaches the standard.

[0119] (3) Check the timing feasibility of the subsequent nodes (XP2=>XP3, XP3=>XP4, XP4=>XP5) and find that the new path XP2=>XP3 has a timing problem and needs further iterative adjustment, such as Figure 7 The second line in .

[0120] (4) Use the first method above to adjust the delay of the XP3 node until the path timing meets the standard, such as Figure 7 The third line in .

[0121] (5) Check the timing feasibility of subsequent nodes and confirm that the path XP3=>XP4 still has timing problems and needs to be iterated further, such as Figure 7 The third line in .

[0122] (6) Use the first method above to adjust the delay of the XP4 node until the timing of the CP3=>CP4 path meets the standard, such as Figure 7 The fourth line in .

[0123] (7) Finally, the timing feasibility of all feature nodes is checked to confirm that the path XP4=>XP5 and other paths meet the timing requirements, so the iteration is stopped and ended.

[0124] For the optimization and adaptation mode, based on the pull-through mode, the timing margin of the critical path is further optimized to improve the CPU's tolerance to sudden situations such as voltage and temperature fluctuations, that is, to ensure the stability of the CPU operation.

[0125] In the optimization adaptation mode, any characteristic node is adapted one by one by the second method, such as Figure 8 , the second method includes:

[0126] S30: For any characteristic node, adjusting the current selection control signal according to a preset unit amplitude to improve the working timing margin of the path where the current characteristic node is located;

[0127] S31: using the adjusted selection control signal to configure a plurality of multiplexers F in the network structure;

[0128] S32: Generate test data and pre-response data corresponding to the test data, and send the test data to the current feature node;

[0129] S33: collecting actual response data of another characteristic node adjacent to the characteristic node;

[0130] S34: Compare the actual response data with the pre-response data. If the two are consistent, return to S30. If the two are inconsistent, enter S35.

[0131] S35: Reversely adjust the current selection control signal by a unit amplitude to reduce the working timing margin of the path where the current feature node is located;

[0132] S36: Save the final selection control signal and end the adaptation process.

[0133] like Fig. 9 , shows an example of the process of optimizing the adaptation mode. This example shows that based on the selected control signal configured in the pull-through mode process, fine-tuning is continued to improve the timing margin. The iterative adaptation process in this example is as follows:

[0134] Initial state:

[0135] When the optimization and adaptation mode starts, the delay configuration of each feature node in the CPU is inherited from the final result of the pull-through mode. At this time, the timing of all feature nodes meets the requirements and the data flow is correct.

[0136] Iteration process:

[0137] The optimization and adaptation mode adopts a tentative iterative optimization strategy to adjust the delay node by node and verify whether the CPU's working timing meets the requirements through a test process.

[0138] (1) Fine-tune the delay of XP2 by unit amplitude to further improve the timing margin of the XP1=>XP2 path. The node status after adjustment is as follows: Fig. 9 In the second row. At this time, through the steps S32 to S34 in the second method above, the path XP1=>XP2 is tested. Based on the test results, although the path XP1=>XP2 still has no timing problem, that is, the actual response data is consistent with the response data. However, in this example, since XP2 has been configured to the longest delay, the delay cannot be increased further, so the adjustment of XP2 is stopped and the next node XP3 is turned to.

[0139] (2) Fine-tune the delay of XP3 by unit amplitude to improve the timing margin of the XP2=>XP3 path, and gradually increase the delay of XP3 until the timing test result fails to meet the standard (reaches the limit), that is, an error occurs in the data flow, such as Fig. 9 The third row.

[0140] (3) Since the delay of XP3 was increased in the previous step, which caused the timing to fail to meet the standard, adjust the delay of XP3 back to the configuration when the most recent timing test met the standard, such as Fig. 9 The fourth line.

[0141] Thus, similar iterative optimization is continued for subsequent nodes (XP4, XP5...) according to the above steps until all configurable nodes reach the timing optimized state, that is, the timing margin of the critical path is increased as much as possible while ensuring the correctness of the data flow.

[0142] In another preferred embodiment of the present invention, a multi-core CPU working timing self-adaptive system is also disclosed, which is used to adjust the working timing of the CPU. The structure of the CPU is detailed in the above embodiment and will not be repeated here. Fig.10 and Fig.11 The adaptation system includes a test controller, a test data generator and a response analyzer, and the test controller is communicatively connected with the test data generator, the response analyzer and an on-chip network in the CPU to be tested.

[0143] A test data generator is communicatively connected to the feature nodes within the on-chip network. For ease of description, adjacent feature nodes are named as the first feature node and the second feature node, respectively. The test data generator is used to generate test data and pre-response data corresponding to the test data according to the instructions of the test controller, and provide the test data to the first feature node.

[0144] The response analyzer is connected to the characteristic node in the on-chip network for obtaining the actual response data corresponding to the test data output by the second characteristic node and comparing the actual response data with the pre-response data.

[0145] The test controller is used to control the actions of the test data generator and the response analyzer, generate a selection control signal according to the analysis result of the response analyzer, and configure the state of the corresponding multiplexer F based on the selection control signal.

[0146] The working principle of the self-adaptive system is detailed in the self-adaptive method in the above embodiment, which will not be repeated here.

[0147] In addition, the test controller is provided with a first control module and a second control module. The first control module is configured by the first method, and the second control module is configured by the second method.

[0148] The present invention also discloses another self-adaptive system, which includes one or more processors, a memory and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by the one or more processors, and the program includes instructions for executing the self-adaptive method as described above. The processor can adopt a general central processing unit (CPU), a microprocessor, an application specific integrated circuit (ASIC), or one or more integrated circuits, for executing related programs to implement the functions required to be executed by the modules in the self-adaptive system of the embodiment of the present application, or to execute the self-adaptive method of the method embodiment of the present application.

[0149] The present invention also discloses a computer-readable storage medium, which includes a computer program, and the computer program can be executed by a processor to complete the self-adaptation method as described above. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or a data center that includes one or more available media. The available medium can be a read-only memory (ROM), or a random access memory (RAM), or a magnetic medium, such as a floppy disk, a hard disk, a tape, a magnetic disk, or an optical medium, such as a digital versatile disc (DVD), or a semiconductor medium, such as a solid state disk (SSD).

[0150] The embodiment of the present application also discloses a computer program product or a computer program, which includes a computer instruction stored in a computer-readable storage medium. A processor of an electronic device reads the computer instruction from the computer-readable storage medium, and the processor executes the computer instruction, so that the electronic device performs the above self-adaptation method.

[0151] The above disclosure is only the preferred embodiment of the present invention, which certainly cannot be used to limit the scope of rights of the present invention. Therefore, equivalent changes made according to the scope of the patent application of the present invention are still within the scope covered by the present invention.

Claims

1. A multi-core CPU working timing self-adjustment method, characterized in that: The CPU includes a plurality of CPU cores and an on-chip network, wherein the on-chip network includes a plurality of communication nodes respectively used to connect to each of the CPU cores; the self-adaptation method includes: Acquire a critical path formed by two adjacent communication nodes on the on-chip network in the CPU, wherein the critical path is a path with a minimum delay time margin for data signal transmission on the on-chip network; Inserting a delay adaptation circuit into the communication nodes of the critical path and several segments of paths adjacent to the critical path to obtain a characteristic node; The delay adaptation circuit includes a plurality of network channels for processing each bit of data signal or clock signal respectively, and the network channels include a plurality of multiplexers connected in series, and the multiplexers are used to perform delay processing of different lengths on the data signal or clock signal passing therethrough according to different selection control signals; For any of the characteristic nodes, generating test data and pre-response data corresponding to the test data, and sending the test data to the CPU for execution; Collecting actual response data outputted by another corresponding characteristic node; The actual response data is compared with the pre-response data, and a selection control signal for adjusting the working state of the multiplexer is generated according to the comparison result.

2. The multi-core CPU working timing self-adjustment method according to claim 1, characterized in that: The critical path includes a first critical path related to the setup time of the data signal and a second critical path related to the hold time of the data signal; Inserting a delay adaptation circuit into communication nodes of the first critical path and several adjacent paths behind it; A delay adaptation circuit is inserted into the communication nodes of the second critical path and several adjacent segments of the paths in front of the second critical path.

3. The multi-core CPU working timing self-adjustment method according to claim 1, characterized in that: The method includes a pull-through adaptation mode, in which any of the feature nodes are adapted one by one by a first method, the first method including: For any of the characteristic nodes, use the current selection control signal to configure a number of the multiplexers in the network channel; The actual response data is compared with the pre-response data, and if the two are consistent, the current selection control signal is saved; if the two are inconsistent, the selection control signal is adjusted according to a preset unit amplitude to generate a new selection control signal, and the test data and the pre-response data corresponding to the test data are regenerated to perform iterative testing until the actual response data is consistent with the pre-response data; For any feature node, if the number of iterative tests exceeds the preset value, the test will be exited and a prompt signal will be issued.

4. The multi-core CPU working timing self-adjustment method according to claim 3, characterized in that: After the pull-through adaptation mode is executed, the characteristic nodes are optimized and adjusted through the optimization adaptation mode. In the optimization adaptation mode, any of the characteristic nodes are adapted one by one through a second method, and the second method includes: For any of the characteristic nodes, the current selection control signal is adjusted according to a preset unit amplitude to improve the working timing margin of the path where the current characteristic node is located, and the adjusted selection control signal is used to configure the multiplexer; The actual response data is compared with the pre-response data. If the two are consistent, the current selection control signal is adjusted again according to the preset unit amplitude to improve the working timing margin of the path where the current feature node is located, and the test data and the pre-response data corresponding to the test data are regenerated to perform iterative testing; if the two are inconsistent, the current selection control signal is reversely adjusted by a unit amplitude to reduce the working timing margin of the path where the current feature node is located, so as to obtain and save the final selection control signal.

5. The multi-core CPU working timing self-adjustment method according to claim 1, characterized in that: The number N of the characteristic nodes satisfies the following conditions: 3≤N≤T1 / T2 Wherein, T1 is the clock period of the clock signal configured in the CPU, and T2 is the unit amplitude adopted by the single adjustment selection control signal.

6. The multi-core CPU working timing self-adjustment method according to claim 1, characterized in that: The multiplexer comprises a first channel and a second channel for transmitting a data signal or a clock signal, the first channel is directly connected to a high-speed signal line connected between a signal input point and an output point, and the second channels between a plurality of the multiplexers in the same transmission network channel are connected in series; The selection control signal is used to select the multiplexer at each stage to transmit a bit data signal or a clock signal arriving therein through one of the first channel and the second channel.

7. The multi-core CPU working timing self-adjustment method according to claim 2, characterized in that: According to the comparison result of the actual response data and the pre-response data, if it is confirmed that the establishment time of the data signal is insufficient, the selection control signal is adjusted to increase the delay of the clock signal; if it is confirmed that the holding time of the data signal is insufficient, the selection control signal is adjusted to increase the delay of the data signal.

8. A multi-core CPU, characterized in that: The invention comprises a plurality of CPU cores and an on-chip network, wherein the on-chip network comprises a plurality of communication nodes respectively used to connect to each of the CPU cores, and a delay adaptation circuit is inserted into the communication nodes of a critical path formed by two adjacent communication nodes in the on-chip network and a plurality of path segments adjacent to the critical path, wherein the critical path is a path with the minimum delay time margin for the transmission of a data signal on the on-chip network; The delay adaptation circuit includes a plurality of network channels for processing each bit of data signal or clock signal respectively. The network channels include a plurality of multiplexers connected in series. The multiplexers are used to perform delay processing of different lengths on the data signal or clock signal passing therethrough according to different selection control signals.

9. The multi-core CPU according to claim 8, characterized in that: The critical path includes a first critical path related to the setup time of the data signal and a second critical path related to the hold time of the data signal; The delay adaptation circuit is inserted into the communication nodes of the first critical path and several adjacent paths behind it; The delay adaptation circuit is inserted into the communication nodes of the second critical path and several adjacent paths in front of it.

10. The multi-core CPU according to claim 8, characterized in that: The multiplexer comprises a first channel and a second channel for transmitting a data signal or a clock signal, the first channel is directly connected to a high-speed signal line connected between a signal input point and an output point, and the second channels between a plurality of the multiplexers in the same transmission network channel are connected in series; The selection control signal is used to select the multiplexer at each stage to transmit a bit data signal or a clock signal arriving therein through one of the first channel and the second channel.

11. A multi-core CPU working timing self-adaptive system, characterized in that: Used to adjust the working timing of a CPU, the CPU being as described in any one of claims 8 to 10, the adaptation system comprising a test controller, a test data generator and a response analyzer, the test controller being communicatively connected with the test data generator, the response analyzer and an on-chip network in the CPU to be tested; The test data generator is communicatively connected with a feature node in the on-chip network, the feature node is a communication node having the delay adaptation circuit, the feature node includes a first feature node and a second feature node adjacent to each other, the test data generator is used to generate test data and pre-response data corresponding to the test data according to an instruction of the test controller, and provide the test data to the first feature node; The response analyzer is communicatively connected to the feature node in the on-chip network, and is used to obtain actual response data corresponding to the test data output by the second feature node, and compare the actual response data with the pre-response data; The test controller is used to control the actions of the test data generator and the response analyzer, generate a selection control signal according to the analysis result of the response analyzer, and configure the state of the corresponding multiplexer based on the selection control signal.

12. The multi-core CPU working timing self-adjusting system according to claim 11, characterized in that: The test controller is provided with a first control module, and the first control module is configured using the following first method, the first method comprising: For any of the characteristic nodes, use the current selection control signal to configure a number of the multiplexers in the network channel; The actual response data is compared with the pre-response data, and if the two are consistent, the current selection control signal is saved; if the two are inconsistent, the selection control signal is adjusted according to a preset unit amplitude to generate a new selection control signal, and the test data and the pre-response data corresponding to the test data are regenerated to perform iterative testing until the actual response data is consistent with the pre-response data; For any feature node, if the number of iterative tests exceeds the preset value, the test will be exited and a prompt signal will be issued.

13. The multi-core CPU working timing self-adjusting system according to claim 11, characterized in that: The test controller is provided with a second control module, and the second control module is configured by the following second method, the second method comprising: For any of the characteristic nodes, the current selection control signal is adjusted according to a preset unit amplitude to improve the working timing margin of the path where the current characteristic node is located, and the adjusted selection control signal is used to configure the multiplexer; The actual response data is compared with the pre-response data. If the two are consistent, the current selection control signal is adjusted again according to the preset unit amplitude to improve the working timing margin of the path where the current feature node is located, and the test data and the pre-response data corresponding to the test data are regenerated to perform iterative testing; if the two are inconsistent, the current selection control signal is reversely adjusted by a unit amplitude to reduce the working timing margin of the path where the current feature node is located, so as to obtain and save the final selection control signal.

14. A multi-core CPU working timing self-adjusting system, characterized in that: include: one or more processors; Memory; And one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by the one or more processors, and the programs include instructions for executing the multi-core CPU working timing self-adjustment method as described in any one of claims 1 to 7.

15. A computer-readable storage medium, characterized in that: It includes a computer program, which can be executed by a processor to complete the multi-core CPU working timing self-adjustment method as described in any one of claims 1 to 7.

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