Pixel unit, display panel and display device

Abstract

The present invention proposes a pixel unit, a display panel and a display device, wherein the pixel unit includes a pixel electrode, a first storage capacitor, a second storage capacitor, a first switching circuit, a second switching circuit, a data switch and a polarity switching circuit. In the previous frame, the pixel unit can receive a row scanning signal and a data signal, and the polarity switching circuit can switch to output a first level signal. At this time, the data switch, the first switching circuit and the second switching circuit are switched accordingly and output the data signal to the pixel electrode. In the next frame, the polarity switching circuit switches to output a second level signal, the data switch has no data signal output, and the first switching circuit and the second switching circuit switch output. At this time, the pixel electrode receives a data signal of opposite polarity to achieve polarity switching, and in two adjacent frames, the two storage capacitors store data voltages of the same polarity, thereby avoiding large-scale voltage charging and discharging and reducing charging and discharging power consumption.

Description

Technical Field

[0001] The present invention belongs to the technical field of display panels, and in particular relates to a pixel unit, a display panel and a display device. Background Art

[0002] Liquid crystal display panels have the advantages of high resolution, accurate color reproduction, simple structure, and high stability. Traditional liquid crystal display panels achieve different grayscale displays by controlling the deflection of liquid crystal molecules to control the amount of polarized light passing through.

[0003] In a liquid crystal display panel, voltage is applied on both sides of the liquid crystal layer to drive the liquid crystal molecules to rotate. If a single-direction electric field is applied to the liquid crystal molecules for a long time, the liquid crystal molecules will polarize. After the liquid crystal molecules are polarized, the response characteristics of the liquid crystal will change, such as slow response speed, uneven display, etc. Therefore, polarity switching is required to avoid polarization of the liquid crystal molecules.

[0004] When switching polarity, the storage capacitor in the pixel unit needs to perform a large-amplitude charge and discharge action to ensure that the liquid crystal pixel is displayed according to the correct polarity. The large-amplitude charge and discharge action increases the power consumption of the circuit. Summary of the invention

[0005] The object of the present invention is to provide a pixel unit, aiming to solve the problem of high power consumption of traditional pixel units when polarity switching occurs.

[0006] A first aspect of an embodiment of the present invention provides a pixel unit, comprising:

[0007] Pixel electrode;

[0008] a first storage capacitor;

[0009] a second storage capacitor;

[0010] a first switching circuit, wherein a first input end of the first switching circuit is connected to a first end of the first storage capacitor, a second input end of the first switching circuit, a second end of the first storage capacitor and a first end of the second storage capacitor are connected, an output end of the first switching circuit is connected to the pixel electrode, and the first switching circuit is triggered by a first level signal to connect the first input end and the output end, or is triggered by a second level signal to connect the second input end and the output end;

[0011] a second switching circuit, wherein an input end of the second switching circuit is connected to a common electrode end, a first output end of the second switching circuit, a second end of the first storage capacitor and a first end of the second storage capacitor are connected, a second output end of the second switching circuit is connected to a second end of the second storage capacitor, and the second switching circuit is triggered by the first level signal to connect the input end and the first output end, or is triggered by the second level signal to connect the input end and the second output end;

[0012] A data switch, wherein an input end of the data switch is connected to a data line, an output end of the data switch, a first end of the first storage capacitor, and a second end of the second storage capacitor are connected, and the data switch is used to transmit a data signal of the data line every frame interval and when a row scanning signal of the row is received;

[0013] The polarity switching circuit is connected to the scan line, the first switching circuit and the second switching circuit respectively, and the polarity switching circuit is used to switch the polarity of the output level every time a row of scan signal transmitted by the scan line is received.

[0014] Optionally, the first switching circuit includes a first transistor and a second transistor;

[0015] The first end of the first transistor constitutes the first input end of the first switching circuit, the first end of the second transistor constitutes the second input end of the first switching circuit, the second end of the first transistor and the second end of the second transistor constitute the output end of the first switching circuit, and the control end of the first transistor and the control end of the second transistor are connected to constitute the control end of the first switching circuit.

[0016] Optionally, the second switching circuit includes a third transistor and a fourth transistor;

[0017] The first end of the third transistor and the first end of the fourth transistor are connected to form the input end of the second switching circuit, the second end of the third transistor forms the first output end of the second switching circuit, and the second end of the fourth transistor forms the second output end of the second switching circuit.

[0018] Optionally, the data switch includes a fifth transistor;

[0019] The first end of the fifth transistor is connected to the data line, the control end of the fifth transistor is connected to the scan line, the second end of the fifth transistor constitutes the output end of the data switch, and the data line receives a data signal every frame.

[0020] Optionally, the polarity switching circuit includes a sixth transistor, a seventh transistor, an eighth transistor, a first resistor, a first capacitor, a second capacitor and an AND gate;

[0021] The first input terminal of the AND gate is connected to the scan line, the second input terminal of the AND gate, the first terminal of the first capacitor and the first terminal of the eighth transistor are connected, the output terminal of the AND gate is connected to the first terminal of the sixth transistor, the second terminal of the sixth transistor is connected to the control terminal of the seventh transistor, the control terminal of the sixth transistor, the control terminal of the eighth transistor and the enable signal terminal are connected, the first terminal of the seventh transistor is connected to the common electrode terminal, the second terminal of the seventh transistor, the first terminal of the first resistor, the second terminal of the eighth transistor and the first terminal of the second capacitor are connected to form the output terminal of the polarity switching circuit, the second terminal of the first resistor is connected to the first positive voltage terminal, and the second terminal of the first capacitor and the second terminal of the second capacitor are grounded;

[0022] The enable signal terminal is used to input an enable signal, and the enable signal has the same phase as the row scanning signal input by the scanning line.

[0023] Optionally, the AND gate includes a first diode, a second diode and a second resistor;

[0024] The cathode of the first diode constitutes the first input terminal of the AND gate, the cathode of the second diode constitutes the second input terminal of the AND gate, the anode of the first diode, the anode of the second diode and the first end of the second resistor are connected to constitute the output terminal of the AND gate, and the second end of the second resistor is connected to the second positive voltage terminal.

[0025] Optionally, the enable signal has a polarity opposite to that of a row scan signal input to the scan line, and the enable signal terminal is connected to a scan line to which the pixel units in the next row are connected.

[0026] Optionally, the pixel unit further includes a voltage-stabilizing capacitor, a first end of the voltage-stabilizing capacitor is connected to the output end of the polarity switching circuit, and a second end of the voltage-stabilizing capacitor is grounded.

[0027] A second aspect of an embodiment of the present invention provides a display panel, comprising a plurality of scan lines, a plurality of data lines, and a plurality of pixel units as described above, wherein the pixel units are respectively connected to one of the scan lines and one of the data lines.

[0028] A third aspect of an embodiment of the present invention provides a display device, comprising a display panel driving circuit and the display panel as described above, wherein the display panel driving circuit is connected to the display panel.

[0029] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: the above-mentioned pixel unit includes a pixel electrode, a first storage capacitor, a second storage capacitor, a first switching circuit, a second switching circuit, a data switch and a polarity switching circuit. In the previous frame, the pixel unit can receive a row scanning signal and a data signal, and the polarity switching circuit can switch to output a first level signal. At this time, the data switch, the first switching circuit and the second switching circuit are switched accordingly, and the data signal is output to the pixel electrode. In the next frame, the polarity switching circuit switches to output a second level signal, the data switch has no data signal output, and the first switching circuit and the second switching circuit switch output. At this time, the pixel electrode receives a data signal of opposite polarity to achieve polarity switching, and in two adjacent frames, the two storage capacitors store data voltages of the same polarity, thereby avoiding large-scale voltage charging and discharging and reducing charging and discharging power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0031] Figure 1 A schematic diagram of the structure of a display panel provided in Embodiment 1 and Embodiment 3 of the present invention;

[0032] Figure 2 A schematic diagram of the structure of a pixel unit provided in Embodiment 1 of the present invention;

[0033] Figure 3 A schematic diagram of the signal timing of a pixel unit provided in the first embodiment of the present invention;

[0034] Figure 4 A first circuit diagram of a pixel unit provided in Embodiment 2 of the present invention;

[0035] Figure 5 A schematic diagram of the signal timing of a pixel unit provided in the second embodiment of the present invention;

[0036] Figure 6 A second circuit diagram of a pixel unit provided in the second embodiment of the present invention;

[0037] Figure 7 This is a schematic diagram of the structure of a display device provided in Embodiment 4 of the present invention.

[0038] Among them, the reference numerals in the figures are:

[0039] 100, display panel; 200, display panel driving circuit; 210, source driving circuit; 220, gate driving circuit; 230, timing controller; 10, pixel unit; 11, pixel electrode; 12, first switching circuit; 13, second switching circuit; 14, data switch; 15, polarity switching circuit;

[0040] T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; C1, first capacitor; C2, second capacitor; Cst1, first storage capacitor; Cst2, second storage capacitor; Cboost, voltage stabilizing capacitor; R1, first resistor; R2, second resistor; U1, AND gate; D1, first diode; D2, second diode; S, data line; G, scan line;

[0041] t1, first time sequence; t2, second time sequence; t3, third time sequence; t4, fourth time sequence; t5, fifth time sequence; t6, sixth time sequence; t7, seventh time sequence; t8, eighth time sequence;

[0042] Scan1, row scanning signal; Vdata, data signal; Vcom1, first common electrode voltage; Vcom2, second common electrode voltage; EN, enable signal. DETAILED DESCRIPTION

[0043] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0044] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0045] Embodiment 1

[0046] A first aspect of an embodiment of the present invention provides a pixel unit 10, such as Figure 1As shown, the pixel units 10 are arranged in an array on an array substrate of a display panel 100. The array substrate also includes a plurality of scan lines G, a plurality of data lines S and a common electrode terminal. The common electrode terminal has a first common electrode voltage Vcom1. Each pixel unit 10 is connected to a data line S and a scan line G respectively. The display panel 100 also includes a color filter substrate arranged opposite to the array substrate and a liquid crystal layer arranged between the array substrate and the color filter substrate. Figure 2 As shown, the pixel unit 10 includes a pixel electrode 11, a color filter layer and a common electrode layer are arranged on the color filter substrate, the common electrode layer has a second common electrode voltage Vcom2, and a plurality of scanning lines G are used to input a row scanning signal Scan1 to the pixel units 10 of each row row by row, and when the pixel units 10 of each row receive the row scanning signal Scan1, the data line S outputs a corresponding data signal Vdata to the pixel units 10 of the corresponding row, and the pixel unit 10 generates a corresponding voltage signal to the pixel electrode 11 based on the received row scanning signal Scan1 and the data signal Vdata, and the voltage signal input to the pixel electrode 11 and the second common electrode voltage Vcom2 form a driving voltage, and drive the liquid crystal deflection of the liquid crystal layer, and cooperate with the color filter layer to control the pixel unit 10 to display the corresponding image information.

[0047] In an optional embodiment, the first common electrode voltage Vcom1 and the second common electrode voltage Vcom2 are equal in voltage, for example, 5V, 8V, etc.

[0048] Among them, the row scanning signal Scan1 mainly refers to the row start signal, and the opposite of the row start signal is the row close signal. During row-by-row scanning, multiple scan lines G receive the row start signal in sequence according to the corresponding timing, and other rows that are not selected for scanning input the row close signal.

[0049] In order to reduce the power consumption of the pixel unit 10, in this embodiment, the pixel unit 10 includes:

[0050] Pixel electrode 11;

[0051] A first storage capacitor Cst1;

[0052] A second storage capacitor Cst2;

[0053] A first switching circuit 12, wherein a first input terminal of the first switching circuit 12 is connected to a first terminal of a first storage capacitor Cst1, a second input terminal of the first switching circuit 12, a second terminal of the first storage capacitor Cst1 and a first terminal of a second storage capacitor Cst2 are connected, an output terminal of the first switching circuit 12 is connected to a pixel electrode 11, and the first switching circuit 12 is triggered by a first level signal to connect the first input terminal and the output terminal, or is triggered by a second level signal to connect the second input terminal and the output terminal;

[0054] A second switching circuit 13, wherein the input end of the second switching circuit 13 is connected to the common electrode end, the first output end of the second switching circuit 13, the second end of the first storage capacitor Cst1 and the first end of the second storage capacitor Cst2 are connected, the second output end of the second switching circuit 13 is connected to the second end of the second storage capacitor Cst2, and the second switching circuit 13 is triggered by the first level signal to connect the input end and the first output end, or is triggered by the second level signal to connect the input end and the second output end;

[0055] A data switch 14, wherein an input end of the data switch 14 is connected to the data line S, an output end of the data switch 14, a first end of the first storage capacitor Cst1 and a second end of the second storage capacitor Cst2 are connected, and the data switch 14 is used to transmit a data signal Vdata of the data line S every frame interval and when receiving a row scan signal Scan1 of the row where the data switch 14 is located;

[0056] The polarity switching circuit 15 is connected to the scan line G, the first switching circuit 12 and the second switching circuit 13 respectively. The polarity switching circuit 15 is used to switch the polarity of the output level every time a scan signal Scan1 transmitted by the scan line G is received.

[0057] In this embodiment, the first level signal and the second level signal are high and low level signals with opposite polarities.

[0058] like Figure 3 As shown, assuming that in the first timing t1, in the i-th frame and when the pixel unit 10 of the current row receives the row scanning signal Scan1, the polarity switching circuit 15 can switch to output the first level signal. At this time, the first switching circuit 12 switches to connect its own first input terminal and output terminal, that is, connects the first terminal of the first storage capacitor Cst1 with the pixel electrode 11, and the second switching circuit 13 switches to connect its own input terminal and first output terminal, that is, connects the common electrode terminal with the second terminal of the first storage capacitor Cst1, and the first common electrode voltage Vcom1 of the common electrode terminal is output to the second terminal of the first storage capacitor Cst1. At the same time, the data switch 14 can receive the data signal Vdata of the row in the frame, and transmit the data signal Vdata to the first end of the first storage capacitor Cst1 and the second end of the second storage capacitor Cst2. The data signal Vdata charges the first storage capacitor Cst1 and the second storage capacitor Cst2. The potential of the first end of the first storage capacitor Cst1 and the second end of the second storage capacitor Cst2 reaches the voltage of the data signal Vdata. The voltage difference between the first end and the second end of the first storage capacitor Cst1 and the voltage difference between the second end and the first end of the second storage capacitor Cst2 are:

[0059] ΔV=Vdata-Vcom1;

[0060] At the same time, the data signal Vdata is output to the pixel electrode 11 through the first switching circuit 12. The voltage of the pixel electrode 11 is equal to the voltage of the data signal Vdata, that is, Vdata. The voltage of the pixel electrode 11 and the second common electrode voltage Vcom2 form a first driving voltage of a first polarity. The first driving voltage is Vdata-Vcom2. For example, assuming that the first common electrode voltage Vcom1 and the second common electrode voltage Vcom2 are 8V, the data signal Vdata is 10V, and correspondingly, the first driving voltage is 2V.

[0061] In the second timing sequence t2, in the current frame and when scanning to the next row, there is no row scanning signal Scan1 input to the row where the pixel unit 10 and the data switch 14 are located. Correspondingly, the data switch 14 has no data signal Vdata output, the polarity switching circuit 15 maintains the output of the first level signal, and the voltage of the pixel electrode 11 is maintained at the voltage of the data signal Vdata.

[0062] In the third timing t3, when switching to the i+1th frame and the pixel unit 10 of the current row receives the row scan signal Scan1, since the data switch 14 outputs the data signal Vdata due to the interval frame, at this time, the data switch 14 has no data signal Vdata output, and the polarity switching circuit 15 switches the polarity of the output level after receiving the next row scan signal Scan1, that is, outputs the second level signal, the second switching circuit 13 switches and connects its own input end and the second output end, that is, outputs the first common electrode voltage Vcom1 to the second end of the second storage capacitor Cst2, and the first switching circuit 12 switches and connects its own second input end and output end, that is, connects the first end of the second storage capacitor Cst2 with the pixel electrode 11, at this time, the second storage capacitor Cst2 stores the voltage difference stored in the previous frame, and the voltage of the first end of the second storage capacitor Cst2 and the voltage of the pixel electrode 11 are Vcom1-(Vdata-Vcom 1)=2Vcom1-Vdata, correspondingly, the voltage of the pixel electrode 11 and the second common electrode voltage Vcom2 form a second driving voltage of a second polarity, and the second driving voltage is 2Vcom1-Vdata-Vcom2. Because Vcom1=Vcom2, the second driving voltage is equal to Vcom2-Vdata. The second driving voltage and the first driving voltage are of opposite polarity and have the same value, thereby realizing the polarity switching of the driving signal. For example, assuming that the first common electrode voltage Vcom1 and the second common electrode voltage Vcom2 are 8V, and the data signal Vdata is 10V, correspondingly, the voltage of the first end of the second storage capacitor Cst2 and the voltage of the pixel electrode 11 are 6V, the second driving voltage is -2V, and 10V is a positive polarity data signal Vdata relative to 8V, and 6V is a negative polarity data signal Vdata relative to 8V, and the difference between the two and the first common electrode voltage Vcom1 is equal.

[0063] Among them, in adjacent frames, the first storage capacitor Cst1 and the second storage capacitor Cst2 simultaneously store the data signal Vdata of the same polarity, and when the polarity is switched, the first storage capacitor Cst1 and the second storage capacitor Cst2 have no large polarity voltage charging and discharging process, thereby achieving the purpose of reducing power consumption.

[0064] In the fourth timing sequence t4, in the next frame and when scanning the next row, the pixel unit 10 of the current row does not receive the row scanning signal Scan1, the polarity switching circuit 15 maintains outputting the second level signal, and at the same time, the data switch 14 has no data signal Vdata output, and the voltage of the pixel electrode 11 is maintained at 2Vcom1-Vdata.

[0065] In the fifth timing sequence t5, in the i+2th frame, the row scan signal Scan1 is output to the pixel unit 10 of the current row for the third time, the polarity switching circuit 15 switches to output the first level signal, and the data switch 14 can output the data signal Vdata, that is, the pixel unit 10 in the fifth timing sequence t5 repeats the working state in the first timing sequence t1, and outputs the reloaded data signal Vdata to the pixel electrode 11, and the reloaded data signal Vdata has the same polarity as the data signal Vdata loaded in the i-th frame, that is, the polarity of the data line S connected to the pixel unit 10 can remain unchanged.

[0066] Similarly, in the sixth timing sequence t6, in the i+2th frame, when the row scan signal Scan1 scans to the next row, the pixel unit 10 of the current row does not receive the row scan signal Scan1, and the pixel unit 10 in the sixth timing sequence t6 repeats the working state in the second timing sequence t2 and maintains outputting the reloaded data signal Vdata to the pixel electrode 11.

[0067] By setting the first switching circuit 12, the second switching circuit 13 and the polarity switching circuit 15, two adjacent frames can be used as a frame cycle. During the frame scanning process, the polarity on the data line S can remain unchanged, and the polarity of the driving voltage of the liquid crystal layer can be switched in the frame cycle, thereby reducing the polarization of the liquid crystal layer and improving the working reliability of the liquid crystal layer.

[0068] Among them, the first switching circuit 12, the second switching circuit 13 and the data switch 14 can adopt corresponding switching circuits, switching devices, etc., and the polarity switching circuit 15 can adopt circuit structures such as latches, triggers, logic gates, etc., and the specific structure is not limited.

[0069] Furthermore, in order to maintain the output level of the polarity switching circuit 15 in each frame, in an optional embodiment, as Figure 2As shown, the pixel unit 10 also includes a voltage-stabilizing capacitor Cboost, a first end of the voltage-stabilizing capacitor Cboost is connected to the output end of the polarity switching circuit 15, and a second end of the voltage-stabilizing capacitor Cboost is grounded. The voltage-stabilizing capacitor Cboost can be charged when the polarity switching circuit 15 outputs different levels, and maintains continuous output of the first level signal or the second level signal in each frame.

[0070] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: the above-mentioned pixel unit 10 includes a pixel electrode 11, a first storage capacitor Cst1, a second storage capacitor Cst2, a first switching circuit 12, a second switching circuit 13, a data switch 14 and a polarity switching circuit 15. In the previous frame, the pixel unit 10 can receive a row scan signal Scan1 and a data signal Vdata, and the polarity switching circuit 15 can switch to output a first level signal. At this time, the data switch 14, the first switching circuit 12 and the second switching circuit 13 are switched accordingly, and the data signal Vdata is output to the pixel electrode 11. In the next frame, the polarity switching circuit 15 switches to output a second level signal, the data switch 14 has no data signal Vdata output, and the first switching circuit 12 and the second switching circuit 13 switch outputs. At this time, the pixel electrode 11 receives a data signal Vdata of opposite polarity to achieve polarity switching, and in two adjacent frames, the two storage capacitors store data voltages of the same polarity, thereby avoiding large-scale voltage charging and discharging and reducing charging and discharging power consumption.

[0071] Embodiment 2

[0072] In an alternative embodiment, if Figure 4 As shown, the first switching circuit 12 includes a first transistor T1 and a second transistor T2;

[0073] The first end of the first transistor T1 constitutes the first input end of the first switching circuit 12, the first end of the second transistor T2 constitutes the second input end of the first switching circuit 12, the second end of the first transistor T1 and the second end of the second transistor T2 constitute the output end of the first switching circuit 12, and the control end of the first transistor T1 and the control end of the second transistor T2 are connected to constitute the control end of the first switching circuit 12.

[0074] The second switching circuit 13 includes a third transistor T3 and a fourth transistor T4;

[0075] The first end of the third transistor T3 and the first end of the fourth transistor T4 are connected to form the input end of the second switching circuit 13, the second end of the third transistor T3 forms the first output end of the second switching circuit 13, and the second end of the fourth transistor T4 forms the second output end of the second switching circuit 13.

[0076] The data switch 14 includes a fifth transistor T5;

[0077] A first end of the fifth transistor T5 is connected to the data line S, a control end of the fifth transistor T5 is connected to the scan line G, a second end of the fifth transistor T5 constitutes an output end of the data switch 14, and the data line S receives a data signal Vdata every frame.

[0078] The polarity switching circuit 15 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a first resistor R1, a first capacitor C1, a second capacitor C2 and an AND gate U1;

[0079] A first input terminal of the AND gate U1 is connected to the scan line G, a second input terminal of the AND gate U1, a first terminal of the first capacitor C1 and a first terminal of the eighth transistor T8 are connected, an output terminal of the AND gate U1 is connected to a first terminal of the sixth transistor T6, a second terminal of the sixth transistor T6 is connected to a control terminal of the seventh transistor T7, a control terminal of the sixth transistor T6, a control terminal of the eighth transistor T8 and an enable signal terminal are connected, a first terminal of the seventh transistor T7 is connected to a common electrode terminal, a second terminal of the seventh transistor T7, a first terminal of the first resistor R1, a second terminal of the eighth transistor T8 and a first terminal of the second capacitor C2 are connected to form an output terminal of the polarity switching circuit 15, a second terminal of the first resistor R1 is connected to a first positive voltage terminal VDD1, and a second terminal of the first capacitor C1 and a second terminal of the second capacitor C2 are grounded;

[0080] The enable signal terminal is used to input an enable signal EN. The enable signal EN and the row scan signal Scan1 input from the scan line G have the same phase.

[0081] In this embodiment, Figure 5As shown, assuming that in the first timing sequence t1, in the i-th frame and when the pixel unit 10 of the current row receives the row scanning signal Scan1, the row scanning signal Scan1 is high, the initial terminal voltage of the first capacitor C1 is low, the AND gate U1 outputs a low level, the enable signal EN is low at the first timing sequence t1, the sixth transistor T6 is turned on, the seventh transistor T7 and the eighth transistor T8 are turned off, at this time, the polarity switching circuit 15 switches to output a high potential first level signal, the first transistor T1 and the third transistor T3 are turned on, the second transistor T2 and the fourth transistor T4 are turned off, the first switching circuit 12 connects the first end of the first storage capacitor Cst1 to the pixel electrode 11, and the second switching circuit 13 switches to connect the common electrode end to the second end of the first storage capacitor Cst1. The first common electrode voltage Vcom1 at the common electrode end is output to the second end of the first storage capacitor Cst1. At the same time, the fifth transistor T5 can receive the data signal Vdata of the row in the frame, and is triggered to be turned on under the control of the row scan signal Scan1, and transmits the data signal Vdata to the first end of the first storage capacitor Cst1 and the second end of the second storage capacitor Cst2. The data signal Vdata charges the first storage capacitor Cst1 and the second storage capacitor Cst2. The potential of the first end of the first storage capacitor Cst1 and the second end of the second storage capacitor Cst2 reaches the voltage of the data signal Vdata. The voltage difference between the first end and the second end of the first storage capacitor Cst1 and the voltage difference between the second end and the first end of the second storage capacitor Cst2 are:

[0082] ΔV=Vdata-Vcom1;

[0083] At the same time, the data signal Vdata is output to the pixel electrode 11 through the first switching circuit 12. The voltage of the pixel electrode 11 is equal to the voltage of the data signal Vdata, that is, Vdata. The voltage of the pixel electrode 11 and the second common electrode voltage Vcom2 form a first driving voltage of a first polarity. The first driving voltage is Vdata-Vcom2.

[0084] In the second timing t2, in the current frame and when scanning to the next line, the enable signal EN is at a high level, the row scan signal Scan1 is at a low level, the eighth transistor T8 is turned on, and the polarity switching circuit 15 is maintained at a high level due to the existence of the second capacitor C2. Correspondingly, the first transistor T1 and the third transistor T3 are turned on, the second transistor T2, the fourth transistor T4 and the fifth transistor T5 are turned off, the second capacitor C2 charges the first capacitor C1, and the terminal voltage of the first capacitor C1 gradually rises to a high potential.

[0085] In the third timing t3, when switching to the i+1th frame and the pixel unit 10 of the current row receives the row scan signal Scan1, since the data line S outputs the data signal Vdata at intervals, at this time, the data switch 14 has no data signal Vdata output, and the polarity switching circuit 15 outputs a high level after receiving the next row scan signal Scan1, and the AND gate U1 outputs a high level, the sixth transistor T6 is turned on, the eighth transistor T8 is turned off, and the seventh transistor T7 receives a high level trigger to turn on, the polarity switching circuit 15 switches to output a low-level second level signal, the second transistor T2 and the fourth transistor T4 are turned on, the first transistor T1 and the third transistor T3 are turned off, and the second switching circuit 13 switches to connect its own input terminal and the second output terminal, and outputs the first common electrode voltage Vcom1 to the second end of the second storage capacitor Cst2. And the first switching circuit 12 switches and connects its own second input terminal and output terminal, and connects the first terminal of the second storage capacitor Cst2 with the pixel electrode 11. At this time, the second storage capacitor Cst2 stores the voltage difference stored in the previous frame, and the voltage of the first terminal of the second storage capacitor Cst2 and the voltage of the pixel electrode 11 are Vcom1-(Vdata-Vcom1)=2Vcom1-Vdata. Correspondingly, the voltage of the pixel electrode 11 and the second common electrode voltage Vcom2 form a second driving voltage of a second polarity. The second driving voltage is 2Vcom1-Vdata-Vcom2. Because Vcom1=Vcom2, the second driving voltage is equal to Vcom2-Vdata. The second driving voltage and the first driving voltage are of opposite polarity and have equal values, thereby realizing the polarity switching of the driving signal.

[0086] Among them, in adjacent frames, the first storage capacitor Cst1 and the second storage capacitor Cst2 simultaneously store the data signal Vdata of the same polarity, and when the polarity is switched, the first storage capacitor Cst1 and the second storage capacitor Cst2 have no large polarity voltage charging and discharging process, thereby achieving the purpose of reducing power consumption.

[0087] In the fourth timing sequence t4, in the next frame and when scanning the next row, the pixel unit 10 of the current row does not receive the row scanning signal Scan1, and the polarity switching circuit 15 maintains the output of the second level signal due to the existence of the second capacitor C2. At the same time, the fifth transistor T5 has no data signal Vdata output, and the voltage of the pixel electrode 11 is maintained at 2Vcom1-Vdata.

[0088] In the fifth timing sequence t5, in the i+2 frame, the row scan signal Scan1 is output to the pixel unit 10 of the current row for the third time, the polarity switching circuit 15 switches to output the first level signal, and the fifth transistor T5 is triggered to be turned on, and the data line S can output the data signal Vdata, and the fifth transistor T5 can transmit the newly loaded data signal Vdata, that is, in the fifth timing sequence t5, the pixel unit 10 repeats the working state in the first timing sequence t1, and outputs the reloaded data signal Vdata to the pixel electrode 11, and the reloaded data signal Vdata has the same polarity as the data signal Vdata loaded in the i-th frame, that is, the polarity of the data line S connected to the pixel unit 10 can remain unchanged.

[0089] Similarly, in the sixth timing sequence t6, in the i+2th frame, when the row scan signal Scan1 scans to the next row, the pixel unit 10 of the current row does not receive the row scan signal Scan1, and the pixel unit 10 in the sixth timing sequence t6 repeats the working state in the second timing sequence t2 and maintains outputting the reloaded data signal Vdata to the pixel electrode 11.

[0090] By setting the first switching circuit 12, the second switching circuit 13 and the polarity switching circuit 15, two adjacent frames can be used as a frame cycle. During the frame scanning process, the polarity on the data line S can remain unchanged, and the polarity of the driving voltage of the liquid crystal layer can be switched in the frame cycle, thereby reducing the polarization of the liquid crystal layer and improving the working reliability of the liquid crystal layer.

[0091] Among them, the sixth transistor T6 and the eighth transistor T8 are transistors of opposite types, for example, the sixth transistor T6 is an N-channel transistor, the eighth transistor T8 is a P-channel transistor, or the sixth transistor T6 is a P-channel transistor, the eighth transistor T8 is an N-channel transistor, and the seventh transistor T7 receives a high level trigger to turn on, and the seventh transistor T7 can be an N-channel transistor.

[0092] Correspondingly, according to the triggering method of the level signal, the first transistor T1, the third transistor T3 and the fifth transistor T5 can use the same type of transistors. In an optional embodiment, the first transistor T1, the third transistor T3 and the fifth transistor T5 can use N-channel transistors, the second transistor T2 and the fourth transistor T4 can use the same type of transistors, and the first transistor T1 and the second transistor T2 are transistors of opposite types. In an optional embodiment, the second transistor T2 and the fourth transistor T4 can use P-channel transistors.

[0093] The AND gate U1 may be a logic gate in a logic circuit, or may be composed of components. In an optional embodiment, in order to simplify the circuit structure, as shown in FIG. Figure 6 As shown, the AND gate U1 includes a first diode D1, a second diode D2 and a second resistor R2;

[0094] The cathode of the first diode D1 constitutes the first input terminal of the AND gate U1, the cathode of the second diode D2 constitutes the second input terminal of the AND gate U1, the anode of the first diode D1, the anode of the second diode D2 and the first end of the second resistor R2 are connected to form the output terminal of the AND gate U1, and the second end of the second resistor R2 is connected to the second positive voltage terminal VDD2.

[0095] In this embodiment, in the previous frame, when the cathode of the first diode D1 inputs the row scanning signal Scan1, the first diode D1 is turned off, and since the terminal voltage of the first capacitor C1 is at a low level, the second diode D2 is turned on, and the second diode D2 outputs a low level to the sixth transistor T6.

[0096] And in the previous frame, when the cathode of the first diode D1 is not input with the row scan signal Scan1 of the current row, the first diode D1 is turned on, the terminal voltage of the first capacitor C1 is high potential, the second diode D2 is turned on or off, and the first diode D1 outputs a low level.

[0097] And in the next frame, the row scan signal Scan1 is input to the cathode of the first diode D1, and the terminal voltage of the first capacitor C1 is at a high level. At this time, the first diode D1 and the second diode D2 are turned off, and the AND gate U1 outputs a high level to the sixth transistor T6. By adopting the first diode D1 and the second diode D2 and the second resistor R2, the function of the AND gate U1 can be realized and the circuit structure can be simplified.

[0098] Among them, the enable signal EN can use a clock signal, and the enable signal EN can be the same or different in polarity from the row scan signal Scan1 input to the current row. For example, when the polarity is the same, the sixth transistor T6 is adjusted to an N-channel transistor, and the eighth transistor T8 is adjusted to a P-channel transistor. When the row scan signal Scan1 is input to the current row, the sixth transistor T6 is turned on and the eighth transistor T8 is turned off. When the row scan signal Scan1 is not input to the current row, that is, when the row shutdown signal is input, the sixth transistor T6 is turned off and the eighth transistor T8 is turned on.

[0099] On the contrary, when the polarity is opposite, the sixth transistor T6 can be adjusted to a P-channel transistor, and the eighth transistor T8 can be adjusted to an N-channel transistor. When the row scan signal Scan1 is input to this row, the sixth transistor T6 is turned on and the eighth transistor T8 is turned off. When the row scan signal Scan1 is not input to this row, the sixth transistor T6 is turned off and the eighth transistor T8 is turned on.

[0100] In order to reduce the setting of additional signal terminals and simplify the circuit structure of the pixel unit 10 and the array substrate, in an optional embodiment, the enable signal EN is opposite in polarity to the row scan signal Scan1 input by the scan line G, the enable signal EN terminal is connected to the scan line G connected to the next row of pixel units 10, and the enable signal EN terminal inputs the row scan signal Scan1 input by the next row of scan line G. When scanning to the current row, the row scan signal Scan1 of the current row is high, and the row scan signal Scan1 input by the pixel units 10 of the next row is low; and when scanning to the next row, the row scan signal Scan1 of the current row is switched to a low level, and the row scan signal Scan1 input by the pixel units 10 of the next row is high, and the two have opposite polarities in the same frame.

[0101] Embodiment 3

[0102] like Figure 1 As shown, the second aspect of the embodiment of the present invention provides a display panel 100, which includes a plurality of scan lines G, a plurality of data lines S and a plurality of pixel units 10. The specific structure of the pixel unit 10 refers to the above embodiment. Since the display panel 100 adopts all the technical solutions of all the above embodiments, it at least has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described one by one here. Among them, the pixel unit 10 is connected to a scan line G and a data line S respectively.

[0103] The pixel units 10 are arranged in an array on an array substrate of a display panel 100. The array substrate further includes a plurality of scan lines G, a plurality of data lines S and a common electrode terminal. The common electrode terminal has a first common electrode voltage Vcom1. Each pixel unit 10 is connected to a data line S and a scan line G respectively. The display panel 100 further includes a color filter substrate disposed opposite to the array substrate and a liquid crystal layer disposed between the array substrate and the color filter substrate. Figure 2 As shown, the pixel unit 10 includes a pixel electrode 11, a color filter layer and a common electrode layer are arranged on the color filter substrate, the common electrode layer has a second common electrode voltage Vcom2, and a plurality of scanning lines G are used to input a row scanning signal Scan1 to the pixel units 10 of each row row by row, and when the pixel units 10 of each row receive the row scanning signal Scan1, the data line S outputs a corresponding data signal Vdata to the pixel units 10 of the corresponding row, and the pixel unit 10 generates a corresponding voltage signal to the pixel electrode 11 based on the received row scanning signal Scan1 and the data signal Vdata, and the voltage signal input to the pixel electrode 11 and the second common electrode voltage Vcom2 form a driving voltage, and drive the liquid crystal deflection of the liquid crystal layer, and cooperate with the color filter layer to control the pixel unit 10 to display the corresponding image information.

[0104] In an optional embodiment, the first common electrode voltage Vcom1 and the second common electrode voltage Vcom2 are equal in voltage, for example, 5V, 8V, etc.

[0105] Embodiment 4

[0106] like Figure 7 As shown, the third aspect of the embodiment of the present invention provides a display device, which includes a display panel drive circuit 200 and a display panel 100. The specific structure of the display panel 100 refers to the above embodiment. Since the display device adopts all the technical solutions of all the above embodiments, it at least has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described one by one here. Among them, the display panel drive circuit 200 is connected to the display panel 100.

[0107] In this embodiment, the driving circuit 200 of the display panel may include a timing controller 230, a source driving circuit 210 and a gate driving circuit 220. The timing controller 230 is used to control the gate driving circuit 220 to output a row scanning signal Scan1 to each row scanning line G row by row, and to control the source driving circuit 210 to output a data signal Vdata to each column data line S. The timing controller 230 also controls the source driving circuit 210 to output the data signal Vdata every other frame, so that two adjacent frames can be used as a frame cycle. During the frame scanning process, the polarity on the data line S can remain unchanged, and the pixel unit 10 switches the polarity of the driving voltage of the liquid crystal layer in the frame cycle, thereby reducing the polarization of the liquid crystal layer and improving the working reliability of the liquid crystal layer.

[0108] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A pixel unit, characterized in that: include: Pixel electrode; a first storage capacitor; a second storage capacitor; a first switching circuit, wherein a first input end of the first switching circuit is connected to a first end of the first storage capacitor, a second input end of the first switching circuit, a second end of the first storage capacitor and a first end of the second storage capacitor are connected, an output end of the first switching circuit is connected to the pixel electrode, and the first switching circuit is triggered by a first level signal to connect the first input end and the output end, or is triggered by a second level signal to connect the second input end and the output end; a second switching circuit, wherein an input end of the second switching circuit is connected to a common electrode end, a first output end of the second switching circuit, a second end of the first storage capacitor and a first end of the second storage capacitor are connected, a second output end of the second switching circuit is connected to a second end of the second storage capacitor, and the second switching circuit is triggered by the first level signal to connect the input end and the first output end, or is triggered by the second level signal to connect the input end and the second output end; A data switch, wherein an input end of the data switch is connected to a data line, an output end of the data switch, a first end of the first storage capacitor, and a second end of the second storage capacitor are connected, and the data switch is used to transmit a data signal of the data line every frame interval and when a row scanning signal of the row is received; A polarity switching circuit is respectively connected to the scan line, the control end of the first switching circuit and the control end of the second switching circuit. The polarity switching circuit is used to output the first level signal or the second level signal, and switch the polarity of the output level each time a row of scan signal transmitted by the scan line is received. The first level signal and the second level signal are high and low level signals with opposite polarities.

2. The pixel unit according to claim 1, characterized in that: The first switching circuit includes a first transistor and a second transistor; The first end of the first transistor constitutes the first input end of the first switching circuit, the first end of the second transistor constitutes the second input end of the first switching circuit, the second end of the first transistor and the second end of the second transistor constitute the output end of the first switching circuit, and the control end of the first transistor and the control end of the second transistor are connected to constitute the control end of the first switching circuit.

3. The pixel unit according to claim 1, characterized in that: The second switching circuit includes a third transistor and a fourth transistor; The first end of the third transistor and the first end of the fourth transistor are connected to form the input end of the second switching circuit, the second end of the third transistor forms the first output end of the second switching circuit, and the second end of the fourth transistor forms the second output end of the second switching circuit.

4. The pixel unit according to claim 1, characterized in that: The data switch comprises a fifth transistor; The first end of the fifth transistor is connected to the data line, the control end of the fifth transistor is connected to the scan line, the second end of the fifth transistor constitutes the output end of the data switch, and the data line receives a data signal every frame.

5. The pixel unit according to any one of claims 1 to 4, characterized in that: The polarity switching circuit includes a sixth transistor, a seventh transistor, an eighth transistor, a first resistor, a first capacitor, a second capacitor and an AND gate; The first input terminal of the AND gate is connected to the scan line, the second input terminal of the AND gate, the first terminal of the first capacitor and the first terminal of the eighth transistor are connected, the output terminal of the AND gate is connected to the first terminal of the sixth transistor, the second terminal of the sixth transistor is connected to the control terminal of the seventh transistor, the control terminal of the sixth transistor, the control terminal of the eighth transistor and the enable signal terminal are connected, the first terminal of the seventh transistor is connected to the common electrode terminal, the second terminal of the seventh transistor, the first terminal of the first resistor, the second terminal of the eighth transistor and the first terminal of the second capacitor are connected to form the output terminal of the polarity switching circuit, the second terminal of the first resistor is connected to the first positive voltage terminal, and the second terminal of the first capacitor and the second terminal of the second capacitor are grounded; The enable signal terminal is used to input an enable signal, and the enable signal has the same phase as the row scanning signal input by the scanning line.

6. The pixel unit according to claim 5, characterized in that: The AND gate includes a first diode, a second diode and a second resistor; The cathode of the first diode constitutes the first input terminal of the AND gate, the cathode of the second diode constitutes the second input terminal of the AND gate, the anode of the first diode, the anode of the second diode and the first end of the second resistor are connected to constitute the output terminal of the AND gate, and the second end of the second resistor is connected to the second positive voltage terminal.

7. The pixel unit according to claim 5, characterized in that: The enable signal has a polarity opposite to that of a row scan signal inputted by the scan line, and the enable signal terminal is connected to a scan line connected to the pixel units of the next row.

8. The pixel unit according to claim 1, characterized in that: The pixel unit further includes a voltage-stabilizing capacitor, a first end of the voltage-stabilizing capacitor is connected to the output end of the polarity switching circuit, and a second end of the voltage-stabilizing capacitor is grounded.

9. A display panel, characterized in that: The invention comprises a plurality of scan lines, a plurality of data lines and a plurality of pixel units according to any one of claims 1 to 8, wherein the pixel units are respectively connected to one of the scan lines and one of the data lines.

10. A display device, characterized in that: The invention comprises a display panel driving circuit and the display panel as claimed in claim 9, wherein the display panel driving circuit is connected to the display panel.

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