Data reading circuit for nonvolatile memory and nonvolatile memory

Abstract

The present invention discloses a data reading circuit for a nonvolatile memory and a nonvolatile memory. The nonvolatile memory includes at least one nonvolatile storage unit, which includes at least a switch unit and a nonvolatile storage unit connected in series. The data reading circuit includes: a gate circuit, wherein the first end of the gate circuit is connected to the nonvolatile storage unit through a bit line; a clamp circuit, wherein the first end of the clamp circuit is connected to the second end of the gate circuit; an amplifier circuit, wherein the first end of the amplifier circuit is connected to the second end of the clamp circuit, the second end of the amplifier circuit is used to receive a reference signal, and the third end of the amplifier circuit is used to output an amplified identification signal; and a pull-down circuit, wherein the first end of the pull-down circuit is connected to the second end of the gate circuit and the first end of the clamp circuit, and the second end of the pull-down circuit is grounded. The data reading circuit can reduce the VWL required when the switch unit is turned on, thereby reducing leakage current.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to a data reading circuit for a non-volatile memory and a non-volatile memory. Background Art

[0002] In the related art, in order to ensure that the gate tube can be turned on, the architecture of the non-volatile memory usually requires a larger VWL (word line voltage). At the same time, the larger the VML value, the greater the leakage current of the gate tube. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, one object of the present invention is to provide a data reading circuit for a non-volatile memory, which can reduce the VWL required when the switch unit is turned on and reduce the leakage current.

[0004] A second objective of the present invention is to provide a non-volatile memory.

[0005] A third objective of the present invention is to provide a control method for a non-volatile memory.

[0006] A fourth objective of the present invention is to provide an electronic device.

[0007] In order to solve the above problems, an embodiment of the first aspect of the present invention proposes a data reading circuit for a non-volatile memory, wherein the non-volatile memory includes at least one non-volatile storage unit, and the non-volatile storage unit at least includes a switching unit and a non-volatile storage unit connected in series, and the data reading circuit includes: a gate circuit, a first end of the gate circuit is connected to the non-volatile storage unit through a bit line; a clamp circuit, a first end of the clamp circuit is connected to a second end of the gate circuit; an amplifier circuit, a first end of the amplifier circuit is connected to a second end of the clamp circuit, the second end of the amplifier circuit is used to receive a reference signal, and the third end of the amplifier circuit is used to output an amplified identification signal; a pull-down circuit, a first end of the pull-down circuit is connected to the second end of the gate circuit and the first end of the clamp circuit, and the second end of the pull-down circuit is grounded.

[0008] According to the data reading circuit for a non-volatile memory of an embodiment of the present invention, before the non-volatile memory read operation, a pull-down control signal is sent to the pull-down circuit, and the pull-down circuit pulls down the clamping voltage, thereby reducing the clamping voltage when the switch unit is turned on, thereby reducing the word line voltage required when the switch unit is turned on, achieving the effect of starting the switch unit at a low voltage, and also reducing the leakage current.

[0009] In some embodiments, the pull-down circuit includes: a first MOS transistor, the gate of the first MOS transistor is used to receive the pull-down control signal, the drain of the first MOS transistor is connected to the second end of the gate circuit and the first end of the clamping circuit, and the source of the first MOS transistor is grounded.

[0010] In some embodiments, the gate circuit includes: a second MOS transistor, the gate of the second MOS transistor is used to receive an isolation enable signal, the drain of the second MOS transistor is connected to the non-volatile storage unit through the bit line, and the source of the second MOS transistor is respectively connected to the first end of the clamping circuit and the first end of the pull-down circuit.

[0011] In some embodiments, the clamping circuit includes: an inverter, the input end of the inverter is connected to the source of the second MOS tube; a third MOS tube, the gate of the third MOS tube is connected to the output end of the inverter, the drain of the third MOS tube is connected to the input end of the inverter and the source of the second MOS tube, and the source of the third MOS tube is connected to the first end of the amplifier circuit.

[0012] In some embodiments, the amplification circuit includes: a fourth MOS tube, the gate of the fourth MOS tube is used to receive a read enable signal, and the drain of the fourth MOS tube is connected to the source of the third MOS tube; a fifth MOS tube, the gate of the fifth MOS tube is used to receive a bias signal, the drain of the fifth MOS tube is connected to the source of the fourth MOS tube, and the source of the fifth MOS tube is grounded; a comparator, the positive input terminal of the comparator is connected to the drain of the fourth MOS tube and the source of the third MOS tube, the reverse input terminal of the comparator is connected to a reference power supply to receive the reference signal, and the output terminal of the comparator is used to output the amplified identification signal.

[0013] A second aspect of the present invention provides a nonvolatile memory, which includes at least one nonvolatile storage unit, wherein the nonvolatile storage unit includes at least a switching unit and a nonvolatile storage unit connected in series; and a data reading circuit for the nonvolatile memory of the above embodiment, wherein the data reading circuit is connected to the nonvolatile storage unit through a bit line.

[0014] According to the nonvolatile memory of the embodiment of the present invention, the VWL required for turning on the switch unit is reduced by the pull-down circuit in the data reading circuit, thereby solving the turn-on problem of the gate tube under low voltage and reducing leakage current.

[0015] In some embodiments, the non-volatile memory cell includes one or more of RRAM, MRAM, FERAM, and PCRAM.

[0016] In some embodiments, the switch unit includes at least a gate transistor.

[0017] A third aspect of the present invention provides a control method for the above non-volatile memory, the control method comprising: when the switch unit is turned on, sending a pull-down control signal to the pull-down circuit to pull down the clamping voltage of the clamping circuit.

[0018] According to the control method of the non-volatile memory of the embodiment of the present invention, when the switch unit is turned on, a pull-down control signal is sent to the pull-down circuit to pull down the clamping voltage of the clamping circuit, thereby reducing the VWL required when the switch unit is turned on and reducing the leakage current.

[0019] In some embodiments, the control method further includes: after determining that the switch unit is turned on, sending a shutdown control signal to the pull-down circuit to stop the pull-down operation of the pull-down circuit.

[0020] In some embodiments, the control method further includes: after the switch unit is turned on and the pull-down operation of the pull-down circuit is turned off, performing a read / write operation on a non-volatile storage unit corresponding to the switch unit.

[0021] A fourth aspect of the present invention provides an electronic device, comprising the non-volatile memory of the above embodiment.

[0022] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0024] Figure 1 is a schematic diagram of an original non-volatile memory;

[0025] Figure 2 is a schematic diagram of a non-volatile memory according to an embodiment of the present invention;

[0026] Figure 3 is a structural block diagram of a non-volatile memory according to an embodiment of the present invention;

[0027] Figure 4 is a schematic diagram of a nonvolatile storage unit according to an embodiment of the present invention;

[0028] Figure 5 FIG. 4 is a timing diagram of a non-volatile memory according to an embodiment of the present invention.

[0029] Reference numerals:

[0030] Non-volatile memory 1000;

[0031] Data reading circuit 100; non-volatile storage unit 200; switch unit 300; non-volatile storage unit 400;

[0032] Gate circuit 10; clamp circuit 20; amplifier circuit 30; pull-down circuit 40;

[0033] A first MOS tube M1; a second MOS tube M2; a third MOS tube M3; an inverter D1; a fourth MOS tube M4; a fifth MOS tube M5; and a comparator U1. DETAILED DESCRIPTION

[0034] Embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present invention are described in detail below.

[0035] In the related art, the architecture of non-volatile memory is as follows Figure 1 As shown, in this architecture, in order to more accurately distinguish data0 / data1, the corresponding VC is clamped at V1 level when reading data0, and the V1 range is 0v~vdd; when reading data1, V (VC)>V1. Based on this, before the read and write operation, the selector tube, namely the Selector, needs to be turned on first. The Selector has a turn-on threshold voltage (VTH_selector), that is, the selector can only be turned on when the voltage difference across the selector is greater than VTH_selector. Therefore, the word line voltage VWL>VTH-selector+V1+VDS_M1+V_ReRAM condition needs to be met to turn on the Selector, where V1 is the clamping voltage of VC when reading data0; VDS_M1 is the cross voltage between the source / drain of the MOS tube M1; and V_ReRAM is the cross voltage between the two ends of the memory ReRAM. At the same time, if the word line voltage is larger, the leakage current will also increase accordingly.

[0036] In order to solve the above problems, a first embodiment of the present invention provides a data reading circuit for a non-volatile memory, wherein the data reading circuit can reduce the VWL required when a switch unit is turned on, thereby reducing leakage current.

[0037] Reference below Figure 2 and Figure 3A data reading circuit 100 for a nonvolatile memory 1000 according to an embodiment of the present invention is described. The nonvolatile memory 1000 includes at least one nonvolatile storage unit 200. The nonvolatile storage unit 200 includes at least a switch unit 300 and a nonvolatile storage unit 400 connected in series. The data reading circuit 100 includes a gate circuit 10, a clamp circuit 20, an amplifier circuit 30 and a pull-down circuit 40.

[0038] Among them, the first end of the gate circuit 10 is connected to the non-volatile storage unit 200 through the bit line; the first end of the clamp circuit 20 is connected to the second end of the gate circuit 10; the first end of the amplifier circuit 30 is connected to the second end of the clamp circuit 20, the second end of the amplifier circuit 30 is used to receive a reference signal, and the third end of the amplifier circuit 30 is used to output an amplified identification signal; the first end of the pull-down circuit 40 is connected to the second end of the gate circuit 10 and the first end of the clamp circuit 20, and the second end of the pull-down circuit 40 is grounded.

[0039] Specifically, before the non-volatile memory 1000 performs a read and write operation, the switch unit 300 needs to be turned on. The gate tube is taken as an example of the switch unit 300 for explanation below. Before turning on the gate tube, the present application sends a pull-down control signal to the pull-down circuit 40, and the pull-down circuit 40 pulls down the clamping voltage of the clamping circuit 20, so that the clamping voltage is pulled down to the ground. Therefore, the gate tube can be turned on only by satisfying the condition of word line voltage VWL>VTH-selector+VDS_M1+V_ReRAM, that is, the voltage required to turn on the gate tube reduces the clamping voltage V1, thereby achieving the effect of starting the gate tube at a low voltage, and also solving the leakage problem caused by the large word line voltage.

[0040] In some embodiments, when the first end of the gate circuit 10 is connected to the nonvolatile storage unit 200 through the bit line, the first end of the gate circuit 10 can be connected to the switch unit 300 through the bit line, or, Figure 2 As shown, the first end of the gate circuit 10 is connected to the non-volatile memory cell 400 through a bit line, which is not limited.

[0041] In which, taking the non-volatile memory 1000 including nine non-volatile storage units 200 as an example, the nine non-volatile storage units 200 are arranged in an array, each row of non-volatile storage units 200 is connected to the same word line, and each column of non-volatile storage units 200 is connected to the same bit line. Figure 2 and Figure 4 As shown, a plurality of nonvolatile storage units 200 form a 3×3 array, wherein BL0, BL1 and BL3 are three bit lines, the nonvolatile storage unit 400 is connected to the first end of the gate circuit 10 through the corresponding bit lines, and WL, WL1 and WL2 are three word lines.

[0042] According to the data reading circuit 100 for the non-volatile memory 1000 of the embodiment of the present invention, before the non-volatile memory 1000 is read, a pull-down control signal is sent to the pull-down circuit 40, and the pull-down circuit 40 pulls down the clamping voltage, so that the clamping voltage can be reduced when the switch unit 300 is turned on, thereby reducing the word line voltage required when the switch unit 300 is turned on, achieving the effect of starting the switch unit 300 at a low voltage, and also reducing the leakage current.

[0043] In some embodiments, Figure 2 As shown, the pull-down circuit 40 includes a first MOS transistor M1.

[0044] The gate of the first MOS transistor M1 is used to receive a pull-down control signal, the drain of the first MOS transistor M1 is connected to the second end of the gate circuit and the first end of the clamp circuit 20 , and the source of the first MOS transistor M1 is grounded.

[0045] Specifically, the gate of the first MOS transistor M1 is used to receive a pull-down control signal. When the pull-down control signal is not activated, the first MOS transistor M1 remains turned off; when the pull-down control signal is activated, the first MOS transistor M1 is turned on. Since the source of the first MOS transistor M1 is grounded, the clamping voltage is pulled down to 0. Therefore, the present application reduces the VWL required when the switch unit 300 is turned on by pulling down the clamping voltage. Furthermore, after the switch unit 300 is turned on, the first MOS transistor M1 is turned off, and the non-volatile memory 1000 can perform normal data reading and writing.

[0046] In some embodiments, Figure 2 As shown, the gate level circuit 10 includes a second MOS transistor M2.

[0047] Among them, the gate of the second MOS transistor M2 is used to receive the isolation enable signal, the drain of the second MOS transistor M2 is connected to the non-volatile storage unit 200 through the bit line, and the source of the second MOS transistor M2 is respectively connected to the first end of the clamping circuit 20 and the first end of the pull-down circuit 40.

[0048] Specifically, the second MOS transistor M2 is used to isolate the non-volatile storage unit 200 and the clamping circuit 20, and to prevent the high voltage from being transmitted to the low voltage element and damaging the low voltage element by isolating the enable signal SA_GATE.

[0049] In some embodiments, Figure 2 As shown, the clamping circuit 20 includes an inverter D1 and a third MOS transistor M3.

[0050] The input end of the inverter D1 is connected to the source of the second MOS tube M2; the gate of the third MOS tube M3 is connected to the output end of the inverter D1, the drain of the third MOS tube M3 is connected to the input end of the inverter D1 and the source of the second MOS tube M2, and the source of the third MOS tube M3 is connected to the first end of the amplifier circuit 30.

[0051] Specifically, the input voltage of the inverter D1, i.e., the clamping voltage, is VC, and the output voltage of the inverter D1, i.e., the gate voltage of the second MOS tube M2, is VG. When the non-volatile memory unit 400 reads data 0, the clamping voltage VC is controlled within a preset voltage range; when reading data 1, the clamping voltage VC is controlled to be greater than the preset voltage range, so that the reading of data 0 and data 1 can be accurately distinguished, wherein the preset voltage range can be set according to actual conditions, for example, the preset voltage range is set to 0V-V1, and V1 can be set according to actual conditions, and no specific limitation is made here.

[0052] In some embodiments, Figure 2 As shown, the amplifier circuit 30 includes a fourth MOS transistor M4, a fifth MOS transistor M5 and a comparator U1.

[0053] Among them, the gate of the fourth MOS tube M4 is used to receive the read enable signal, that is, EN, and the drain of the fourth MOS tube M4 is connected to the source of the third MOS tube M3; the gate of the fifth MOS tube M5 is used to receive the bias signal, that is, NBIAS, the drain of the fifth MOS tube M5 is connected to the source of the fourth MOS tube M4, and the source of the fifth MOS tube M5 is grounded; the positive input end of the comparator U1 is connected to the drain of the fourth MOS tube M4 and the source of the third MOS tube M3, the reverse input end of the comparator U1 is connected to the reference power supply to receive the reference signal, and the output end of the comparator U1 is used to output the amplified identification signal, that is, DOUT.

[0054] Specifically, when the non-volatile memory 1000 performs a read and write operation, the switch unit 300 needs to be turned on. The gate tube is taken as an example of the switch unit 300 for explanation below. VWL should be greater than the sum of VTH-selector, V1, VDS_M1 and V_ReRAM, wherein VTH-selector is the turn-on threshold voltage of the gate tube, VDS_M1 is the cross-voltage between the source and the drain of the second MOS tube, and V_ReRAM is the cross-voltage across the non-volatile memory unit 400. In order to reduce the word line voltage when the gate tube is turned on, the present application pulls down the clamping voltage through the pull-down circuit 40 to pull the clamping voltage down to 0. Therefore, when the gate tube is turned on, VWL only needs to be greater than the sum of VTH-selector, VDS_M1 and V_ReRAM, thereby reducing the VWL required when the gate tube is turned on.

[0055] In addition, it should be noted that, for the MOS tube elements mentioned in the above-mentioned application, their source and drain structures are substantially the same. Based on this, when setting the connection relationship of the MOS tube elements, the source and drain of the MOS tube elements can be interchanged in essence, and this can be set according to actual conditions, and no specific restrictions are made here.

[0056] The second embodiment of the present invention provides a non-volatile memory 1000, such as Figure 2 and Figure 3 As shown, the nonvolatile memory 1000 includes at least one nonvolatile memory unit 200 and a data reading circuit 100 for a nonvolatile memory.

[0057] The nonvolatile storage unit 200 at least includes a switch unit 300 and a nonvolatile storage unit 400 , and the data reading circuit 100 is connected to the nonvolatile storage unit 200 via a bit line.

[0058] According to the nonvolatile memory 1000 of the embodiment of the present invention, the pull-down circuit 40 in the data reading circuit 100 reduces the VWL required for turning on the switch unit 300, thereby solving the turn-on problem of the switch unit 300 at low voltage and reducing leakage current.

[0059] In some embodiments, the non-volatile memory cell includes one or more of RRAM, MRAM, FERAM, and PCRAM. Figure 2 A schematic diagram of a non-volatile memory 1000 is shown.

[0060] In some embodiments, the switch unit 300 can be a two-terminal switch device or a gate tube. For example, the switch unit 300 can adopt a bidirectional threshold switch device (OTS, Ovonic Threshold Switch), a unidirectional threshold switch device, a threshold switch device based on ion migration, a threshold switch device based on metal-insulator transition, a conductive bridge threshold switch type gate tube or a barrier type gate tube, etc., without limitation.

[0061] For example, Figure 2 Specifically, the nonvolatile memory 1000 of the present application reduces the VWL required for turning on the gate tube through the pull-down circuit 40 in the data reading circuit 100, thereby solving the conduction problem of the gate tube under low voltage and reducing leakage current.

[0062] A third aspect of the present invention provides a control method for the non-volatile memory of the above embodiment. The control method includes sending a pull-down control signal to the pull-down circuit to pull down the clamping voltage of the clamping circuit when the switch unit is turned on.

[0063] Specifically, when the switch unit 300 is turned on, a pull-down control signal is sent to the pull-down circuit 40, and the first MOS tube M1 is controlled to be turned on by the pull-down control signal, and the clamping voltage of the clamping circuit 20 is pulled down to 0, thereby reducing the VWL required when the gate tube is turned on and reducing the leakage current.

[0064] According to the control method of the non-volatile memory of the embodiment of the present invention, when the switch unit 300 is turned on, a pull-down control signal is sent to the pull-down circuit 40 to pull down the clamping voltage of the clamping circuit 20, thereby reducing the VWL required when the switch unit 300 is turned on, thereby reducing the leakage current.

[0065] In some embodiments, the control method further includes sending a shutdown control signal to the pull-down circuit to stop the pull-down operation of the pull-down circuit after determining that the switch unit is turned on.

[0066] Specifically, after the switch unit 300 is turned on, a shutdown control signal is sent to the pull-down circuit 40 , and the first MOS tube M1 is turned off by the shutdown control signal, so that the non-volatile memory unit 400 can read and write data normally.

[0067] In some embodiments, after the switch unit is turned on and the pull-down operation of the pull-down circuit is turned off, a read / write operation is performed on the non-volatile memory unit corresponding to the switch unit.

[0068] For example, the switch unit 300 is taken as a gate tube. Figure 5 As shown, Figure 5 The timing diagram of the non-volatile memory of the present invention is shown in FIG. 1 , wherein the Read stage is when the non-volatile memory 1000 performs a read operation, the Write stage is when the non-volatile memory 1000 performs a write operation, the Idle stage is when the non-volatile memory 1000 does not perform an operation, and the Selector setup is when the non-volatile memory 1000 performs a read operation. In this stage, the non-volatile memory 1000 performs a control method for the non-volatile memory. Before the Read operation, the clamp voltage is first pulled down so that the selector can be turned on, and after the selector is turned on, the first MOS tube M1 is turned off, so that data can be read normally.

[0069] A fourth aspect of the present invention provides an electronic device, including a non-volatile memory 1000 .

[0070] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0071] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A data reading circuit for a non-volatile memory, characterized in that: The nonvolatile memory includes at least one nonvolatile storage unit, the nonvolatile storage unit includes at least a switch unit and a nonvolatile storage unit connected in series, and the data reading circuit includes: A gate circuit, a first end of which is connected to the nonvolatile storage unit via a bit line; a clamp circuit, wherein a first end of the clamp circuit is connected to a second end of the gate circuit; an amplifier circuit, wherein a first end of the amplifier circuit is connected to a second end of the clamp circuit, the second end of the amplifier circuit is used to receive a reference signal, and a third end of the amplifier circuit is used to output an amplified identification signal; a pull-down circuit, wherein a first end of the pull-down circuit is connected to a second end of the gate circuit and a first end of the clamp circuit, and a second end of the pull-down circuit is grounded; Wherein, before turning on the switch unit, the pull-down circuit performs a pull-down operation on the clamping voltage of the clamping circuit so that the clamping voltage is pulled down to ground.

2. The data reading circuit for a non-volatile memory according to claim 1, characterized in that: The pull-down circuit comprises: A first MOS transistor, wherein the gate of the first MOS transistor is used to receive a pull-down control signal, the drain of the first MOS transistor is connected to the second end of the gate circuit and the first end of the clamp circuit, and the source of the first MOS transistor is grounded.

3. The data reading circuit for a non-volatile memory according to claim 2, characterized in that: The gate circuit comprises: A second MOS transistor, wherein the gate of the second MOS transistor is used to receive an isolation enable signal, the drain of the second MOS transistor is connected to the non-volatile storage unit through the bit line, and the source of the second MOS transistor is respectively connected to the first end of the clamping circuit and the first end of the pull-down circuit.

4. The data reading circuit for a non-volatile memory according to claim 3, characterized in that: The clamping circuit comprises: An inverter, wherein an input terminal of the inverter is connected to a source of the second MOS tube; a third MOS tube, wherein the gate of the third MOS tube is connected to the output end of the inverter, the drain of the third MOS tube is connected to the input end of the inverter and the source of the second MOS tube, and the source of the third MOS tube is connected to the first end of the amplifier circuit.

5. The data reading circuit for non-volatile memory according to claim 4, characterized in that: The amplifying circuit comprises: a fourth MOS tube, wherein a gate of the fourth MOS tube is used to receive a read enable signal, and a drain of the fourth MOS tube is connected to a source of the third MOS tube; a fifth MOS tube, wherein the gate of the fifth MOS tube is used to receive a bias signal, the drain of the fifth MOS tube is connected to the source of the fourth MOS tube, and the source of the fifth MOS tube is grounded; A comparator, wherein the positive input end of the comparator is connected to the drain of the fourth MOS tube and the source of the third MOS tube, the reverse input end of the comparator is connected to a reference power supply to receive the reference signal, and the output end of the comparator is used to output the amplified identification signal.

6. A non-volatile memory, characterized in that: include: at least one nonvolatile storage unit, the nonvolatile storage unit comprising at least a switch unit and a nonvolatile storage unit connected in series; as well as The data reading circuit for a non-volatile memory according to any one of claims 1 to 5, wherein the data reading circuit is connected to the non-volatile storage unit via a bit line.

7. The nonvolatile memory according to claim 6, wherein: The non-volatile memory unit includes one or more of RRAM, MRAM, FERAM, and PCRAM.

8. The nonvolatile memory according to claim 6 or 7, characterized in that: The switch unit at least includes a gate tube.

9. A method for controlling a non-volatile memory according to any one of claims 6 to 8, characterized in that: The control method comprises: When the switch unit is turned on, a pull-down control signal is sent to the pull-down circuit to perform a pull-down operation on the clamping voltage of the clamping circuit.

10. The control method of the non-volatile memory according to claim 9, characterized in that: The control method further comprises: After determining that the switch unit is turned on, a shutdown control signal is sent to the pull-down circuit to stop the pull-down operation of the pull-down circuit.

11. The control method of the non-volatile memory according to claim 10, characterized in that: The control method further comprises: After the switch unit is turned on and the pull-down operation of the pull-down circuit is stopped, a read / write operation is performed on the non-volatile storage unit corresponding to the switch unit.

12. An electronic device, characterized in that: The non-volatile memory comprises the non-volatile memory as claimed in any one of claims 6 to 8.

Images