Memory device and operating method thereof

Abstract

The present disclosure provides a memory device and an operating method thereof, wherein the peripheral circuit in the memory device is configured to: perform a first write operation on a target memory cell in a memory array, adjust the threshold voltage of the target memory cell to within the range of a first threshold voltage distribution to write a first value into the target memory cell, or adjust the threshold voltage of the target memory cell to within the range of a second threshold voltage distribution to write a second value into the target memory cell; the minimum value of the second threshold voltage distribution is greater than the maximum value of the first threshold voltage distribution; in response to a first write command, apply a first read voltage to a conductive line coupled to the target memory cell to perform a first read operation on the target memory cell and obtain a read value of the target memory cell; the first read voltage is greater than the minimum value of the second threshold voltage distribution; compare the read value and the target value, and determine whether to perform a second write operation on the target memory cell based on the comparison result.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly to a memory device and an operating method thereof. Background Art

[0002] To bridge the performance gap between dynamic random access memory (DRAM) and NAND flash memory, a new storage medium technology, storage class memory (SCM), has been proposed. Mainstream SCM media include phase-change memory (PCM), resistive random access memory (ReRAM), and magnetic random access memory (MRAM). PCM offers significant advantages over flash memory in many aspects, including read and write speed, read and write cycles, data retention time, and cell area. However, PCM still faces numerous challenges in practical applications, leaving significant room for optimization. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a memory device and an operating method thereof.

[0004] To achieve the above objectives, the technical solution of the embodiment of the present disclosure is implemented as follows:

[0005] In a first aspect, an embodiment of the present disclosure provides a memory device, comprising a memory array and a peripheral circuit coupled to the memory array; the peripheral circuit is configured to:

[0006] performing a first write operation on a target memory cell in the memory array, adjusting a threshold voltage of the target memory cell to be within a range of a first threshold voltage distribution so as to write a first value into the target memory cell, or adjusting the threshold voltage of the target memory cell to be within a range of a second threshold voltage distribution so as to write a second value into the target memory cell; wherein a minimum value of the second threshold voltage distribution is greater than a maximum value of the first threshold voltage distribution;

[0007] In response to a first write command, applying a first read voltage to a conductive line coupled to the target memory cell to perform a first read operation on the target memory cell and obtain a read value of the target memory cell; the first read voltage is greater than a minimum value of the second threshold voltage distribution;

[0008] The read value and the target value are compared, and it is determined whether to perform a second write operation on the target memory cell according to the comparison result.

[0009] In an optional implementation manner, the read value and the target value are both the first value; and the peripheral circuit is further configured to:

[0010] A second write operation of writing the first value is performed on the target memory cell.

[0011] In an optional implementation manner, the read value and the target value are both the second value; and the peripheral circuit is further configured to:

[0012] The second write operation is not performed on the target memory cell.

[0013] In an optional implementation, the read value is the first value, and the target value is the second value; and the peripheral circuit is further configured to:

[0014] A second write operation of writing the second value is performed on the target memory cell.

[0015] In an optional implementation manner, the read value is the second value, and the target value is the first value; and the peripheral circuit is further configured to:

[0016] A second write operation of writing the first value is performed on the target memory cell.

[0017] In an optional implementation, the peripheral circuit is further configured as follows:

[0018] In response to a second write command, a second read voltage is applied to the conductive line coupled to the target memory cell to perform a second read operation on the target memory cell.

[0019] In an optional embodiment, a time interval between the first read operation and the first write operation is smaller than a time interval between the second read operation and the second write operation; and the second read voltage is greater than the first read voltage.

[0020] In an optional implementation, the time interval between the first read operation and the first write operation is equal to the time interval between the second read operation and the second write operation; and the second read voltage is equal to the first read voltage.

[0021] In an optional embodiment, the time interval between the first read operation and the first write operation is greater than the time interval between the second read operation and the second write operation; the second read voltage is less than the first read voltage, and the second read voltage is greater than the minimum value of the second threshold voltage distribution.

[0022] In a second aspect, an embodiment of the present disclosure provides a method for operating a memory device, including:

[0023] Performing a first write operation on a target memory cell in a memory array to adjust a threshold voltage of the target memory cell to be within a range of a first threshold voltage distribution so as to write a first value into the target memory cell, or adjusting the threshold voltage of the target memory cell to be within a range of a second threshold voltage distribution so as to write a second value into the target memory cell; a minimum value of the second threshold voltage distribution is greater than a maximum value of the first threshold voltage distribution;

[0024] In response to a first write command, applying a first read voltage to a conductive line coupled to the target memory cell to perform a first read operation on the target memory cell and obtain a read value of the target memory cell; the first read voltage is greater than a minimum value of the second threshold voltage distribution;

[0025] The read value and the target value are compared, and it is determined whether to perform a second write operation on the target memory cell according to the comparison result.

[0026] In the technical solution provided in the present disclosure, the peripheral circuit can be configured to apply a first read voltage to the conductive line coupled to the target memory cell in response to a first write command to perform a first read operation on the target memory cell, the first read voltage being greater than the minimum value of the second threshold voltage distribution, and determining whether to perform a second write operation on the target memory cell by comparing the read value with the target value, and when the read value and the target value are both the first value, the second write operation of writing the first value is still performed on the target memory cell, and when the read value and the target value are both the second value, the second write operation is not performed on the target memory cell. In this way, repeated writing to the memory cell can be avoided to a certain extent, while reducing the possibility of read errors and then write errors caused by threshold voltage drift of the memory cell, thereby improving the reliability of the memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A schematic diagram of a memory device provided in an embodiment of the present disclosure;

[0028] Figure 2 A schematic diagram of a three-dimensional structure of part of the storage array provided in an embodiment of the present disclosure;

[0029] Figure 3 Schematic diagram of threshold voltage distribution provided by the embodiment of the present disclosure Figure 1 ;

[0030] Figure 4 Schematic diagram of threshold voltage distribution provided by the embodiment of the present disclosure Figure 2 ;

[0031] Figure 5 A block diagram of a read-before-write operation provided in an embodiment of the present disclosure;

[0032] Figure 6 Schematic diagram of threshold voltage distribution provided by the embodiment of the present disclosure Figure 3 ;

[0033] Figure 7 A flowchart of an operating method of a memory device provided in an embodiment of the present disclosure is provided. DETAILED DESCRIPTION

[0034] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0035] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0036] In the drawings, like reference numerals refer to like elements throughout.

[0037] It should be understood that spatial relationship terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" can include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial description terms used herein are interpreted accordingly.

[0038] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0039] Figure 1 Schematic diagram of the composition of the memory device provided by the present disclosure Figure 1 , Figure 2 This is a schematic diagram of a three-dimensional structure of a portion of the structure of the memory device provided in an embodiment of the present disclosure. Figure 1 and Figure 2 The memory device includes a memory array 10 and a peripheral circuit 20 coupled to the memory array 10. The memory array 10 includes a plurality of memory cells 100. The memory cells 100 are located between a first conductive line 121 and a second conductive line 120 in a first direction. The memory cells 100 arranged along the second direction are coupled to one first conductive line 121, and the memory cells 100 arranged along the third direction are coupled to one second conductive line 120. Here, the first direction is the Z direction, the second direction is the X direction, and the third direction is the Y direction.

[0040] It should be noted that the number of first conductive lines, the number of second conductive lines, and the number of storage units shown in the figure are only examples, and the present disclosure does not impose any specific restrictions on them. Figure 1 and Figure 2 Taking the example of the memory array 10 including only one layer of memory cells 100, the present disclosure is not limited thereto. In other embodiments, the memory array 10 may include multiple memory layers stacked and arranged along the Z direction, and each memory layer includes multiple first conductive lines, multiple second conductive lines, and multiple memory cells located between the first conductive lines and the second conductive lines in the Z direction.

[0041] In some embodiments, reference Figure 2The memory cell 100 includes a gating element 102 and a phase change element 104 stacked and arranged along a first direction. The gating element 102 is located between the first conductive line 121 and the phase change element 104. In addition, the memory cell 100 also includes a first electrode 101, a second electrode 103, and a third electrode 105. The first electrode 101 is located between the gating element 102 and the first conductive line 121, the second electrode 103 is located between the gating element 102 and the phase change element 104, and the third electrode 105 is located between the phase change element 104 and the second conductive line 120. Here, the first conductive line 121 can be a word line (WL), and the second conductive line 120 can be a bit line (BL).

[0042] In some specific examples, the first electrode 101, the second electrode 103, and the third electrode 105 may include a conductive material and may serve as a conductive path. Here, the conductive material may be at least one of a doped semiconductor material (e.g., doped silicon, doped germanium, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), a metal material (e.g., tungsten, titanium, tantalum, aluminum, copper, etc.), and a metal semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0043] In some specific examples, the second electrode 103 may further include a thermal insulation material, thereby reducing thermal crosstalk between the gating element 102 and the phase change element 104. For example, the second electrode 103 may include amorphous carbon.

[0044] In some specific examples, the resistance of the gating element 102 can change in response to a change in the selection voltage applied between the first electrode 101 and the second electrode 103. In some embodiments, the gating element 102 may include a material having an Ovonic Threshold Switch (OTS) property, and the material having the OTS property may include at least one element selected from oxygen, sulfur, selenium, tellurium, germanium, antimony, silicon, and arsenic, such as Zn. x Te y 、Ge x Te y 、Nb x O y 、Si x As y Te z When the voltage applied between the first electrode 101 and the second electrode 103 is lower than its threshold voltage, the gating element 102 can be in a high resistance state that prevents current from flowing, and when the voltage applied between the first electrode 101 and the second electrode 103 is higher than its threshold voltage, the gating element 102 can be in a low resistance state that allows current to flow.

[0045] In a specific example, the phase change element 104 may include a chalcogenide component, such as at least one of binary compounds such as GaSb, InSb, InSe, SbTe and GeTe, ternary compounds such as GeSbTe, GaSeTe, InSbTe, SnSbTe and InSbGe, and quaternary compounds such as AgInSbTe, (GeSn)SbTe, GeSb(SeTe) and TeGeSbS.

[0046] In some embodiments, the phase change element 104 can be reversibly switched between a crystalline state and an amorphous state, and data can be stored by utilizing the resistivity difference between the crystalline and amorphous states. The crystalline phase of the phase change element 104 can be changed through a set (SET) operation and a reset (RESET) operation. Specifically, the set operation may include heating the phase change element 104 to above the recrystallization temperature by Joule heat generated by the voltage applied between the first conductive line 121 and the second conductive line 120, and then slowly decreasing the voltage applied between the first conductive line 121 and the second conductive line 120, thereby slowly cooling the phase change element 104 and transforming it into a low-resistance crystalline state. The reset operation may include heating the phase change element 104 to above the melting point by Joule heat generated by the voltage applied between the first conductive line 121 and the second conductive line 120, and then rapidly decreasing the voltage applied between the first conductive line 121 and the second conductive line 120, thereby rapidly cooling the phase change element 104 and transforming it into a high-resistance amorphous state. When the memory cell 100 is in the set state after a set operation, the data stored in the memory cell 100 may be one of "0" and "1". When the memory cell 100 is in the reset state after a reset operation, the data stored in the memory cell 100 may be the other of "0" and "1". In the embodiment of the present disclosure, the memory cell 100 in the set state stores "1" data, and the memory cell 100 in the reset state stores "0" data as an example.

[0047] In some embodiments, after data is written to the memory array through the aforementioned reset and set operations, when new data needs to be written, a read-before-write operation can be performed to avoid repeated write operations on the memory cells. This can extend the lifespan of the memory cells and save power. Specifically, when the data to be written is the same as the data to be read, the write operation to the memory cell can be omitted. When the data to be written is different from the data to be read, a write operation to the memory cell is performed.

[0048] In some embodiments, as Figure 3As shown, when a write operation is completed, the threshold voltage of the memory cell storing "1" after the set operation can be within the range of the first threshold voltage distribution 201, and the threshold voltage of the memory cell storing "0" after the reset operation can be within the range of the second threshold voltage distribution 301. The voltage applied to the conductive line coupled to the memory cell in the read operation can be a read voltage V0, which is greater than the maximum value of the first threshold voltage distribution 201 and less than the minimum value of the second threshold voltage distribution 301. However, over time, the structural relaxation of the amorphous phase change material will cause the threshold voltage of the memory cell in the reset state to drift toward the positive direction, and the conductive filaments of the amorphous OTS material will gradually degenerate, causing the threshold voltage of the memory cell in the set state to drift toward the positive direction. The longer the time interval between two adjacent write operations, the more serious the drift of the threshold voltage of the memory cell. For example, the threshold voltage distribution of the memory cell in the set state may drift from the first threshold voltage distribution 201 to the third threshold voltage distribution 202, and may also drift from the third threshold voltage distribution 202 to the fourth threshold voltage distribution 203 over time; the threshold voltage distribution of the memory cell in the reset state may drift from the second threshold voltage distribution 301 to the fifth threshold voltage distribution 302, and may also drift from the fifth threshold voltage distribution 302 to the sixth threshold voltage distribution 303 over time. In this case, if a read operation is still performed on the memory cell by applying a read voltage V0 to the conductive line coupled to the memory cell, and then determining whether a write operation needs to be performed on the memory cell based on a comparison result between the data to be written and the read data, an error in the read result may occur, which in turn may cause an error in the write operation, thereby potentially reducing the reliability of the memory device.

[0049] In view of the above problems, the present disclosure proposes the following embodiments.

[0050] The present disclosure provides a memory device, in combination with reference to Figure 1 and Figure 3 The memory device includes a memory array 10 and a peripheral circuit 20 coupled to the memory array 10. The peripheral circuit 20 is configured to: perform a first write operation on a target memory cell in the memory array 10, adjust the threshold voltage of the target memory cell to within a range of a first threshold voltage distribution 201 to write a first value to the target memory cell, or adjust the threshold voltage of the target memory cell to within a range of a second threshold voltage distribution 301 to write a second value to the target memory cell; the minimum value of the second threshold voltage distribution 301 is greater than the maximum value of the first threshold voltage distribution 201. Here, the first value can be "1" and the second value can be "0".

[0051] It should be noted that, in the embodiment of the present disclosure, the target storage unit may be at least one storage unit 100 in the storage array 10. For ease of explanation, the present disclosure takes the operation performed on one target storage unit as an example. It can be understood that the operation performed on the target storage unit may be an operation performed simultaneously on multiple storage units in the storage array 10.

[0052] In some embodiments, the peripheral circuit 20 is configured to: in response to a first write command, apply a first read voltage to the conductive line coupled to the target memory cell to perform a first read operation on the target memory cell and obtain a read value of the target memory cell; the first read voltage is greater than the minimum value of the second threshold voltage distribution 301; compare the read value with the target value, and determine whether to perform a second write operation on the target memory cell based on the comparison result. Here, the conductive line coupled to the target memory cell can be Figure 1 The first conductive line 121 in.

[0053] In some specific examples, refer to Figure 4 , the first read voltage V1 is greater than the minimum value of the second threshold voltage distribution 301, and the first read voltage V1 is greater than voltage V0. Here, voltage V0 can be considered a default read voltage, which is greater than the maximum value of the first threshold voltage distribution 201 and less than the minimum value of the second threshold voltage distribution 301. By using a relatively large first read voltage V1 to perform the first read operation on the target memory cell, read errors and write errors caused by the threshold voltage of the target memory cell drifting toward the positive direction can be avoided to a certain extent, thereby improving the reliability of the write operation.

[0054] It should be noted that since a verification operation is performed when a write operation is performed on a memory cell, the range of the first threshold voltage distribution 201 and the range of the second threshold voltage distribution 301 are both known. However, since there may be a long time interval between the first write operation and the first read operation, when the first read operation is performed, the threshold voltage of the memory cell storing the first value may no longer be within the range of the first threshold voltage distribution 201, and the threshold voltage of the memory cell storing the second value may no longer be within the range of the second threshold voltage distribution 301. The process of determining the threshold voltage distribution in which the threshold voltage of the memory cell after the threshold voltage drift occurs is relatively cumbersome, which will result in reduced efficiency of the write operation. Therefore, when the first read operation is performed, the specific range of the threshold voltage distribution in which the threshold voltage of the memory cell is located is unknown. That is, in the embodiment of the present disclosure, the range of the first threshold voltage distribution 201 and the range of the second threshold voltage distribution 301 are both fixed ranges and will not change over time. The first threshold voltage distribution 201 only represents the range of the threshold voltage of the memory cell when the write operation of writing the first value to the memory cell is completed, and cannot represent the range of the threshold voltage of all memory cells storing the first value. The second threshold voltage distribution 301 only represents the range of the threshold voltage of the memory cell when the write operation of writing the second value to the memory cell is completed, and cannot represent the range of the threshold voltage of all memory cells storing the second value.

[0055] In some embodiments, when the read value and the target value are both first values, the peripheral circuit 20 is further configured to: perform a second write operation on the target memory cell, writing the first value. Here, the second write operation on the target memory cell may be a set operation. After the second write operation on the target memory cell, the threshold voltage of the target memory cell is within the range of the first threshold voltage distribution 201.

[0056] In the disclosed embodiment, when the read value and target value of a target memory cell are both the first value, a second write operation to write the first value to the target memory cell is still performed to further improve the reliability of the write operation. This is because the time interval between the first write operation and the second write operation is not fixed, which may result in a situation where the threshold voltage of the target memory cell drifts slightly in the positive direction, while the first read voltage V1 is too large. This may cause the threshold voltage of the target memory cell in the reset state to be still less than the first read voltage V1. When the first read operation is performed on it using the first read voltage V1, its read value is the first value, which may cause a read error. If the target value of the second write operation is also the first value at this time, then according to the original read-first-then-write method, the write operation to write the first value to the target memory cell will be omitted, which will cause a write error.

[0057] In some embodiments, when the read value and the target value are both the second value, the peripheral circuit 20 is further configured to not perform the second write operation on the target memory cell, thereby avoiding repeated writing to the target memory cell.

[0058] In some embodiments, when the read value is a first value and the target value is a second value, the peripheral circuit 20 is further configured to: perform a second write operation on the target memory cell to write the second value. Here, the second write operation to write the second value can be a reset operation. After the second write operation to write the second value to the target memory cell is performed, the threshold voltage of the target memory cell is within the range of the second threshold voltage distribution 301.

[0059] In some embodiments, when the read value is the second value and the target value is the first value, the peripheral circuit 20 is further configured to: perform a second write operation on the target memory cell to write the first value.

[0060] In some specific examples, refer to Figure 5 , the peripheral circuit 20 can be configured to implement the read-before-write operation as shown in the figure. Specifically, the peripheral circuit 20 can be configured to: start performing the read-before-write operation on the target memory cell in response to the write command, first, perform a read operation on the target memory cell, then determine whether the target value carried by the write command is 1, and if the target value is 1, determine whether the read value is 1, if not, that is, the read value is 0, then perform a set operation on the target memory cell; if yes, that is, the read value is 1, then perform a set operation on the target memory cell; if the target value is 0, determine whether the read value is 0, if not, that is, the read value is 1, then perform a reset operation on the target memory cell; if yes, that is, the read value is 0, then omit the write operation.

[0061] In an embodiment of the present disclosure, the peripheral circuit can be configured to apply a first read voltage to a conductive line coupled to a target memory cell in response to a first write command to perform a first read operation on the target memory cell, wherein the first read voltage is greater than the minimum value of the second threshold voltage distribution, and whether to perform a second write operation on the target memory cell is determined by comparing the read value with the target value, and when the read value and the target value are both the first value, the second write operation of writing the first value is still performed on the target memory cell, and when the read value and the target value are both the second value, the second write operation is not performed on the target memory cell. In this way, repeated writing to the memory cell can be avoided to a certain extent, while reducing the possibility of read errors and write errors caused by threshold voltage drift of the memory cell, thereby improving the reliability of the memory device.

[0062] In some embodiments, the peripheral circuit 20 is further configured to: in response to a second write command, apply a second read voltage to the conductive line coupled to the target memory cell to perform a second read operation on the target memory cell. Here, the second write command may be a write command subsequent to the first write command.

[0063] In some embodiments, since the longer the time interval between two write operations, the more serious the drift of the threshold voltage of the memory cell may be, the size of the second read voltage can be determined based on the size relationship between the time interval between the first read operation and the first write operation and the time interval between the second read operation and the second write operation to further improve the reliability of the write operation.

[0064] In some specific examples, refer to Figure 6 , the time interval between the first read operation and the first write operation is shorter than the time interval between the second read operation and the second write operation, and the second read voltage V2a is greater than the first read voltage V1.

[0065] In some specific examples, refer to Figure 6 , the time interval between the first read operation and the first write operation is equal to the time interval between the second read operation and the second write operation, and the second read voltage is equal to the first read voltage V1.

[0066] In some specific examples, refer to Figure 6 , the time interval between the first read operation and the first write operation is greater than the time interval between the second read operation and the second write operation, the second read voltage V2b is less than the first read voltage V1, and the second read voltage V2b is greater than the minimum value of the second threshold voltage distribution 301.

[0067] In some embodiments, similar to the aforementioned embodiments, after performing a second read operation on the target memory cell, the peripheral circuit is further configured to compare the read value of the second read operation with the target value carried by the second write command, and determine whether to perform a third write operation on the target memory cell based on the comparison result; and when the read value and the target value are both the first value, the third write operation of writing the first value is still performed on the target memory cell; and when the read value and the target value are both the second value, the write operation on the target memory cell is omitted.

[0068] In the embodiment of the present disclosure, the longer the interval between the read operation in the current read-first-then-write operation and the previous write operation, the larger the read voltage used in the read operation in the current read-first-then-write operation can be. This is because the longer the interval, the more serious the drift of the threshold voltage of the storage unit may be. By determining the magnitude of the read voltage based on the time interval, the read voltage can always be a larger value. Combined with the fact that when the read value and the target value are both the first value, the write operation of writing the first value to the storage unit is still performed, and when the read value and the target value are both the second value, the write operation to the storage unit is omitted. This can improve the durability of the storage unit and avoid write operation errors caused by read operation errors, thereby improving the reliability of the memory device.

[0069] It should be noted that the above embodiments take the memory device as a phase change memory as an example. Selector Only Memory (SOM) and Resistive Random Access Memory (ReRAM) also have similar problems as phase change memory. The memory device provided in the present disclosure can also be a selector only memory or a resistive random access memory.

[0070] Based on a concept similar to the above-mentioned memory device, the present disclosure also provides an operating method of the memory device. Figure 7 A flowchart of the operating method of the memory device provided by the present disclosure is shown in FIG. Figure 7 As shown, the operating method of the memory device includes the following steps:

[0071] Step S10: performing a first write operation on a target memory cell in a memory array, adjusting the threshold voltage of the target memory cell to be within a range of a first threshold voltage distribution to write a first value into the target memory cell, or adjusting the threshold voltage of the target memory cell to be within a range of a second threshold voltage distribution to write a second value into the target memory cell; a minimum value of the second threshold voltage distribution is greater than a maximum value of the first threshold voltage distribution;

[0072] Step S20: in response to a first write command, applying a first read voltage to a conductive line coupled to the target memory cell to perform a first read operation on the target memory cell and obtain a read value of the target memory cell; the first read voltage is greater than a minimum value of the second threshold voltage distribution;

[0073] Step S30: comparing the read value and the target value, and determining whether to perform a second write operation on the target memory cell according to the comparison result.

[0074] In some embodiments, the read value and the target value are both the first value; and the operating method of the memory device further includes: performing a second write operation on the target memory cell to write the first value.

[0075] In some embodiments, the read value and the target value are both the second value; and the operating method of the memory device further includes: not performing the second write operation on the target storage unit.

[0076] In some embodiments, the read value is the first value, and the target value is the second value; the operating method of the memory device further includes: performing a second write operation on the target storage unit to write the second value.

[0077] In some embodiments, the read value is the second value, and the target value is the first value; the operating method of the memory device further includes: performing a second write operation on the target storage unit to write the first value.

[0078] In some embodiments, the operating method of the memory device further includes: applying a second read voltage to a conductive line coupled to the target memory cell in response to a second write command to perform a second read operation on the target memory cell.

[0079] In some embodiments, a time interval between the first read operation and the first write operation is smaller than a time interval between the second read operation and the second write operation; and the second read voltage is greater than the first read voltage.

[0080] In some embodiments, a time interval between the first read operation and the first write operation is equal to a time interval between the second read operation and the second write operation; and the second read voltage is equal to the first read voltage.

[0081] In some embodiments, the time interval between the first read operation and the first write operation is greater than the time interval between the second read operation and the second write operation; the second read voltage is less than the first read voltage, and the second read voltage is greater than the minimum value of the second threshold voltage distribution.

[0082] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0083] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0084] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present disclosure, and they should all be covered by the protection scope of the present disclosure.

Claims

1. A memory device, characterized in that: The invention comprises a memory array and a peripheral circuit coupled to the memory array; the peripheral circuit is configured to: performing a first write operation on a target memory cell in the memory array, adjusting a threshold voltage of the target memory cell to be within a range of a first threshold voltage distribution so as to write a first value into the target memory cell, or adjusting the threshold voltage of the target memory cell to be within a range of a second threshold voltage distribution so as to write a second value into the target memory cell; wherein a minimum value of the second threshold voltage distribution is greater than a maximum value of the first threshold voltage distribution; In response to a first write command, applying a first read voltage to a conductive line coupled to the target memory cell to perform a first read operation on the target memory cell and obtain a read value of the target memory cell; The first read voltage is greater than a minimum value of the second threshold voltage distribution; comparing the read value and the target value, and determining whether to perform a second write operation on the target storage unit according to the comparison result; If the read value and the target value are different or both the read value and the target value are the first value, the second write operation is performed on the target storage unit; otherwise, the second write operation is not performed on the target storage unit.

2. The memory device according to claim 1, wherein The read value and the target value are both the first value; and the peripheral circuit is further configured as follows: A second write operation of writing the first value is performed on the target memory cell.

3. The memory device according to claim 1, wherein The read value and the target value are both the second value; and the peripheral circuit is further configured as follows: The second write operation is not performed on the target memory cell.

4. The memory device according to claim 1, wherein: The read value is the first value, and the target value is the second value; the peripheral circuit is further configured to: A second write operation of writing the second value is performed on the target memory cell.

5. The memory device according to claim 1, wherein The read value is the second value, and the target value is the first value; and the peripheral circuit is further configured to: A second write operation of writing the first value is performed on the target memory cell. The memory device according to claim 1 , wherein: The peripheral circuit is further configured to: In response to a second write command, a second read voltage is applied to the conductive line coupled to the target memory cell to perform a second read operation on the target memory cell.

7. The memory device according to claim 6, wherein: A time interval between the first read operation and the first write operation is shorter than a time interval between the second read operation and the second write operation; and the second read voltage is greater than the first read voltage.

8. The memory device according to claim 6, wherein: A time interval between the first read operation and the first write operation is equal to a time interval between the second read operation and the second write operation; and the second read voltage is equal to the first read voltage.

9. The memory device according to claim 6, wherein: The time interval between the first read operation and the first write operation is greater than the time interval between the second read operation and the second write operation; the second read voltage is less than the first read voltage, and the second read voltage is greater than the minimum value of the second threshold voltage distribution.

10. A method for operating a memory device, characterized in that: include: Performing a first write operation on a target memory cell in a memory array to adjust a threshold voltage of the target memory cell to be within a range of a first threshold voltage distribution so as to write a first value into the target memory cell, or adjusting the threshold voltage of the target memory cell to be within a range of a second threshold voltage distribution so as to write a second value into the target memory cell; a minimum value of the second threshold voltage distribution is greater than a maximum value of the first threshold voltage distribution; In response to a first write command, applying a first read voltage to a conductive line coupled to the target memory cell to perform a first read operation on the target memory cell and obtain a read value of the target memory cell; The first read voltage is greater than a minimum value of the second threshold voltage distribution; comparing the read value and the target value, and determining whether to perform a second write operation on the target storage unit according to the comparison result; If the read value and the target value are different or both the read value and the target value are the first value, the second write operation is performed on the target storage unit; otherwise, the second write operation is not performed on the target storage unit.

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