Chip packaging structure and packaging method thereof

Abstract

The invention discloses a chip packaging structure and a packaging method thereof, and the method comprises the steps: providing a packaging substrate, and enabling the front surface of the packaging substrate to comprise a plurality of first regions which are arranged in an array manner, and first isolation regions located between the adjacent first regions, the back surface of the packaging substrate comprises a plurality of second areas arranged in an array and second isolation areas located between the adjacent second areas; packaging the chip on the first area on the front surface of the packaging substrate, and carrying out primary plastic packaging on the packaging substrate and the chip; cutting the packaging substrate and the first plastic packaging body along the first isolation region or the second isolation region to obtain a plurality of packaging bodies; arranging a plurality of packaging bodies on the carrier plate in an array; performing secondary plastic packaging on the carrier plate and the packaging body, and stripping the carrier plate after the secondary plastic packaging is completed; and cutting the second plastic package body along the interval region between the adjacent package bodies to obtain a plurality of chip package structures. Primary plastic packaging is performed on the chip with the minimum packaging size before secondary plastic packaging, so that the utilization rate of the packaging substrate is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor packaging, and in particular relates to a chip packaging structure and a packaging method thereof. Background Art

[0002] The packaging substrate is one of the most commonly used parts in the field of semiconductor packaging technology, and is consumed in huge quantities during the chip packaging process.

[0003] In the prior art, the chips are arranged on the packaging substrate according to the size array of the packaging structure required in the circuit design, and only one plastic encapsulation is performed. After the plastic encapsulation, the final chip packaging structure is directly obtained by cutting. Since the size of the chip encapsulated inside the substrate is very different from the size of the final packaging structure, the effective utilization rate of the packaging substrate is low and the packaging cost remains high.

[0004] Therefore, in view of the above technical problems, it is necessary to provide a chip packaging structure and a packaging method thereof. Summary of the invention

[0005] The object of the present invention is to provide a chip packaging structure and a packaging method thereof, which can improve the utilization rate and production efficiency of the packaging substrate.

[0006] In order to achieve the above purpose, the technical solution provided by an embodiment of the present invention is as follows:

[0007] A chip packaging method, the packaging method comprising:

[0008] A packaging substrate is provided, wherein the front side of the packaging substrate comprises a plurality of first areas arranged in an array and a first isolation area located between adjacent first areas, the back side of the packaging substrate comprises a plurality of second areas arranged in an array and a second isolation area located between adjacent second areas, the first areas and the second areas are arranged opposite to each other, the first isolation area and the second isolation area are arranged opposite to each other, and a plurality of pads are arranged on the second areas;

[0009] The chip is packaged on the first area on the front side of the packaging substrate, the chip is electrically connected to the pad through the circuit layer on the packaging substrate, and the packaging substrate and the chip are plastic-sealed once to obtain a first packaging structure including a first plastic-sealed body;

[0010] Cutting the packaging substrate and the first plastic packaging body in the first packaging structure along the first isolation region or the second isolation region to obtain a plurality of packaging bodies;

[0011] Arranging a plurality of package arrays on a carrier board, with adjacent packages spaced apart;

[0012] Performing secondary plastic sealing on the carrier board and the packaging body, and peeling off the carrier board after the secondary plastic sealing is completed to obtain a second packaging structure including the first plastic sealing body and the second plastic sealing body;

[0013] The second plastic package body in the second package structure is cut along the spacing area between adjacent package bodies to obtain a plurality of chip package structures.

[0014] In one embodiment, the ratio of the total area of ​​the first region to the total area of ​​the front surface of the package substrate is greater than the ratio of the total area of ​​the projection of the package body on the carrier to the total area of ​​the carrier.

[0015] In one embodiment, the distance between adjacent packages on the carrier along the first direction is greater than the width of the first isolation region along the first direction; and / or,

[0016] The distance between adjacent packages on the carrier along the second direction is greater than the width of the first isolation region along the second direction.

[0017] In one embodiment, the ratio of the area of ​​the first region to the projection area of ​​the chip on the first region is (1.2-2.5):1.

[0018] In one embodiment, the chip is packaged on the first area on the front side of the packaging substrate by wire bonding.

[0019] In one embodiment, a release film is disposed on the carrier, the plurality of packages are arrayed on the release film, and the pads are in contact with the release film.

[0020] Another embodiment of the present invention provides a technical solution as follows:

[0021] A chip packaging structure, the packaging structure comprising:

[0022] A substrate, wherein a plurality of pads are provided on the back side of the substrate;

[0023] A chip is packaged on the front side of the substrate, and the chip is electrically connected to the pad through the circuit layer on the substrate;

[0024] The plastic package body comprises a first plastic package body formed on the substrate and the front side of the chip and a second plastic package body formed on the outer side of the substrate.

[0025] In one embodiment, the bottom of the second plastic packaging body is flush with the back surface of the substrate, and the top of the second plastic packaging body is flush with the top of the first plastic packaging body.

[0026] In one embodiment, part of the second plastic packaging body covers the first plastic packaging body.

[0027] In one embodiment, the outer circumference of the second plastic packaging body is circular, square or rectangular, and the outer circumference of the first plastic packaging body is square or rectangular.

[0028] Compared with the prior art, the present invention has the following beneficial effects:

[0029] The present invention first performs a plastic encapsulation according to the size of the chip with the minimum packaging size, and after cutting, the chip packaging structure with a size that meets the design requirements is obtained by rearrangement and secondary plastic encapsulation, which greatly improves the utilization rate of the packaging substrate, reduces costs and improves production efficiency. At the same time, the size of the chip packaging structure can be easily adjusted without repeatedly customizing the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0031] Figure 1 This is a schematic diagram of the chip packaging structure in Comparative Example 1 of the present invention;

[0032] Figure 2a-2b This is a process flow chart of the chip packaging method in Comparative Example 1 of the present invention;

[0033] Figure 3 for Figure 2a The local schematic diagram of the A in the middle;

[0034] Figure 4 is a schematic diagram of a chip packaging structure in Embodiment 1 of the present invention;

[0035] Figures 5a to 5e is a process flow chart of the chip packaging method in Example 1 of the present invention;

[0036] Figure 6 for Figure 5a The local schematic diagram of point B in the middle;

[0037] Figure 7 Schematic diagram of the chip packaging structure in Example 2 of the present invention.

[0038] Description of main reference numerals:

[0039] 10 - packaging substrate, 101 - substrate, 11 - pad, 12 - positioning unit, 20 - chip, 30 - plastic package, 31 - first plastic package, 32 - second plastic package, 40 - bonding wire, 50 - carrier. DETAILED DESCRIPTION

[0040] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0041] The present invention discloses a chip packaging method, comprising:

[0042] A packaging substrate is provided, wherein the front side of the packaging substrate comprises a plurality of first regions arranged in an array and a first isolation region located between adjacent first regions, the back side of the packaging substrate comprises a plurality of second regions arranged in an array and a second isolation region located between adjacent second regions, the first region and the second region are arranged opposite to each other, the first isolation region and the second isolation region are arranged opposite to each other, and a plurality of pads are arranged on the second region;

[0043] The chip is packaged on the first area on the front side of the packaging substrate, the chip is electrically connected to the pad through the circuit layer on the packaging substrate, and the packaging substrate and the chip are plastic-sealed once to obtain a first packaging structure including a first plastic-sealed body;

[0044] Cutting the packaging substrate and the first plastic packaging body in the first packaging structure along the first isolation region or the second isolation region to obtain a plurality of packaging bodies;

[0045] Arranging a plurality of package arrays on a carrier board, with adjacent packages spaced apart;

[0046] Performing secondary plastic sealing on the carrier board and the packaging body, and peeling off the carrier board after the secondary plastic sealing is completed to obtain a second packaging structure including the first plastic sealing body and the second plastic sealing body;

[0047] The second plastic package body in the second package structure is cut along the spacing area between adjacent package bodies to obtain a plurality of chip package structures.

[0048] The present invention also discloses a chip packaging structure, comprising:

[0049] A substrate, wherein a plurality of pads are provided on the back side of the substrate;

[0050] The chip is packaged on the front side of the substrate, and the chip is electrically connected to the pad through the circuit layer on the substrate;

[0051] The plastic package body comprises a first plastic package body formed on the substrate and the front side of the chip and a second plastic package body formed on the outer side of the substrate.

[0052] Specifically, the key dimensional parameters involved in the chip packaging process are the size of the chip, the size of the packaging substrate, and the size of the chip packaging structure. Since the chip needs to be electrically connected to the printed circuit board (PCB) board or the integrated circuit (SMT) board after packaging, the size of the chip and the size of the chip packaging structure have been determined during the circuit design process. By rationally designing the chip packaging method, not only can the utilization rate of the packaging substrate be improved, but also the production efficiency can be improved.

[0053] The present invention is further described below with reference to specific examples.

[0054] Comparative Example 1:

[0055] Ginseng Figure 1 As shown, the chip packaging structure in this comparative example includes:

[0056] A substrate 101, a plurality of pads 11 are provided on the back of the substrate 101;

[0057] The chip 20 is packaged on the front side of the substrate 101, and the chip 20 is electrically connected to the pad 11 through a circuit layer (not shown) on the substrate 101;

[0058] The plastic package 30 is formed on the front side of the substrate 101 and the chip 20 .

[0059] In this comparative example, the chip 20 is packaged on the front surface of the substrate 101 by wire bonding, and the plastic package 30 encapsulates the front surface of the substrate 101 , the front surface of the chip 20 and the bonding wires 40 .

[0060] In this comparative example, the size of the chip 20 is 4 mm*5 mm. According to the design requirements of the circuit, the size of the chip packaging structure is 12 mm*12 mm.

[0061] The chip packaging method in this comparative example is:

[0062] 1. Ginseng Figure 2a Combined with Figure 2b As shown, a packaging substrate 10 is provided, the front side of the packaging substrate 10 includes a plurality of first areas S11 arranged in an array and a first isolation area S12 located between adjacent first areas S11, the back side of the packaging substrate 10 includes a plurality of second areas S21 arranged in an array and a second isolation area S22 located between adjacent second areas S21, the first area S11 and the second area S21 are arranged opposite to each other, the first isolation area S12 and the second isolation area S22 are arranged opposite to each other, and a plurality of pads 11 are provided on the second area S21.

[0063] In this comparative example, the size of the packaging substrate 10 is 240mm*74mm, and the first area S11 and the second area S21 are arranged in an array at a certain spacing on the front and back of the packaging substrate 10 according to the design requirements of the circuit. The size of the first area S11 and the second area S21 matches the size of the chip packaging structure.

[0064] 2. Ginseng Figure 2b As shown, the chip 20 is packaged on the first area S11 on the front side of the packaging substrate 10 . A total of 100 chips 20 are packaged on the packaging substrate 10 , and the size of the chip 20 is 4 mm*5 mm.

[0065] 3. The packaging substrate 10 and the chip 20 are plastic-sealed, and a plastic-sealing body 30 is formed on the front of the packaging substrate 10 and the chip 20 to obtain a packaging structure including the plastic-sealing body 30 .

[0066] 4. After the plastic packaging is completed, the packaging substrate 10 and the plastic packaging body 30 are cut along the second isolation area S22 to obtain multiple chip packaging structures. Finally, the size of the single chip packaging structure is 12mm*12mm.

[0067] Ginseng Figure 3 As shown, a plurality of pads 11 and positioning units 12 are provided on the second area S21 on the back of the package substrate 10. The positioning unit 12 is used to determine the direction of the chip. The arrangement and number of the pads 11 are adjusted according to design requirements.

[0068] The chip packaging method in this comparative example also includes conventional process steps such as preparing the chip on the wafer before packaging the chip 20 on the packaging substrate 10, thinning and cutting the wafer after wafer film bonding, and performing wafer bonding; after plastic sealing, it also includes conventional process steps such as surface polishing of the plastic sealing body and inspection of the chip packaging structure.

[0069] In the chip packaging method in this comparative example, the ratio of the area of ​​the first area S11 on the front side of the packaging substrate 10 to the projection area of ​​the chip 20 on the first area S11 is approximately 7.2:1. The size of the chip 20 is greatly different from that of the first area S11. Only 100 chips can be packaged on the packaging substrate 10. The effective utilization rate of the packaging substrate 10 is low, the packaging cost is high, and the production efficiency is low.

[0070] Embodiment 1:

[0071] Ginseng Figure 4 As shown, the chip packaging structure in this embodiment includes:

[0072] A substrate 101, a plurality of pads 11 are provided on the back of the substrate 101;

[0073] The chip 20 is packaged on the front side of the substrate 101, and the chip 20 is electrically connected to the pad 11 through the circuit layer on the substrate 101;

[0074] The plastic package 30 includes a first plastic package 31 formed on the front of the substrate 101 and the chip 20 and a second plastic package 32 formed on the outside of the substrate 101 .

[0075] Exemplarily, the chip 20 in this embodiment is an LGA fingerprint chip.

[0076] The chip 20 in this embodiment is packaged on the substrate 101 by wire bonding, and the chip 20 is electrically connected to the circuit layer on the substrate 101 through the bonding wires 40 .

[0077] In this embodiment, the material of the plastic sealing body 30 is epoxy resin or acrylic resin, preferably epoxy resin. The materials of the first plastic sealing body 31 and the second plastic sealing body 32 are the same or different.

[0078] Exemplarily, in this embodiment, the bottom of the second plastic sealing body 32 is flush with the back surface of the substrate, the second plastic sealing body 32 is formed on the outer side of the substrate 101 , and part of the second plastic sealing body 32 covers the first plastic sealing body 31 .

[0079] In this example, the outer periphery of the first plastic packaging body 31 is rectangular, and the outer periphery of the second plastic packaging body is square.

[0080] In other embodiments, the outer circumference of the first plastic packaging body 31 may also be square, and the outer circumference of the second plastic packaging body 32 may be circular or rectangular.

[0081] The chip packaging method in this embodiment includes:

[0082] 1. Ginseng Figure 5a Combined with Figure 5b As shown, a packaging substrate 10 is provided, the front side of the packaging substrate 10 includes a plurality of first areas S11 arranged in an array and a first isolation area S12 located between adjacent first areas S11, the back side of the packaging substrate 10 includes a plurality of second areas S21 arranged in an array and a second isolation area S22 located between adjacent second areas S21, the first area S11 and the second area S21 are arranged opposite to each other, the first isolation area S12 and the second isolation area S22 are arranged opposite to each other, and a plurality of pads 11 are provided on the second area S21.

[0083] Specifically, the first area S11 and the second area S21 are arrayed on the front and back of the package substrate 10 according to the minimum package size of the chip 20. The ratio of the area of ​​the first area S11 or the second area S21 to the projection area of ​​the chip on the first area S11 is (1.2-2.5):1.

[0084] Exemplarily, in this embodiment, the size of the chip 20 is 4 mm*5 mm, the size of the first region S11 is 6 mm*8 mm, and the ratio of the area of ​​the first region S11 to the projection area of ​​the chip on the first region S11 is 2.4:1.

[0085] 2. The chip 20 is packaged in the first area S11 on the front side of the packaging substrate 10. The chip 20 is electrically connected to the pad 11 through the circuit layer on the packaging substrate 10. The packaging substrate 10 and the chip 20 are plastic-sealed to obtain a first packaging structure including a first plastic packaging body 31.

[0086] Ginseng Figure 5b As shown, in this embodiment, the size of the packaging substrate 10 is 240 mm*74 mm, and the chip 20 is packaged on the first area S11 on the front side of the packaging substrate 10 . In this embodiment, a total of 296 chips 20 are packaged on the packaging substrate 10 .

[0087] Exemplarily, the chip 20 is packaged on the first area S11 by wire bonding, and the first plastic package 31 encapsulates the front surface of the package substrate 10, the front surface of the chip 20 and the bonding wires 40. The bonding wires 40 in this embodiment are gold wires.

[0088] 3. Ginseng Figure 5c As shown, the package substrate 10 and the first plastic package body 31 in the first package structure are cut along the first isolation region S12 or the second isolation region S22 to obtain a plurality of package bodies.

[0089] Specifically, in this example, along the second isolation region S22 ( Figure 5c The packaging substrate 10 and the first plastic package body 31 are cut at the dotted line position.

[0090] 4. Ginseng Figure 5d As shown, a plurality of packages are arrayed on a carrier 50, and adjacent packages are spaced apart.

[0091] Specifically, a release film (not shown) is disposed on the carrier 50 , a plurality of packages are arrayed on the release film, and the pads 11 are in contact with the release film.

[0092] Furthermore, the ratio of the total area of ​​the first region S11 to the total area of ​​the front surface of the package substrate 10 is greater than the ratio of the total area of ​​the package body projected on the carrier 50 to the total area of ​​the carrier 50 .

[0093] Exemplarily, the first direction in this embodiment is the X-axis direction, and the second direction is the Y-axis direction.

[0094] Ginseng Figure 5d Combined with Figure 5a As shown, the width of the first isolation region S12 along the X-axis direction is d x1The distance between adjacent packages on the carrier 50 along the X-axis direction is d x2 ; d of the second isolation region S22 along the Y-axis direction y1 The distance between adjacent packages on the carrier 50 along the Y axis is d y2 In this embodiment, d x2 >d x1 And d y2 >d y1 .

[0095] In other embodiments, only d x2 >d x1 or y2 >d y1 .

[0096] It should be understood that d x2 and y2 The design should match the size of the chip packaging structure required by the circuit design, so as to facilitate cutting after secondary plastic packaging to obtain a chip packaging structure with a size that meets the design requirements.

[0097] 5. Perform secondary plastic sealing on the carrier 50 and the packaging body. After the secondary plastic sealing is completed, the carrier 50 is peeled off to obtain a second packaging structure including the first plastic sealing body 31 and the second plastic sealing body 32.

[0098] Exemplarily, the second plastic package body 32 is formed on the outside and top of the package body, that is, during the secondary plastic packaging process, the plastic package fills the spacing area between the packages on the carrier 50 and covers the first plastic package body 31 .

[0099] 6. Cut the second plastic package body 32 in the second package structure along the spacing area between adjacent package bodies to obtain multiple chip package structures.

[0100] Specifically, according to the design requirements of the circuit, the second packaging structure is cut into single chip packaging structures with sizes that meet the requirements.

[0101] For example, Figure 5e As shown, the second plastic package body 32 in the second packaging structure is cut along the dotted line position in the figure to obtain a chip packaging structure with a size of 12mm*12mm.

[0102] For example, Figure 6 As shown, a plurality of pads 11 and positioning units 12 are provided on the second area S21 on the back of the package substrate 10. The positioning unit 12 is intended to determine the direction of the chip. The arrangement and number of the pads 11 can be adjusted accordingly according to design requirements.

[0103] It should be understood that the chip packaging method in this embodiment also includes conventional process steps such as preparing the chip on the wafer before packaging the chip 20 on the packaging substrate 10, thinning the wafer, cutting the wafer and performing wafer bonding after wafer film bonding; and conventional steps such as surface polishing of the plastic package body and inspection of the chip packaging structure after the secondary plastic sealing.

[0104] Compared with Comparative Example 1, the chip packaging structure and packaging method in this embodiment have greatly improved the utilization rate of the packaging substrate 10, and the utilization rate of the packaging substrate 10 is improved to 3 times that in Comparative Example 1.

[0105] Embodiment 2:

[0106] Ginseng Figure 7 As shown, the chip packaging structure and packaging method in this embodiment are substantially the same as those in Embodiment 1, except that the top of the second plastic packaging body 32 in this embodiment is flush with the top of the first plastic packaging body 31 .

[0107] Embodiment 3:

[0108] The chip packaging structure and packaging method in this embodiment are substantially the same as those in Embodiment 1, except that the chip packaging structure in this embodiment is designed to be a circle with a diameter of 10 mm, the size of the chip 20 is 3 mm*4 mm, the size of the first area S21 is designed to be 4 mm*5 mm, and the ratio of the area of ​​the first area S11 to the projection area of ​​the chip 20 on the first area S11 is approximately 1.7:1.

[0109] It can be seen from the above scheme that the present invention has the following beneficial effects:

[0110] The present invention first performs a plastic encapsulation according to the size of the chip with the minimum packaging size, and after cutting, the chip packaging structure with a size that meets the design requirements is obtained by rearrangement and secondary plastic encapsulation, which greatly improves the utilization rate of the packaging substrate, reduces costs and improves production efficiency. At the same time, the size of the chip packaging structure can be easily adjusted without repeatedly customizing the substrate.

[0111] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0112] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A chip packaging method, characterized in that: The packaging method comprises: A packaging substrate is provided, wherein the front side of the packaging substrate comprises a plurality of first areas arranged in an array and a first isolation area located between adjacent first areas, the back side of the packaging substrate comprises a plurality of second areas arranged in an array and a second isolation area located between adjacent second areas, the first areas and the second areas are arranged opposite to each other, the first isolation area and the second isolation area are arranged opposite to each other, and a plurality of pads are arranged on the second areas; The chip is packaged on the first area on the front side of the packaging substrate, the chip is electrically connected to the pad through the circuit layer on the packaging substrate, and the packaging substrate and the chip are plastic-sealed once to obtain a first packaging structure including a first plastic-sealed body; Cutting the packaging substrate and the first plastic packaging body in the first packaging structure along the first isolation region or the second isolation region to obtain a plurality of packaging bodies; Arrange a plurality of package arrays on a carrier board, with adjacent packages spaced apart; Performing secondary plastic sealing on the carrier and the packaging body, and peeling off the carrier after the secondary plastic sealing is completed to obtain a second packaging structure including the first plastic sealing body and the second plastic sealing body; The second plastic package body in the second package structure is cut along the spacing area between adjacent package bodies to obtain a plurality of chip package structures.

2. The chip packaging method according to claim 1, characterized in that: The ratio of the total area of ​​the first region to the total area of ​​the front surface of the packaging substrate is greater than the ratio of the total area of ​​the projection of the packaging body on the carrier to the total area of ​​the carrier.

3. The chip packaging method according to claim 2, characterized in that: The distance between adjacent packages on the carrier along the first direction is greater than the width of the first isolation region along the first direction; and / or, The distance between adjacent packages on the carrier along the second direction is greater than the width of the first isolation region along the second direction.

4. The chip packaging method according to claim 1, characterized in that: The ratio of the area of ​​the first region to the projection area of ​​the chip on the first region is (1.2-2.5):

1.

5. The chip packaging method according to claim 1, characterized in that: The chip is packaged on the first area on the front side of the packaging substrate by wire bonding.

6. The chip packaging method according to claim 1, characterized in that: A release film is disposed on the carrier plate, the plurality of packages are arrayed on the release film, and the pad is in contact with the release film.

7. A chip packaging structure, characterized in that: The packaging structure comprises: A substrate, wherein a plurality of pads are provided on the back side of the substrate; A chip is packaged on the front side of the substrate, and the chip is electrically connected to the pad through the circuit layer on the substrate; The plastic package body comprises a first plastic package body formed on the substrate and the front side of the chip and a second plastic package body formed on the outer side of the substrate.

8. The chip packaging structure according to claim 7, characterized in that: The bottom of the second plastic packaging body is flush with the back side of the substrate, and the top of the second plastic packaging body is flush with the top of the first plastic packaging body.

9. The chip packaging structure according to claim 7, characterized in that: Part of the second plastic packaging body covers the first plastic packaging body.

10. The chip packaging structure according to claim 7, characterized in that: The outer circumference of the second plastic-sealed body is circular, square or rectangular, and the outer circumference of the first plastic-sealed body is square or rectangular.

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