Power supply network RDL layout

Abstract

The invention discloses a power supply network RDL layout, and relates to the technical field of chips, the power supply network RDL layout comprises a plurality of power supply salient points used for connecting chips, the power supply salient points are arranged at intervals along a first direction, the power supply salient points are arranged in multiple rows in a staggered manner along a second direction, the first direction is perpendicular to the second direction, and the power supply network RDL layout comprises a first wire, a second wire and a third wire, the plurality of first wires extend along the first direction and are arranged at intervals along the second direction, and each first wire penetrates through the center of one row of power supply salient points to connect one row of power supply salient points; and the second wires are arranged between every two adjacent first wires, each second wire comprises a plurality of second connecting wires which are arranged at intervals in the first direction, and each second connecting wire is correspondingly connected with the edge of one power supply salient point. According to the technical scheme provided by the invention, the RDL in the chip is improved, the current distribution and stress distribution on the RDL are balanced, the manufacturing yield of the chip is improved, and the normal working time of the chip is prolonged.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a power supply network RDL layout. Background Art

[0002] In order to take into account the impact of various factors in chip design and manufacturing, for ultra-large-scale chips using the existing traditional standard flip-chip packaging, in order to ensure reliability, during the chip physical design process, physical design engineers will try their best to reduce the power bump spacing of the power network on the chip.

[0003] However, the shortening of the power bump pitch will also reduce the spacing of the redistribution metal layer power network RDL inside the chip. Figures 3 to 5 FIG. 1 is a layout diagram of the power network RDL after the power bump pitch is reduced under the existing process, wherein the power network RDL connects multiple power bumps horizontally, that is, the power network RDL can only connect power bumps of a single attribute, which results in that the power network RDL between two adjacent rows of power bumps of different attributes can only be connected to the power bumps of one attribute, while the edge of the power bump of the other attribute cannot be covered by the power network RDL, so that the power bump can only be connected like Figure 3 The power network RDL covers three-quarters or even one-half of the power bumps, so the stress distribution around the power bumps will be different, which can easily lead to chip damage during processing. In addition, the current from the power bumps to the power network RDL will also be unevenly distributed, resulting in excessive local current, affecting the reliability of the chip. Summary of the invention

[0004] The main purpose of the present invention is to propose a power network RDL layout, which aims to balance the current distribution and stress distribution on the power network RDL and extend the normal working time of the chip.

[0005] To achieve the above-mentioned object, the present invention proposes a power network RDL layout, which is used to connect the power bumps of a chip, wherein a plurality of the power bumps are arranged at intervals along a first direction, and the power bumps are arranged in multiple rows staggered along a second direction, and the first direction is perpendicular to the second direction. The power network RDL layout includes: A first conductive wire extending along the first direction and arranged in plurality along the second direction, each of the first conductive wires passing through the center of a row of the power bumps to connect the row of the power bumps; The second conductive wire is arranged between every two adjacent first conductive wires. The second conductive wire includes a plurality of second connecting wires arranged at intervals along the first direction. Each second connecting wire is correspondingly connected to an edge of the power bump.

[0006] In one embodiment, the power network RDL layout further includes a connection layer, and one connection layer is provided corresponding to each power bump, and the connection layer connects the first conductive line corresponding to the power bump and the second connection line corresponding to the power bump.

[0007] In one embodiment, the power network RDL layout further includes a power through hole, and a plurality of the power through holes are provided. The plurality of the power through holes are densely distributed on the first conductive line and the second conductive line and are arranged around the power bump.

[0008] In one embodiment, the power through holes on the first conductive wires and the second conductive wires are arranged in a matrix.

[0009] In one embodiment, in the second direction, at least two rows of the power through holes are disposed on each of the second connecting lines.

[0010] In one embodiment, the maximum spacing between power vias on any two adjacent first conductive lines of the same attribute is D, wherein D is not greater than 116 micrometers.

[0011] Compared with the prior art, in the technical solution of the present invention, the power network RDL layout includes a first wire and a second wire, the first wire and the second wire both extend along the first direction, each metal layer runs through the center of a row of power bumps and connects the row of power bumps, the second wire is arranged between two adjacent first wires, and the second wire includes a plurality of second connecting wires arranged in parallel along the first direction, and each second connecting wire is connected to the edge of a power bump. In this way, the center of each power bump is covered by the first wire, and the edge of each power bump is covered by the second connecting wire, and the first wire and the second wire cooperate to cover the edge and center of each power bump. In this way, during the processing, the stress of each power bump can be evenly dispersed outward, ensuring the uniformity of stress distribution on the entire chip, thereby preventing the occurrence of excessive local stress on the chip and improving the reliability of the chip; in addition, the current passing through each power bump can also be evenly dispersed around the power bump, which also prevents local concentration of current and is also conducive to improving the reliability of the chip. Moreover, when the power network RDL adopts this type of structure, the spacing between the power bumps can be further reduced without causing uneven stress and current distribution, which is beneficial to extending the life of the chip and extending the normal working time of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0013] Figure 1 A schematic diagram of the structure of the power network RDL layout provided by the present invention; Figure 2 for Figure 1 A partial enlarged view of any power bump; Figure 3 It is a structural schematic diagram of the existing power network RDL layout; Figure 4 for Figure 3 A partial enlarged view of any power bump; Figure 5 Another structural schematic diagram of an existing power network RDL layout.

[0014] Description of Figure Numbers: 100, first conductive wire; 110, first connecting wire; 200, second conductive wire; 210, second connecting wire; 300, power bump; 400, power through hole.

[0015] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0016] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0017] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components in a certain specific posture. If the specific posture changes, the directional indication will also change accordingly.

[0018] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features limited to "first" and "second" may explicitly or implicitly include at least one of the features. In addition, if "and / or" or "and / or" appears in the full text, its meaning includes three parallel solutions. Taking "A and / or B" as an example, it includes solution A, solution B, or solutions that satisfy both A and B. In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the ability of ordinary technicians in this field to implement. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0019] In order to balance the current distribution and stress distribution on the power network RDL while reducing the spacing between the power bumps 300, the technical solution proposes a power network RDL layout for connecting the power bumps 300 of the chip, wherein a plurality of power bumps 300 are arranged at intervals along a first direction, and the power bumps 300 are arranged in multiple rows staggered along a second direction, and the first direction is perpendicular to the second direction, and the power network RDL layout includes: A plurality of first conductive wires 100 extending along the first direction and spaced apart along the second direction, each first conductive wire 100 passing through the center of a row of power bumps 300 to connect the row of power bumps 300; The second conductive wire 200 is disposed between every two adjacent first conductive wires 100 . The second conductive wire 200 includes a plurality of second connecting wires 210 spaced apart along the first direction. Each second connecting wire 210 is connected to an edge of a power bump 300 .

[0020] Compared with the prior art, in the technical solution of the present invention, the power network RDL layout includes a first conductor 100 and a second conductor 200, both of which extend along a first direction, and each metal layer passes through the center of a row of power bumps 300 and connects the row of power bumps 300. The second conductor 200 is arranged between two adjacent first conductors 100, and the second conductor 200 includes a plurality of second connecting wires 210 arranged in parallel along the first direction, and each second connecting wire 210 is connected to the edge of a power bump 300. In this way, the center of each power bump 300 is covered by the first wire 100, and the edge of each power bump 300 is covered by the second connecting wire 210. The first wire 100 and the second wire 200 cooperate to cover the edge and center of each power bump 300. In this way, during the processing, the stress of each power bump 300 can be evenly dispersed outward, ensuring the uniformity of stress distribution on the entire chip, thereby preventing the occurrence of excessive local stress on the chip and improving the reliability of the chip; in addition, the current passing through each power bump 300 can also be evenly dispersed around the power bump 300, which also prevents local concentration of current and is also conducive to improving the reliability of the chip. And when the power network RDL adopts this structure, the spacing of the power bump 300 can be further reduced without causing uneven stress and current distribution, which is conducive to extending the life of the chip and extending the timeliness of the normal operation of the chip.

[0021] like Figure 1 and Figure 2, the red and green lines extending in the horizontal direction in the figure belong to first wires 100 of different properties, that is, any two adjacent first wires 100 correspond to circuits of different properties (power / ground) on the connected chip, each first wire 100 corresponds to a row of power bumps 300, and the first wire 100 covers the central area of ​​the row of power bumps 300 corresponding to it, and connects these power bumps 300. A second wire 200 is arranged between any two adjacent first wires 100, and each second wire 200 is composed of a plurality of second connecting wires 210 arranged in parallel along the first direction, and each second connecting wire 210 corresponds to a power bump 300 position in the second direction, and each second connecting wire 210 covers the edge of the corresponding power bump 300. This layout ensures that each power bump 300 is not only covered by the first wire 100 at its center, but also effectively electrically connected at its edge through the second connecting wire 210; in this way, each power bump 300 is completely covered both from the center and the edge, which helps to more evenly disperse the stress applied to the power bump 300 during the chip manufacturing process. When external force acts on the chip, due to the presence of the metal layer, the stress can be effectively guided to be uniformly transmitted to the entire chip surface along the metal path, thereby avoiding the risk of damage caused by uneven force in local areas and greatly improving the mechanical stability of the chip. In addition, this structure also has a positive effect on the uniform distribution of current. The current flowing through the center of the power bump 300 can be diffused from the first wire 100 and the second connecting wire 210 to the surroundings, making the current conduction more balanced and reducing the risk of failure caused by current concentration. This feature is particularly important for the application of high power density chips. In addition, thanks to the structure in the technical solution, even if the spacing between the power bumps 300 is further reduced, each power bump 300 can still maintain a good stress and current distribution state. This means that without affecting the uniformity of stress distribution and current distribution, the number of any two adjacent power bumps 300 with the same properties can be designed to be greater, which can further reduce the stress distribution difference.

[0022] like Figure 2 In one embodiment of the present invention, the power network RDL layout further includes a connection layer, and each power bump 300 is provided with a connection layer corresponding to the power bump 300, and the connection layer connects the first wire 100 corresponding to the power bump 300 and the second connection line 210 corresponding to the power bump 300. The provision of the connection layer can further promote the uniform distribution of current around the power bump 300, further prevent the local concentration of current, and reduce the risk of damage caused by local overheating or stress concentration.

[0023] like Figure 2In one embodiment of the present invention, the power network RDL layout further includes a power through hole 400, and a plurality of power through holes 400 are provided. The plurality of power through holes 400 are densely distributed on the first wire 100 and the second wire 200 and are arranged around the power bump 300; the power bump 300 connects the first wire 100 and the second wire 200 to the deeper circuit on the chip, so that the current can be more evenly and efficiently conducted between the power network RDL layer and the top metal layer, thereby reducing the loss in the signal transmission process and improving the working efficiency of the overall circuit; in addition, the uniform distribution of the power through holes 400 also plays a role in enhancing the mechanical stability of the power network RDL structure, which enhances the bonding force between different metal layers and reduces the risk of failure caused by physical factors; such as Figure 4 ,In the traditional power network RDL layout, the power bump cannot be completely covered by the ,first conductor with the same property, which causes the through-current to be concentrated on individual RV ,power vias, for example Figure 4 The two power through holes indicated in the figure have the problem of excessive current because there are no other power through holes nearby for shunting, and the current of each power through hole is uneven, which may easily cause premature aging of individual power through holes and affect the working life of the chip; in this solution, power through holes 400 are densely distributed on the first wire 100 and the second wire 200, and the power through holes around the power bump are distributed more evenly, so that the current can be dispersed and the possibility of local current concentration is reduced.

[0024] In one embodiment of the present invention, the power vias 400 on the first conductive wire 100 and the second conductive wire 200 are arranged in a matrix. The matrix arrangement can further improve the uniformity of current dispersion in the power vias 400 and improve chip performance.

[0025] In one embodiment of the present invention, at least two rows of power through holes 400 are disposed on each second connection line 210 in the second direction. This ensures that there are power through holes 400 around the power bump 300, ensures that the current of the power bump 300 can be evenly distributed around the four sides, and prevents abnormally high current flow through individual power through holes 400, which is beneficial to further ensure the reliability of the chip.

[0026] like Figure 2 In one embodiment of the present invention, the maximum spacing between the power supply vias 400 on any two adjacent first conductive lines 100 of the same property is D, wherein D is not greater than 116 microns; Figure 3For this traditional structure, the spacing between any two adjacent first conductive lines 100 is designed to be smaller. In this solution, the optimal design of D is 116 microns, so that the redistribution metal layer power network RDL is more uniform in the entire power network RDL layout and the top metal connection in the chip, so that when the current demand of the chip is large in any local range, there will be no abnormally high current flow through individual power vias 400, so as to balance the complete and uniform distribution of all current paths, so as to achieve the purpose of improving the overall physical consistency of the chip.

[0027] The above description is only an exemplary embodiment of the present invention, and does not limit the patent scope of the present invention. All equivalent structural changes made by using the contents of the present invention specification and drawings under the technical concept of the present invention, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present invention.

Claims

1. A power network RDL layout, used for connecting power bumps of a chip, wherein a plurality of power bumps are arranged at intervals along a first direction, and a plurality of power bumps are arranged in a staggered manner along a second direction, wherein the first direction is perpendicular to the second direction, and wherein: The power network RDL layout includes: A first conductive wire extending along the first direction and arranged in plurality along the second direction, each of the first conductive wires passing through the center of a row of the power bumps to connect the row of the power bumps; The second conductive wire is arranged between every two adjacent first conductive wires. The second conductive wire includes a plurality of second connecting wires arranged at intervals along the first direction. Each second connecting wire is correspondingly connected to an edge of the power bump.

2. The power network RDL layout according to claim 1, characterized in that: The power network RDL layout also includes a connection layer. One connection layer is provided corresponding to each power bump. The connection layer connects the first conductive line corresponding to the power bump and the second connection line corresponding to the power bump.

3. The power network RDL layout according to claim 2, characterized in that: The power network RDL layout also includes a power through hole, and a plurality of the power through holes are provided. The plurality of the power through holes are densely distributed on the first conductive line and the second conductive line and are arranged around the power bump.

4. The power network RDL layout according to claim 3, characterized in that: The power through holes on the first conductive wires and the second conductive wires are arranged in a matrix.

5. The power network RDL layout according to claim 4, characterized in that: In the second direction, at least two rows of the power through holes are disposed on each of the second connecting lines.

6. The power network RDL layout according to claim 5, characterized in that: The maximum spacing between the power supply vias on any two adjacent first conductive lines of the same attribute is D, wherein D is not greater than 116 micrometers.

Images