Method of fabricating a semiconductor test structure

Abstract

The application relates to a preparation method of a semiconductor test structure, which comprises the following steps: providing a substrate; forming a plurality of mask strips on the top surface of the substrate, which are spaced apart along a first direction and extend along a second direction; performing ion implantation processes with the same energy and different doses on initial test areas at least by taking the plurality of mask strips as mask plates to obtain target test structures comprising two doped regions; determining a first target test correlation between the ion implantation dose, the diffusion width and the breakdown voltage of different target test structures according to the ion implantation dose, the diffusion width and the breakdown voltage of the plurality of target test structures; and determining the actual diffusion width of a target test junction to be measured according to the actual ion implantation dose and the actual breakdown voltage of the target test junction to be measured. Based on the existing process flow, no additional mask is needed. Through simple and effective target test structures, the target test correlation for monitoring the actual diffusion width of ion implantation is obtained, and the influence of implantation under different dose conditions on the device performance is further reflected.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a preparation method of a semiconductor test structure. BACKGROUND

[0002] Ion implantation is one of the indispensable material modification methods in modern integrated circuit manufacturing processes. The essence is to focus ionized impurity atoms or molecules into an ion beam, and then implant them into a semiconductor substrate according to the design with a specific energy and dose, so as to achieve the doping requirement. When the ion beam is incident on the material surface, the charged ions are affected by the interaction of the target atomic nucleus and the surrounding electron cloud, and their speed and direction change, and finally form a certain spatial distribution in the substrate. However, during device debugging, the implanted impurity ions will collide with silicon atoms in the substrate, causing lateral diffusion (scattering), resulting in an increase in the diffusion range of the implanted ions, as shown in FIG. 1, which is different from the device structure of the actual layout design, and further affects the device performance. Figure 1

[0003] This not only affects the accuracy of the circuit layout, but also may cause unintended changes in circuit characteristics, such as weakened current control, threshold voltage shift, etc. Therefore, monitoring the lateral diffusion degree of ion implantation is crucial for ensuring the optimization of electronic device performance and stable circuit characteristics. SUMMARY

[0004] Therefore, it is necessary to provide a preparation method of a semiconductor test structure to at least monitor the lateral diffusion width of ion implantation, and further better optimize the debugging of the required ions of the device.

[0005] In a first aspect, the present application provides a preparation method of a semiconductor structure, comprising: providing a substrate; forming a plurality of mask strips on the top surface of the substrate, which are spaced apart along a first direction and extend along a second direction; the substrate between adjacent two mask strips is used to constitute an initial test area; adjacent two initial test areas are used to constitute an initial test structure; adjacent initial test structures are spaced apart along the first direction; the first direction and the second direction intersect and are parallel to the top surface of the substrate;

[0006] At least using the plurality of mask strips as a mask plate, ion implantation process is performed on the initial test area to obtain a target test structure comprising two doped regions, wherein the ion implantation energy of different target test structures is the same and the dose is different;

[0007] ​The first target test correlation between the ion implantation dose, the diffusion width and the breakdown voltage of the different target test structures is determined according to the ion implantation dose, the diffusion width and the breakdown voltage of the multiple target test structures; and the first target test correlation is used to determine the actual diffusion width of the target test junction under test according to the actual ion implantation dose and the actual breakdown voltage of the target test junction under test.

[0008] In the above method for preparing a semiconductor test structure for actual diffusion width of ion implantation, target test structures corresponding to ion implantation doses are sequentially prepared by performing ion implantation processes with the same energy and different doses in the structure process. The target test junction under test is formed in the target test structure due to the difference in the conductivity type between the doped region and the substrate. The electrical performance of each target test junction under test is measured to collect the corresponding breakdown voltage. The first target test correlation between the ion implantation dose, the diffusion width and the breakdown voltage is established according to the ion implantation dose, the diffusion width and the breakdown voltage of the multiple target test structures.

[0009] In short, this method can effectively dynamically monitor and quantify the lateral diffusion behavior of ions under different doses but with constant energy, reflect the actual diffusion width of the target test junction under test under different doses to determine the actual ion implantation range, reduce the redundant repeated experiments and data analysis in the subsequent device debugging process, and lay a foundation for subsequent optimization of device design and research.

[0010] In some embodiments, the substrate includes a substrate and a first-type semiconductor layer on the substrate; the doped region is a second doped region; and the multiple mask strips on the top surface of the substrate are formed by: forming a mask layer on the top surface of the first-type semiconductor layer; and patterning the mask layer to obtain multiple mask strips spaced apart along a first direction and extending along a second direction.

[0011] In some embodiments, the ion implantation process is performed on the initial test structure by: forming an ion implantation mask above the initial test structure; and using the ion implantation mask and the multiple mask strips as a mask plate to perform the ion implantation process on the initial test structure by a self-alignment process to obtain the multiple target test structures.

[0012] In some embodiments, the first type is P-type and the second type is N-type, or the first type is N-type and the second type is P-type.

[0013] In some embodiments, the spacing between adjacent mask strips is greater than or equal to a preset threshold.

[0014] In a second aspect, the present application further provides a method for preparing a semiconductor test structure, comprising: providing a substrate; forming a plurality of mask strips spaced apart along a first direction and extending along a second direction on a top surface of the substrate; the substrate between two adjacent mask strips is used to form an initial test area; two adjacent initial test areas are used to form an initial test structure; adjacent initial test structures are spaced apart along the first direction; the first direction and the second direction intersect and are both parallel to the top surface of the substrate;

[0015] An ion implantation process is performed into an initial test region using at least a plurality of mask strips as a mask to obtain a target test structure including two doped regions, wherein the implanted ion energies and doses of different target test structures are the same but the target sizes are different; the target size is the spacing between adjacent mask strips along a first direction, or the length of the mask strips along the first direction;

[0016] Based on the target sizes, diffusion widths and breakdown voltages of multiple target test structures, a second target test association relationship between the target sizes, diffusion widths and breakdown voltages of different target test structures is determined; the second target test association relationship is used to determine the measured diffusion width of the target test junction to be tested based on the actual target size and actual breakdown voltage of the target test junction to be tested.

[0017] In the aforementioned method for fabricating another semiconductor test structure with an actual diffusion width using ion implantation, ion implantation processes with the same energy but different doses are performed during the fabrication process to sequentially fabricate target test structures corresponding to the implanted doses, form target test junctions to be tested, and measure the electrical properties of each target test junction to collect the corresponding breakdown voltage. The aforementioned process is then repeated for multiple test structures with different target sizes to determine a second target test correlation relationship between the target size, diffusion width, and breakdown voltage of each target test structure.

[0018] Based on the original preparation method, this method adjusts the target size of the target test structure and simultaneously monitors the ion implantation range corresponding to different implanted ion doses under multiple target sizes, thereby broadening the diversity of semiconductor test structures.

[0019] In some embodiments, the substrate includes a base and a first-type semiconductor layer located on the base; the doped region is a second-type doped region; a plurality of mask strips are formed on the top surface of the substrate, including: forming a mask layer on the top surface of the first-type semiconductor layer; patterning the mask layer to obtain a plurality of mask strips spaced apart along a first direction and extending along a second direction.

[0020] In some embodiments, the first type is P-type and the second type is N-type; or the first type is N-type and the second type is P-type.

[0021] In some embodiments, the target size is the spacing between adjacent mask strips along the first direction; when the target size is the maximum value and the adjacent doped regions are in contact, the minimum value of the breakdown voltage and the maximum value of the diffusion width are obtained; when the target size is the minimum value, the maximum value of the breakdown voltage and the minimum value of the diffusion width are obtained; the maximum value of the diffusion width and the minimum value of the diffusion width are used to determine whether the measured diffusion width of the test junction under test is abnormal.

[0022] In some embodiments, the target size is the length of the mask strip along the first direction; when the target size is the minimum value and the adjacent doped regions are in contact, the minimum value of the breakdown voltage and the maximum value of the diffusion width are obtained; when the target size is the maximum value, the maximum value of the breakdown voltage and the minimum value of the diffusion width are obtained; the maximum value of the diffusion width and the minimum value of the diffusion width are used to determine whether the measured diffusion width of the test junction under test is abnormal.

[0023] In the above embodiments, the unexpected technical effects of the present application are:

[0024] Based on the existing process flow, by means of simple and effective target test structures, the first target test correlation between the implanted ion dose, the diffusion width and the breakdown voltage of different target test structures, and the second target test correlation between the target size, the diffusion width and the breakdown voltage are established. Through the first target test correlation and the second target test correlation, the actual width of ion implantation lateral diffusion of multiple target sizes under different doses and the same energy is monitored, and then the actual ion implantation range under different dose conditions is reflected, so as to better optimize the debugging of the required ions of the device.

[0025] These methods not only realize the dynamic quantification of ion lateral diffusion behavior, reveal the influence on device performance under different doses, reduce repeated experiments, but also realize real-time monitoring of diffusion width of multiple sizes by adjusting the target size, significantly improve the diversity of test structures, and provide effective tools and foundation for optimizing device design and reducing subsequent research work. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0027] Figure 1 A layout design diffusion width and actual diffusion width comparison chart for a device structure;

[0028] Figure 21 is a schematic flow chart of a method for preparing a semiconductor test structure provided in one embodiment;

[0029] Figure 3 1. A schematic cross-sectional view of a structure obtained by forming a mask strip in step S1044 of a method for preparing a semiconductor structure provided in one embodiment;

[0030] Figure 4 1 is a schematic cross-sectional view of a structure obtained after forming a doped region in step S1062 in a method for preparing a semiconductor structure provided in one embodiment;

[0031] Figure 5 1 is a schematic cross-sectional view of a structure obtained after forming electrical connectors in step S1064 in a method for preparing a semiconductor structure provided in one embodiment;

[0032] Figure 6 Schematic diagram of the cross section of the structure obtained after performing ion implantation processes with the same energy and different doses;

[0033] Figure 7 for Figure 6 A schematic cross-sectional view of the structure obtained after the electrical connector is formed;

[0034] Figure 8 Schematic diagram of a process for preparing a semiconductor test structure provided in another embodiment;

[0035] Figure 9 1 is a schematic cross-sectional view of a structure obtained after forming a doped region in step S206 of a method for preparing a semiconductor structure provided in one embodiment;

[0036] Figure 10 1 is a schematic cross-sectional view of a structure obtained after a target size D1 is changed in a method for preparing a semiconductor structure provided in one embodiment;

[0037] Figure 11 1 is a schematic cross-sectional view of a structure obtained after a target size D2 is changed in a method for preparing a semiconductor structure provided in one embodiment;

[0038] Figure 12a A schematic cross-sectional view of a structure corresponding to obtaining a minimum breakdown voltage and a maximum diffusion width in a method for preparing a semiconductor structure provided in an embodiment;

[0039] Figure 12b for Figure 12a A schematic diagram of the structure in the plane formed by the first direction and the second direction;

[0040] Figure 13a A schematic cross-sectional view of a structure corresponding to the process of obtaining the maximum breakdown voltage and the minimum diffusion width in a method for preparing a semiconductor structure provided in an embodiment;

[0041] Figure 13b Fig. 1 is a schematic diagram of a structure in a first direction and a second direction forming a plane according to an embodiment of the present application; Figure 13a Fig. 1 is a schematic diagram of a structure in a first direction and a second direction forming a plane according to an embodiment of the present application;

[0042] Figure 14a Fig. 2 is a schematic diagram of a cross-section of a structure corresponding to a normal diffusion of ion implantation in a method of manufacturing a semiconductor structure according to an embodiment of the present application;

[0043] Figure 14b Fig. 2 is a schematic diagram of a cross-section of a structure corresponding to a normal diffusion of ion implantation in a method of manufacturing a semiconductor structure according to an embodiment of the present application; Figure 14a Fig. 1 is a schematic diagram of a structure in a first direction and a second direction forming a plane according to an embodiment of the present application;

[0044] BRIEF DESCRIPTION OF DRAWINGS

[0045] 10, substrate; 101, base; 102, first type semiconductor layer; 11, dielectric layer; 12, mask strip; 13, doped region; 131, first doped region; 132, second doped region; 14, electrical connection. DETAILED DESCRIPTION

[0046] In order to facilitate the understanding of the present application, a more complete understanding of the present application can be had by reference to the following description and the accompanying drawings. In the following description and drawings, identical reference characters refer to the same elements throughout. By way of illustration, and without intent to limit the application, embodiments of the application will now be described in detail in conjunction with popular embodiments. Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in various embodiments.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0048] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will also be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section; for example, a first doped type could be termed a second doped type; and similarly, a second doped type could be termed a first doped type; a first doped type and a second doped type are different doped types, for example, a first doped type can be P-type and a second doped type can be N-type, or a first doped type can be N-type and a second doped type can be P-type.

[0049] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in the other direction (for example, rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. The terms "first", "second", "third", etc. can be used herein to describe various elements, components, regions, layers and / or sections but do not require or imply a particular order or sequence unless explicitly stated otherwise.

[0050] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It should also be understood that, unless clearly indicated to the contrary, the word "comprise" and / or the like does not exclude the presence of one or more other features, integers, steps, operations, elements, and / or components but does include such. Also, as used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0051] Embodiments of the application are described herein with reference to the drawings, which show idealized embodiments of the application (and intermediate structures) in cross-section. Variations in the shapes of the regions shown in the drawings can occur due to, for example, manufacturing processes and / or tolerances, and therefore embodiments of the application should not be construed as limited to the particular shapes of regions shown in the drawings. For example, an implanted region that is shown as a rectangle will typically have rounded or curved features at its edges and / or an implant concentration gradient, rather than a binary change from the implanted region to the non-implanted region. Similarly, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which the implant was performed. Thus, the regions shown in the drawings are schematic in nature and their shapes are not intended to be limiting of the scope of the present application.

[0052] Referring now to the drawings, wherein like reference numerals designate identical structures throughout the several views, Figure 2 The present application provides a method for manufacturing a semiconductor test structure, comprising: step S102-step S108.

[0053] Step S102: providing a substrate 10.

[0054] In some embodiments, the substrate 10 comprises a base 101 and a first-type semiconductor layer 102 on the base 101; the doped region 13 is a second-type doped region.

[0055] In some embodiments, the first type is P-type and the second type is N-type; or the first type is N-type and the second type is P-type.

[0056] Specifically, the substrate 10 can comprise word line structures and capacitor contact structures, etc. Since they are not related to the inventive point of the present application, they are omitted.

[0057] The base 101 provides mechanical support for the first-type semiconductor layer 102.

[0058] The first-type semiconductor layer 102 can be a single-layer structure or a multi-layer structure. For example, the semiconductor layer can comprise a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the first-type semiconductor layer 102 can also comprise a Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon germanium-on-insulator substrate, etc. Therefore, the type of the first-type semiconductor layer 102 should not limit the protection scope of the present application.

[0059] Step S104: forming a plurality of mask strips 12 on the top surface of the substrate 10, the mask strips 12 being spaced apart along a first direction and extending along a second direction; the substrate between two adjacent mask strips 12 is used to form an initial test region; two adjacent initial test regions are used to form an initial test structure; adjacent initial test structures are spaced apart along the first direction; the first direction and the second direction are perpendicular to each other and parallel to the top surface of the substrate 10.

[0060] Referring to Figure 3 In some embodiments, step S104 further includes:

[0061] Step S1042: forming a mask layer (not shown) on the top surface of the first-type semiconductor layer 102.

[0062] Referring to Figure 3 Step S1044: patterning the mask layer to obtain the plurality of mask strips 12 spaced apart along the first direction and extending along the second direction.

[0063] For example, the dielectric layer can be formed of silicon dioxide (SiO2) or a material with high dielectric constant. For example, the material of the dielectric layer includes aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2) or strontium titanium oxide (SrTiO3).

[0064] In the embodiment, the material of the mask layer includes polysilicon.

[0065] Referring to Figure 4-Figure 7 Step S106: performing ion implantation on the initial test regions to obtain a plurality of target test structures including two doped regions 13, by taking the plurality of mask strips 12 as a mask, wherein the ion implantation energy of different target test structures is the same and the dose is different.

[0066] In some embodiments, step S106 further includes:

[0067] Step S1062: forming an ion implantation mask above the initial test structure; performing ion implantation on the initial test structure by taking the ion implantation mask and the plurality of mask strips 12 as a mask to obtain a plurality of target test structures by using a self-alignment process.

[0068] Step S1064: after each target test structure is obtained, an electrical connecting member 14 is arranged on the top surface of the doped region 13.

[0069] Referring to Figure 4-Figure 5 Specifically, as Figure 4As shown, the ion implantation process is a self-aligned process, placed after the etching mask strip 12, and based on the same mask, the second type of ions are implanted into the first type of semiconductor layer 102, that is, the implantation offset caused by the lithography alignment error is prevented, and the process is simple without additional masks. As shown in FIG. 2B, after the dose of the ion implantation process is performed, the first doped region 131 and the second doped region 132 are formed in the first type of semiconductor layer 102, which are spaced apart along the first direction. The electrical connection 14 is arranged on the top surface of the doped region 13, wherein the electrical connection 14 is configured to connect the first doped region 131 at the first end A and connect the second doped region 132 at the second end B. Figure 5 As shown in FIG. 2B, after the dose of the ion implantation process is performed, the first doped region 131 and the second doped region 132 are formed in the first type of semiconductor layer 102, which are spaced apart along the first direction. The electrical connection 14 is arranged on the top surface of the doped region 13, wherein the electrical connection 14 is configured to connect the first doped region 131 at the first end A and connect the second doped region 132 at the second end B.

[0070] As shown in FIG. 2B, after the dose of the ion implantation process is performed, the first doped region 131 and the second doped region 132 are formed in the first type of semiconductor layer 102, which are spaced apart along the first direction. The electrical connection 14 is arranged on the top surface of the doped region 13, wherein the electrical connection 14 is configured to connect the first doped region 131 at the first end A and connect the second doped region 132 at the second end B. Figure 6-Figure 7 , Figure 6 As shown in FIG. 2B, after the dose of the ion implantation process is performed, the first doped region 131 and the second doped region 132 are formed in the first type of semiconductor layer 102, which are spaced apart along the first direction. The electrical connection 14 is arranged on the top surface of the doped region 13, wherein the electrical connection 14 is configured to connect the first doped region 131 at the first end A and connect the second doped region 132 at the second end B. Figure 7 As shown in FIG. 2B, after the dose of the ion implantation process is performed, the first doped region 131 and the second doped region 132 are formed in the first type of semiconductor layer 102, which are spaced apart along the first direction. The electrical connection 14 is arranged on the top surface of the doped region 13, wherein the electrical connection 14 is configured to connect the first doped region 131 at the first end A and connect the second doped region 132 at the second end B.

[0071] Step S108: determining a first target test correlation between the implant ion dose, the diffusion width, and the breakdown voltage of different target test structures according to the implant ion dose, the diffusion width, and the breakdown voltage of the plurality of target test structures; the first target test correlation is used to determine the actual diffusion width of the target test junction to be tested according to the actual implant dose and the actual breakdown voltage of the target test junction to be tested.

[0072] As shown in FIG. 2B, after the dose of the ion implantation process is performed, the first doped region 131 and the second doped region 132 are formed in the first type of semiconductor layer 102, which are spaced apart along the first direction. The electrical connection 14 is arranged on the top surface of the doped region 13, wherein the electrical connection 14 is configured to connect the first doped region 131 at the first end A and connect the second doped region 132 at the second end B. Figure 7 As shown in FIG. 2B, after the dose of the ion implantation process is performed, the first doped region 131 and the second doped region 132 are formed in the first type of semiconductor layer 102, which are spaced apart along the first direction. The electrical connection 14 is arranged on the top surface of the doped region 13, wherein the electrical connection 14 is configured to connect the first doped region 131 at the first end A and connect the second doped region 132 at the second end B.

[0073] In some embodiments, the spacing between adjacent mask strips 12 is greater than or equal to a preset threshold.

[0074] As shown in FIG. 2B, after the dose of the ion implantation process is performed, the first doped region 131 and the second doped region 132 are formed in the first type of semiconductor layer 102, which are spaced apart along the first direction. The electrical connection 14 is arranged on the top surface of the doped region 13, wherein the electrical connection 14 is configured to connect the first doped region 131 at the first end A and connect the second doped region 132 at the second end B. Figure 7D represents the interval between the adjacent mask strips 12, and is also the window size for performing the ion implantation process. It should be noted that, in this case, it is required that D is as large as possible, so as to cover the diffusion width of different doses. W represents the diffusion width of the target test junction. In the case where D is known, by performing the ion implantation process on a plurality of target test structures, data related to the ion implantation dose, diffusion width and breakdown voltage of the target test structures are collected, so as to determine the first target test correlation between the ion implantation dose, diffusion width and breakdown voltage of different target test structures. The first target test correlation reflects the actual diffusion width of the target test junction under different actual dose conditions, so as to determine the actual ion implantation range, reduce the redundant repeated experiments and data analysis work in the subsequent device debugging process, and lay a foundation for the subsequent device design and research work.

[0075] The semiconductor structure obtained after steps S102-S108 can be referred to Figure 7 For the purpose of facilitating the understanding of the present application, Figure 7 An example of the semiconductor structure prepared by the preparation method of the present application can be provided, and other suitable examples of the semiconductor structure prepared by the present application can also be provided, which are not limited herein.

[0076] For the purpose of facilitating the understanding of the present application, Figure 8 The present application provides another preparation method of a semiconductor test structure, steps S202-S208.

[0077] Step S202: providing a substrate 10.

[0078] In some embodiments, the substrate 10 comprises a base 101 and a first-type semiconductor layer 102 located on the base 101; and the doped region 13 is a second-type doped region. The materials of the base 101 and the first-type semiconductor layer 102 are consistent with the foregoing description, which will not be described herein.

[0079] In some embodiments, the first type is P-type, and the second type is N-type; or the first type is N-type, and the second type is P-type. Different conductive types are used to form the target test junction to be tested.

[0080] Step S204: forming a plurality of mask strips on the top surface of the substrate, which are spaced apart along a first direction and extend along a second direction; the substrate between two adjacent mask strips is used to constitute an initial test region; two adjacent initial test regions are used to constitute an initial test structure; adjacent initial test structures are spaced apart along the first direction; the first direction and the second direction intersect and are parallel to the top surface of the substrate.

[0081] In some embodiments, step S204 further comprises:

[0082] Step S2042: forming a mask layer (not shown) on the top surface of the first-type semiconductor layer 102.

[0083] Step S2044: patterning the mask layer to obtain a plurality of mask strips 12 spaced apart along the first direction and extending along the second direction. The mask strips 12 are used as a mask plate for performing ion implantation process.

[0084] Step S206: performing ion implantation process on the initial test region at least with the plurality of mask strips 12 as a mask plate to obtain a target test structure including two doped regions 13, wherein the ion implantation energy and dose of different target test structures are the same and the target size is different; the target size is the interval between adjacent mask strips 12 along the first direction or the length of the mask strip 12 along the first direction.

[0085] Please refer to Figure 9 , specifically, when the same energy and the same dose of ion implantation, this structure can also simultaneously monitor the implantation diffusion width of multiple sizes by changing the interval between adjacent mask strips 12 or the length of the mask strip 12 along the first direction. D1 is used to represent the target size as the interval between adjacent mask strips along the first direction; D2 is used to represent the target size as the length of the mask strip 12 along the first direction; BV is used to represent the breakdown voltage (Breakdown voltage, BV).

[0086] Step S208: determining a second target test correlation between the target size, diffusion width and breakdown voltage of different target test structures according to the target size, diffusion width and breakdown voltage of the plurality of target test structures; the second target test correlation is used to determine the measured diffusion width of the target test junction to be tested according to the actual target size, actual breakdown voltage of the target test junction to be tested.

[0087] Please refer to Figure 10-11 , specifically, by adjusting the target size D1 or D2 of the target test structure, the ion implantation process on a plurality of target test structures with different target sizes is performed, and the data related to the implantation ion dose, diffusion width and breakdown voltage is collected to determine the second target test correlation between the target size, diffusion width and breakdown voltage of different target test structures. This method controls the target size, such as D1 or D2, of the target test structure as an adjustable variable on the basis of the original preparation method, achieves the purpose of simultaneously monitoring the ion implantation range corresponding to different implantation ion doses under multiple target sizes, widens the diversity of semiconductor test structures, and provides a theoretical basis for subsequent device regulation.

[0088] Please refer to Figure 12a-Figure 14bIn some embodiments, the target size is the spacing between adjacent mask strips 12 along the first direction; the minimum breakdown voltage (BVmin) and the maximum diffusion width (Wmax) are obtained when the target size is the maximum value and the adjacent doped regions are in contact; the maximum breakdown voltage (BVmax) and the minimum diffusion width (Wmin) are obtained when the target size is the minimum value; the maximum diffusion width (Wmax) and the minimum diffusion width (Wmin) are used to determine whether the measured diffusion width of the target test junction is abnormal.

[0089] Specifically, as shown in Figure 12a , D1 is the maximum value, representing that the window size of the ion implantation process can cover the diffusion width of the target test junction introduced by different doses. When the ion dose is such that the first doped region 131 and the second doped region 132 are in contact, the voltage value measured in this state is recorded as the minimum breakdown voltage (BVmin) and the maximum diffusion width (Wmax), Figure 12b is a schematic view of the structure in the plane formed by the first direction and the second direction.

[0090] As shown in Figure 13a , when D1 is the minimum value, the size of the doped region 13 along the first direction is substantially consistent with D1 after the ion implantation process is performed, and the voltage value measured in this state is recorded as the maximum breakdown voltage (BVmax) and the minimum diffusion width (Wmin). Figure 13b is a schematic view of the structure in the plane formed by the first direction and the second direction.

[0091] The normal diffusion width is as shown in Figure 14a , the breakdown voltage and the diffusion width are between the two extreme values described above, and the diffusion width is directly monitored according to the test results to determine whether it is within the expected range. If it is within the range, the second target test correlation is determined, and the actual target size, the actual breakdown voltage, and the measured diffusion width of the target test junction are determined according to the actual target size, the actual breakdown voltage, and the measured diffusion width of the target test junction. The actual diffusion range is checked for the difference from the expected value, and the device debugging efficiency is improved. Figure 14b is a schematic view of the structure in the plane formed by the first direction and the second direction.

[0092] Please refer to Figure 12a-Figure 14b , in some embodiments, the target size is the length of the mask strip 12 along the first direction; the minimum breakdown voltage (BVmin) and the maximum diffusion width (Wmax) are obtained when the target size is the minimum value and the adjacent doped regions are in contact; the maximum breakdown voltage (BVmin) and the minimum diffusion width (Wmin) are obtained when the target size is the maximum value; the maximum diffusion width (Wmax) and the minimum diffusion width (Wmin) are used to determine whether the measured diffusion width of the target test junction is abnormal.

[0093] For example, the specific implementation corresponding to the target size D2 is consistent with the target size D1, which is not repeated here.

[0094] The technical features of the above-described embodiments can be combined in any manner. To make the description concise, all possible combinations of the technical features of the above-described embodiments are not described, but as long as the combination of the technical features does not exist contradictory, it should be considered within the scope of the present disclosure.

[0095] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent scope of the application. It should be pointed out that for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

Claims

1. A method for preparing a semiconductor test structure, characterized in that: include: providing a substrate; forming a plurality of mask strips on the top surface of the substrate, which are spaced apart along a first direction and extend along a second direction; The substrate between two adjacent mask strips is used to form an initial test area; Two adjacent initial test areas are used to form an initial test structure; the adjacent initial test structures are spaced apart along the first direction; the first direction and the second direction intersect and are both parallel to the top surface of the substrate; Performing an ion implantation process on the initial test region using at least the plurality of mask strips as a mask to obtain a target test structure including two doped regions, wherein the implanted ions in different target test structures have the same energy and different doses; According to the implanted ion dose, diffusion width and breakdown voltage of the multiple target test structures, a first target test association relationship between the implanted ion dose, diffusion width and breakdown voltage of different target test structures is determined; the first target test association relationship is used to determine the measured diffusion width of the target test junction to be tested based on the actual implanted ion dose and actual breakdown voltage of the target test junction to be tested.

2. The method for preparing a semiconductor test structure according to claim 1, wherein: The substrate comprises a base and a first-type semiconductor layer located on the base; the doped region is a second-type doped region; Forming the plurality of mask strips on the top surface of the substrate comprises: forming a mask layer on the top surface of the first-type semiconductor layer; The mask layer is patterned to obtain a plurality of mask strips spaced apart along the first direction and extending along the second direction.

3. The method for preparing a semiconductor test structure according to claim 1, wherein: Performing an ion implantation process on the initial test region includes: forming an ion implantation mask over the initial test structure; The ion implantation mask and the plurality of mask strips are used as masks, and a self-alignment process is adopted to perform an ion implantation process on the initial test structure to obtain the plurality of target test structures.

4. The method for preparing a semiconductor test structure according to claim 2, wherein: The first type is P type, and the second type is N type; or The first type is N-type, and the second type is P-type.

5. The method for preparing a semiconductor test structure according to any one of claims 1 to 4, characterized in that: The spacing between adjacent mask strips is greater than or equal to a preset threshold.

6. A method for preparing a semiconductor test structure, characterized in that: include: providing a substrate; forming a plurality of mask strips on the top surface of the substrate, which are spaced apart along a first direction and extend along a second direction; The substrate between two adjacent mask strips is used to form an initial test area; Two adjacent initial test areas are used to form an initial test structure; Adjacent initial test structures are spaced apart and distributed along the first direction; the first direction and the second direction intersect and are both parallel to the top surface of the substrate; performing an ion implantation process into the initial test region using at least the plurality of mask strips as a mask to obtain a target test structure including two doped regions, wherein different target test structures have the same implanted ion energy and dose but different target sizes; the target size being the spacing between adjacent mask strips along the first direction; According to the target sizes, diffusion widths and breakdown voltages of the multiple target test structures, a second target test association relationship between the target sizes, diffusion widths and breakdown voltages of different target test structures is determined; the second target test association relationship is used to determine the measured diffusion width of the target test junction to be tested based on the actual target size and actual breakdown voltage of the target test junction to be tested.

7. The method for preparing a semiconductor test structure according to claim 6, wherein: The substrate comprises a base and a first-type semiconductor layer located on the base; the doped region is a second-type doped region; Forming the plurality of mask strips on the top surface of the substrate comprises: forming a mask layer on the top surface of the first-type semiconductor layer; The mask layer is patterned to obtain a plurality of mask strips spaced apart along the first direction and extending along the second direction.

8. The method for preparing a semiconductor test structure according to claim 7, wherein: The first type is P type, and the second type is N type; or The first type is N-type, and the second type is P-type.

9. The method for preparing a semiconductor test structure according to any one of claims 6 to 8, characterized in that: The target size is the spacing between adjacent mask strips along the first direction; When the target size is at a maximum value and adjacent doping regions are in contact, obtaining a minimum value of the breakdown voltage and a maximum value of the diffusion width; When the target size is at the minimum value, the maximum value of the breakdown voltage and the minimum value of the diffusion width are obtained; the maximum value of the diffusion width and the minimum value of the diffusion width are used to determine whether the measured diffusion width of the target test junction to be tested is abnormal.

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