Equalization circuit and continuous time linear equalizer

Abstract

The present application discloses an equalization circuit and a continuous time linear equalizer, which include: an input stage circuit, a feedback control circuit, a source degeneration circuit and a load circuit; the input stage circuit is coupled to the feedback control circuit, when the input signal at the signal input end is low frequency, the feedback control circuit is cut off, and the signal is amplified by the first transistor; when the frequency of the received signal increases, the feedback control circuit is turned on, and the signal is amplified by the first transistor and the second transistor; when the input signal is high frequency, the source degeneration circuit produces a source degeneration effect related to the frequency; the load circuit is composed of a feedback loop, which is used to realize the decoupling of the load parasitics and the input stage circuit parasitics; it is also used to receive the control voltage and provide the gain to the equalization circuit; the control voltage is used to adjust the gain effect provided by the load circuit. Through the present application, the multi-stage equalization function of the equalizer can be realized to adapt to the attenuation of different channels and compensate for the attenuation of the signal by different attenuation mechanisms.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to an equalization circuit and a continuous time linear equalizer. Background Art

[0002] Continuous Time Linear Equalizer (CTLE) is an equalization technology used in high-speed serial data communications. The CTLE circuit is usually located at the analog front end of the signal chain at the receiving end to pre-process the analog signal for subsequent digital signal processing. Its purpose is to compensate for signal distortion caused by the transmission medium. Especially in high-speed serial links, the CTLE attenuates low-frequency signal components and amplifies high-frequency signal components to compensate for the channel's attenuation of high-frequency signals, which can significantly improve the signal attenuation problem caused by channel characteristics.

[0003] However, the parasitic poles of the output nodes of the current continuous time linear equalizer based on source degeneration structure will limit the amount of gain improvement. Under high compensation intensity, the low-frequency gain will be deteriorated, the eye height of the output signal eye diagram will be compressed, and the level decision bit error rate will be increased, reducing the signal transmission quality. Summary of the invention

[0004] In order to solve the above technical problems, the present application provides an equalization circuit and a continuous time linear equalizer, which use complementary MOS tubes as the input stage, and use additional load circuits to generate gain on the basis of expanding the channel bandwidth, without increasing the parasitics of the output node, which helps to improve the overall link performance, reduce circuit bit errors, and adapt to a variety of different channel application scenarios. Specifically, the technical solution of the present application is as follows:

[0005] In a first aspect, the present application discloses an equalization circuit, comprising: an input stage circuit, a feedback control circuit, a source degeneration circuit, and a load circuit;

[0006] The input stage circuit is coupled to the feedback control circuit. When the input signal at the signal input end is of low frequency, the feedback control circuit is turned off, and the signal is amplified by the first transistor. When the frequency of the received signal increases, the feedback control circuit is turned on, and the signal is amplified by the first transistor and the second transistor.

[0007] When the input signal is high frequency, the source degeneration circuit generates a source degeneration effect related to the frequency;

[0008] The load circuit is composed of a feedback loop, which is used to achieve decoupling of load parasitics and input stage circuit parasitics; it is also used to receive a control voltage and provide gain to the equalization circuit; the control voltage is used to adjust the gain effect provided by the load circuit.

[0009] In some embodiments, the input stage circuit includes the first transistor and the second transistor, and the first transistor and the second transistor are complementary;

[0010] The feedback control circuit includes a switch tube, a feedback capacitor and a feedback resistor;

[0011] The second transistor is coupled to the signal input terminal through the switch tube and the feedback capacitor; the switch tube is connected to an enable signal for controlling the conduction state of the feedback path formed by the feedback capacitor and the feedback resistor;

[0012] The source degeneration circuit includes a source degeneration capacitor and a source degeneration resistor, which are connected in parallel with the source of the input stage circuit.

[0013] In some embodiments, when the input signal is high frequency, the source degeneration capacitor is considered as an open circuit;

[0014] When the input signal is high frequency, the impedance of the source degeneration capacitor decreases and is regarded as a short circuit, and the equalization circuit is converted into a source amplifier to amplify the signal; the source degeneration circuit provides gain for the high frequency signal.

[0015] In some embodiments, the feedback capacitor and the feedback resistor introduce a first zero point and a first pole into the equalization circuit;

[0016] The position of the first zero point is moved to a low frequency by adjusting the capacitance of the feedback capacitor, thereby obtaining a balancing effect at a low frequency;

[0017] By setting the capacitance of the feedback capacitor and the resistance of the feedback resistor, the positions of the first zero point and the first pole are adjusted to adjust the strength of low-frequency equalization;

[0018] The feedback capacitor is a variable capacitor; the feedback resistor is a variable resistor.

[0019] In some embodiments, the position of the first pole is half the position of the first zero.

[0020] In some embodiments, the load circuit introduces a second zero and a second pole;

[0021] By setting the capacitance of the source degeneration capacitor and the resistance of the source degeneration resistor, the positions of the second zero point and the second pole are adjusted to achieve the adjustment of the high-frequency boost effect;

[0022] The source degeneration capacitor is a variable capacitor; the source degeneration resistor is a variable resistor.

[0023] In some implementations, the balancing circuit further includes a bias circuit, and the bias circuit includes a plurality of current mirrors for providing a bias current.

[0024] In some embodiments, the load circuit includes: a control signal receiving terminal, a feedback transistor, and a cascode transistor;

[0025] The gate of the feedback transistor is the control signal receiving end, the source is connected to the input stage circuit, and the drain is connected to the voltage output end;

[0026] The cascode transistors are connected in parallel at both ends of the source and drain of the feedback transistor to improve circuit stability.

[0027] In some implementations, the control signal receiving end is used to receive the control voltage, and the control voltage is used to control the conduction state of the feedback transistor to adjust the gain.

[0028] In other embodiments, the feedback transistor is also used to receive a dynamic current from a previous stage circuit, and the gain provided by the load circuit is related to the equivalent on-resistance of the feedback transistor and has nothing to do with the bias state of the previous stage circuit.

[0029] In some embodiments, the first transistor M1 is a PMOS, whose gate is connected to the positive input voltage, whose drain is connected to the drain of the second transistor M3, and whose source is connected to the source degradation circuit; the second transistor M3 is an NMOS, whose source is connected to the power supply voltage VDD, and whose gate is connected to the drain of the switch tube M5; the first transistor M1 and the second transistor M3 are complementary;

[0030] The first transistor M2 is a PMOS, a gate of which is connected to a negative input voltage, a drain of which is connected to a drain of the second transistor M4, and a source of which is connected to the source degeneration circuit; the second transistor M4 is an NMOS, a source of which is connected to a power supply voltage VDD, and a gate of which is connected to a drain of the switch tube M6; the first transistor M2 and the second transistor M4 are complementary.

[0031] In some embodiments, the switch tube M5 is a PMOS, whose gate is connected to the enable signal, the source is connected to one end of the feedback capacitor Cf1, and the drain is connected to one end of the feedback resistor Rf1; the other end of the feedback capacitor Cf1 is connected to the gate of the first transistor M1; the other end of the feedback resistor Rf1 is connected to the reference voltage;

[0032] The switch tube M6 is a PMOS, whose gate is connected to the enable signal, the source is connected to one end of the feedback capacitor Cf2, and the drain is connected to one end of the feedback resistor Rf2; the other end of the feedback capacitor Cf2 is connected to the gate of the first transistor M2; the other end of the feedback resistor Rf2 is connected to the reference voltage;

[0033] The enable signal is used to control the switch tube.

[0034] In a second aspect, the present application further discloses a continuous time linear equalizer, which includes at least one equalization circuit described in any one of the above embodiments.

[0035] Compared with the prior art, the present invention has at least one of the following beneficial effects:

[0036] 1. The equalization circuit design of this application can achieve the technical effect of compensating the low-frequency and high-frequency bands of the signal respectively. The multi-band equalization function of the equalizer is realized to adapt to the attenuation of different channels and compensate for the attenuation of the signal by different attenuation mechanisms without increasing the extra circuit power consumption. In the low-frequency band of the signal, the passive structure is integrated for compensation; in the high-frequency band of the signal, the source degeneration resistor and capacitor network are used to construct zero poles to obtain high-frequency equalization capability.

[0037] 2. The equalization circuit designed in this application can achieve higher gain and circuit driving capability, and provide a certain circuit gain on the basis of expanding the path bandwidth to meet the input requirements of the subsequent circuit and improve the overall link performance. This solves the problem that traditional solutions cannot take into account both bandwidth and circuit gain.

[0038] 3. Using a transimpedance circuit as a load allows the circuit to work in a low voltage state while still meeting the requirements of a larger output swing. By adding a resistor and capacitor network at different nodes of the circuit, the function of integrating adjustable equalization strength in different frequency bands without increasing the power consumption of the circuit can help reduce circuit bit errors and adapt to a variety of different channel application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The preferred implementation scheme will be described below in a clear and understandable manner with reference to the accompanying drawings to further illustrate the above-mentioned characteristics, technical features, advantages and implementation methods of the present application.

[0040] Figure 1 A continuous time linear equalizer based on a source degeneration structure commonly used in the prior art is shown;

[0041] Figure 2 A circuit connection diagram showing an input stage circuit and a feedback control circuit in an embodiment of the equalization circuit of the present application is shown;

[0042] Figure 3 A circuit connection diagram of a source degeneration circuit in another embodiment of the equalization circuit of the present application is shown;

[0043] Figure 4 A schematic diagram showing the structure of a load circuit in another embodiment of the balancing circuit of the present application is shown;

[0044] Figure 5 A structural schematic diagram of another embodiment of the equalization circuit of the present application is shown. DETAILED DESCRIPTION

[0045] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0046] It should be understood that when used in this specification and the appended claims, the term "comprising" indicates the presence of the described features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or collections.

[0047] In order to simplify the drawings, only the parts related to the invention are schematically shown in each figure, and they do not represent the actual structure of the product. In addition, in order to simplify the drawings and facilitate understanding, in some figures, only one of the parts with the same structure or function is schematically drawn or marked. In this article, "one" not only means "only one", but also means "more than one".

[0048] It should be further understood that the term “and / or” used in the specification and appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0049] In this document, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0050] In a specific implementation, the terminal device described in the embodiments of the present application includes, but is not limited to, other portable devices such as mobile phones, laptop computers, tutoring machines, or tablet computers with touch-sensitive surfaces (e.g., touch screen displays and / or touch pads). It should also be understood that in some embodiments, the terminal device is not a portable communication device, but a desktop computer with a touch-sensitive surface (e.g., touch screen displays and / or touch pads).

[0051] In addition, in the description of the present application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0052] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the specific implementation methods of the present application will be described below with reference to the accompanying drawings. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings and other implementation methods can be obtained based on these drawings without creative work.

[0053] With the rapid development of cloud computing, the Internet of Things, and 5G communication technologies, the amount of data in global data centers has increased dramatically, and improving data transmission speed and reducing energy consumption have become research hotspots. Serializer / Deserializer (SerDes) technology has attracted widespread attention due to its application in high-speed serial data communications. Receivers based on analog-to-digital converters (ADCs) and digital signal processing (DSPs) have been widely used in the field of high-speed communications due to their excellent noise resistance and channel attenuation compensation capabilities. This type of receiver is mainly composed of four parts: analog front end, clock interleaved ADC, digital signal processing, and clock path.

[0054] As an important equalization method in analog front-end circuits, continuous time linear equalizers are widely used in the field of signal communication. The impact of the channel on the signal can be divided into two categories. On the one hand, the signal is corrupted by noise, resulting in a decrease in the signal-to-noise ratio and timing jitter; these two effects are compensated in the clock and data recovery circuit. On the other hand, the limited channel bandwidth causes the transition of the data stream to lose sharpness due to the attenuation of the high-frequency components. This also increases the inter-symbol interference, thereby reducing the opening of the eye diagram and increasing the bit error rate. The transition between different code elements takes longer to complete, which causes the value of each bit of information to be affected by its adjacent code elements. The continuous time linear equalizer is a technology widely used to compensate for the loss of high-frequency components of the channel, which can effectively reduce the bit error rate of the transmission link and achieve high-quality signal transmission.

[0055] The current technical solution is a continuous time linear equalizer based on a source degeneration structure. It is an improved form of the source degeneration structure, which amplifies high-frequency signals by introducing a parallel resistor and capacitor pair at the source of the MOS tube. At low frequencies, the parallel capacitor can be regarded as an open circuit, and the circuit is a traditional source degeneration structure. At high frequencies, the impedance of the parallel capacitor gradually decreases, and in an ideal state it can be regarded as a short circuit. At this time, the circuit is converted into a source amplifier to amplify the signal and output it. Figure 1 , Figure 1 A continuous time linear equalizer based on a source degeneration structure commonly used in the prior art is shown.

[0056] For high-speed applications, after a certain optimal bias, simply increasing the bias current of the source degenerate differential pair circuit does not significantly improve the gain of the circuit, because after increasing the bias current, the output impedance of the differential pair will also decrease. Therefore, even with a larger current, sufficient gain cannot be obtained. Moreover, in applications with low power supply voltage, increasing the size of the device to meet the current capacity will also introduce a larger parasitic capacitance, which is very unfavorable to the bandwidth. In high-speed applications, the attenuation of different frequencies of the signal is affected by different mechanisms. The circuit structure in the prior art cannot perfectly compensate for the attenuation of the channel, thereby increasing the bit error rate of the transmission system.

[0057] therefore, Figure 1 The performance of the continuous-time linear equalizer based on the source degeneration structure shown is increasingly difficult to meet the requirements in terms of bandwidth and gain.

[0058] In order to solve this technical problem, the present application provides an equalization circuit. On the basis of expanding the path bandwidth, a certain circuit gain is provided to meet the input requirements of the subsequent circuit and improve the overall link performance. By adding a resistor and capacitor network at different nodes of the circuit, the function of adjustable equalization strength in different frequency bands is integrated without additionally increasing the power consumption of the circuit, which helps to reduce circuit bit errors and adapt to the application scenarios of various different channels.

[0059] An embodiment of an equalization circuit of the present application includes: an input stage circuit, a feedback control circuit, a source degeneration circuit and a load circuit.

[0060] The input stage circuit is coupled to the feedback control circuit. When the input signal at the signal input end is low frequency, the feedback control circuit is turned off, and the signal is amplified by the first transistor. When the frequency of the received signal increases, the feedback control circuit is turned on, and the signal is amplified by the first transistor and the second transistor.

[0061] When the input signal is high frequency, the source degeneration circuit generates a frequency-dependent source degeneration effect.

[0062] The equalization circuit designed in this application has the ability to compensate for the low-frequency and high-frequency bands of the signal respectively. The main loss mechanism in the low-frequency band is the skin effect, which belongs to resistive loss. It is a suitable choice to integrate passive structures in the circuit for compensation. The high-frequency equalization adopts a solution similar to the prior art, using source degeneration resistors and capacitor networks to construct zero-pole pairs to obtain high-frequency equalization capabilities. However, the difference is that in order to solve the problem of insufficient gain in the prior art, an additional load circuit is used to generate gain without increasing the parasitics of the output node.

[0063] In one implementation of this embodiment, the input stage circuit includes the first transistor and the second transistor, and the first transistor and the second transistor are complementary.

[0064] The feedback control circuit includes a switch tube, a feedback capacitor and a feedback resistor.

[0065] The second transistor is coupled to the signal input terminal through the switch tube and the feedback capacitor. The switch tube is connected to an enable signal for controlling the conduction state of a feedback path formed by the feedback capacitor and the feedback resistor.

[0066] In another implementation of this embodiment, refer to the attached specification. Figure 2 As stated, Figure 2 FIG. 1 is a schematic diagram showing the circuit connection between the input stage circuit and the feedback control circuit in this embodiment. Compared with the prior art circuit using NMOS transistors as the input stage, the present application uses complementary MOS transistors M1 / M3 and M2 / M4 as the input stage circuit. Figure 2 As shown in the dotted circle. Complementary MOS tubes, that is, NMOS (n-type MOSFET) and PMOS (p-type MOSFET) used in CMOS (Complementary Metal-Oxide-Semiconductor) technology complement each other. CMOS circuits can operate in a wider range of power supply voltage VDD, which makes CMOS convenient as an interface to other circuits.

[0067] The first transistor M1 is a PMOS, with a gate connected to a positive input voltage Vin+, a drain connected to a drain of the second transistor M3, and a source connected to the source degeneration circuit. The second transistor M3 is an NMOS, with a source connected to a power supply voltage VDD, and a gate connected to a drain of the switch tube M5. The first transistor M1 and the second transistor M3 are complementary.

[0068] The first transistor M2 is a PMOS, whose gate is connected to the negative input voltage Vin-, whose drain is connected to the drain of the second transistor M4, and whose source is connected to the source degradation circuit. The second transistor M4 is an NMOS, whose source is connected to the power supply voltage VDD, and whose gate is connected to the drain of the switch tube M6. The first transistor M2 and the second transistor M4 are complementary.

[0069] The feedback control circuit includes switch tubes M5, M6, feedback capacitor Rf and feedback resistor Cf. The switch tube M5 is a PMOS, whose gate is connected to the enable signal en, the source is connected to one end of the feedback capacitor Cf1, and the drain is connected to one end of the feedback resistor Rf1. The other end of the feedback capacitor Cf1 is connected to the gate of the first transistor M1. The other end of the feedback resistor Rf1 is connected to the reference voltage Vref.

[0070] The switch tube M6 is a PMOS, with a gate connected to the enable signal en, a source connected to one end of the feedback capacitor Cf2, and a drain connected to one end of the feedback resistor Rf2. The other end of the feedback capacitor Cf2 is connected to the gate of the first transistor M2. The other end of the feedback resistor Rf2 is connected to the reference voltage Vref.

[0071] The enable signal en is used to control the switch tubes, so that the switch tubes M5 and M6 control whether the feedback path formed by Rf and Cf is turned on.

[0072] Reference voltage Vref is used to provide a known voltage level in a circuit as a comparison or reference. In analog circuits, Vref is often used to set the operating point of an amplifier or as a threshold for logic levels in digital circuits.

[0073] Another embodiment of an equalizing circuit of the present application, based on the above embodiment of an equalizing circuit, the feedback capacitor and the feedback resistor introduce a first zero point and a first pole into the equalizing circuit.

[0074] The position of the first zero point is moved to a low frequency by adjusting the capacitance of the feedback capacitor, thereby obtaining a balancing effect at a low frequency.

[0075] By setting the capacitance of the feedback capacitor and the resistance of the feedback resistor, the positions of the first zero point and the first pole are adjusted to adjust the strength of low-frequency equalization.

[0076] Optionally, the feedback capacitor Cf is a variable capacitor, and the feedback resistor Rf is a variable resistor.

[0077] In the RC feedback circuit, the zero point is the solution where the numerator polynomial of the transfer function is equal to zero, that is, at these frequency points, the output signal of the system is zero, while the input signal is not zero. The pole is the solution where the denominator polynomial of the transfer function is equal to zero, that is, at these frequency points, the output signal of the system is infinite, while the input signal is not zero. By adjusting the position of the zero and pole, the circuit can be designed to meet the specific frequency response requirements.

[0078] The equalization circuit designed in this application can not only provide higher high-frequency equalization capability, but also move the equalization frequency band to low frequency to achieve multi-band equalization by adjusting the value of the resistor and capacitor array. Figure 2 As shown, the M3 / M4 tube is coupled to the input end through the switch tube M5 / M6 and the feedback capacitor Cf. In the long channel application scenario, the switch tube M5 / M6 is turned on, and the high-frequency component of the signal is loaded to the M3 / M4 tube through the feedback capacitor Cf for further amplification.

[0079] Specifically, for the convenience of calculation, we assume that the transconductance of M1 / M2 and M3 / M4 is equal and written as gm. If the source degeneration resistance and capacitance in the circuit are not considered, because the input signal of M3 comes from the voltage division of the capacitor and the resistor, the equivalent transconductance of the circuit can be written as:

[0080] .

[0081] Among them, GM1 is the equivalent transconductance of the circuit, gm1 and gm3 are the transconductances of M1 and M3 tubes respectively, and Cf and Rf are the feedback capacitance and resistance values ​​in the circuit respectively. It can be concluded from the formula that at low frequencies, only M1 tube participates in signal amplification in the circuit. As the frequency increases, the capacitor feedback path gradually conducts, and M1 and M3 tubes are added to the circuit at the same time to produce an amplification effect. The balancing effect at low frequencies can be obtained by adjusting the capacitance of the feedback capacitor network.

[0082] Preferably, the position of the first pole is half of the position of the first zero point.

[0083] Specifically, the values ​​of the feedback resistor and capacitor are relatively large, and through parameter design, the pole position introduced by the feedback resistor and capacitor is made to be approximately half of the zero point, thereby achieving the adjustment of the low-frequency equalization strength.

[0084] Another embodiment of the equalization circuit of the present application is shown in the attached specification. Figure 3 As shown, based on an embodiment of the above-mentioned equalization circuit, the source degeneration circuit includes a source degeneration capacitor and a source degeneration resistor, which are connected in parallel with the source of the input stage circuit.

[0085] Figure 3 The RC circuit in the dotted circle is the source degeneration circuit.

[0086] When the input signal is high frequency, the source degeneration capacitor is regarded as an open circuit.

[0087] When the input signal is high frequency, the impedance of the source degeneration capacitor decreases and is regarded as a short circuit, and the equalization circuit is converted into a source amplifier to amplify the signal. The source degeneration circuit provides gain for high frequency signals.

[0088] Specifically, the high-frequency gain of the circuit is still similar to the gain realization form of the traditional source degeneration structure, and can be realized relatively simply by connecting a resistor and capacitor pair in parallel to the source of M1 and M2 to produce a frequency-dependent source degeneration effect. The transconductance at this time can be written as:

[0089] ;

[0090] After simplification, we can get:

[0091] .

[0092] Here, GM1 is the equivalent transconductance of the circuit composed of M1, M3, Cf, and Rf. GM2 is the total equivalent transconductance of the circuit after adding the influence of Rs and Cs. Cs and Rs are the capacitance and resistance of the source degeneration capacitor and the source degeneration resistor in the circuit, respectively.

[0093] Substituting GM1 into the expression of GM2 and simplifying it, we can get the equivalent transconductance of the circuit, which can reflect the location of the zero and pole of the circuit. The equivalent transconductance multiplied by the load provided by the load circuit can get the transfer function of the circuit.

[0094] Another embodiment of an equalization circuit of the present application is shown in the attached specification. Figure 4 As shown, based on an embodiment of the above-mentioned balancing circuit, the load circuit introduces a second zero point and a second pole.

[0095] By setting the capacitance of the source degeneration capacitor and the resistance of the source degeneration resistor, the positions of the second zero point and the second pole are adjusted to achieve the adjustment of the high-frequency boost effect.

[0096] Optionally, the source degeneration capacitor is a variable capacitor, and the source degeneration resistor is a variable resistor.

[0097] Preferably, the source degeneration capacitor is a variable capacitor array. The source degeneration resistor is a variable resistor array. The capacitor array can be adjusted to adjust the position of the zero pole in the circuit to obtain high-frequency boost effects of different magnitudes.

[0098] In one implementation of this embodiment, the load circuit includes: a control signal receiving end, a feedback transistor, and a cascode transistor.

[0099] The gate of the feedback transistor is the control signal receiving end, the source is connected to the input stage circuit, and the drain is connected to the voltage output end.

[0100] The cascode transistors are connected in parallel at both ends of the source and drain of the feedback transistor to improve circuit stability.

[0101] Specifically, the cascode structure can reduce the influence of the channel length modulation effect on the current replication accuracy. In a simple current mirror, due to the channel length modulation effect, when the power supply voltage VDDVDD changes, the replicated current will also change, resulting in a decrease in the current replication accuracy. The cascode structure can suppress this effect by adding a common gate transistor, thereby improving the accuracy of current replication.

[0102] In another implementation of this embodiment, refer to the attached specification. Figure 4 , Figure 4 The schematic diagram of the structure of the load circuit in one embodiment of the present application is shown. Among them, M7, M8, M17, and M18 are current mirror tubes that provide bias current for the circuit. M11 is a feedback MOS tube of the transimpedance circuit, which works in the linear region. M13 and M14 are common source and common gate tubes to ensure the accuracy of the current mirror when copying the current.

[0103] Specifically, the load circuit is composed of a feedback loop, and the input and output impedances of the circuit are very small, approximately the inverse of the transconductance. Not only can the subsequent large load circuit be decoupled from the transconductance stage circuit and the output bandwidth of the circuit be expanded, but it also provides greater driving capability to drive the subsequent sampling circuit. The conduction state of the feedback MOS tube M11 can be adjusted by controlling the voltage Vf to adjust different gains. The feedback MOS tube M11 receives the dynamic current Iin from the previous stage. The gain of the circuit is related to the equivalent on-resistance of the feedback MOS tube, and has nothing to do with the bias state of the previous stage circuit. The output voltage Vout=Iin*R M11 This makes up for the disadvantages of the traditional source degeneration structure used in the prior art.

[0104] Another embodiment of the equalization circuit of the present application is shown in the attached specification. Figure 5 As shown, Figure 5 This is a schematic diagram of the structure of another embodiment of the equalization circuit of the present application. A load circuit is added on both sides of the input stage circuit and the feedback control circuit.

[0105] Figure 5The load circuit on the left is the same as described in the previous embodiment. In the load circuit on the right, M9, M10, M22, and M23 are current mirror tubes that provide bias current for the circuit. M12 is a feedback MOS tube of the transimpedance circuit, which works in the linear region. M15 and M16 are common source and common gate tubes to ensure the accuracy of the current mirror when copying the current. The working principle of the load circuit is the same, and this embodiment will not be repeated.

[0106] Optionally, the equalization circuit further includes a bias circuit, and the bias circuit includes a plurality of current mirrors for providing a bias current. Figure 3 On the basis of, M19, M20, and M21 are added after the source degeneration circuit. In this application, complementary MOS tubes M1 / M3 and M2 / M4 are used as the input stage. M5-6 are switch tubes, which control whether the feedback path composed of Rf and Cf is turned on. Rs and Cs are source degeneration resistors and capacitors, which achieve the gain effect on the high-frequency part. M7-10, M17-23 are current mirror tubes that provide bias current for the circuit. M11-12 is the feedback path of the transimpedance circuit, which works in the linear region. M13-M16 are common source and common gate tubes to ensure the accuracy of the current mirror when copying the current.

[0107] The present application integrates the ability to balance the attenuation of different signal frequency bands in the circuit through the design of feedback resistors and capacitors, and uses the implementation form of the load circuit to complete the decoupling of load parasitics and input circuit parasitics, achieving both high gain and large bandwidth.

[0108] Based on the same technical concept, the present application also discloses a continuous time linear equalizer, which includes at least one equalization circuit described in any one of the above embodiments.

[0109] An equalization circuit and a continuous-time linear equalizer of the present application have the same technical concept, and the technical details of the embodiments of the two are applicable to each other. To reduce repetition, they will not be described again.

[0110] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, only the division of the above-mentioned program modules is used as an example for illustration. In actual applications, the above-mentioned functions can be assigned to different program modules as needed, that is, the internal structure of the device can be divided into different program units or modules to complete all or part of the functions described above. The program modules in the embodiment can be integrated into a processing unit, or each unit can exist physically separately, or two or more units can be integrated into a processing unit, and the above-mentioned integrated unit can be implemented in the form of hardware or in the form of software program units. In addition, the specific names of the program modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application.

[0111] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

Claims

1. An equalization circuit, characterized in that: include: Input stage circuit, feedback control circuit, source degeneration circuit and load circuit; The input stage circuit is coupled to the feedback control circuit. When the input signal at the signal input end is of low frequency, the feedback control circuit is turned off, and the signal is amplified by the first transistor. When the frequency of the received signal increases, the feedback control circuit is turned on, and the signal is amplified by the first transistor and the second transistor. When the input signal is high frequency, the source degeneration circuit generates a source degeneration effect related to the frequency; The load circuit is composed of a feedback loop, and is used to achieve decoupling of load parasitics and input stage circuit parasitics; it is also used to receive a control voltage and provide a gain to the equalization circuit; the control voltage is used to adjust the gain effect provided by the load circuit; Wherein, the input stage circuit comprises the first transistor and the second transistor, and the first transistor and the second transistor are complementary; The feedback control circuit includes a switch tube, a feedback capacitor and a feedback resistor; The gate of the first transistor is a signal input terminal, and the second transistor is coupled to the signal input terminal through the switch tube and the feedback capacitor; the second transistor is also coupled to a reference voltage Vref through the feedback resistor; the switch tube is connected to an enable signal for controlling the conduction state of a feedback path formed by the feedback capacitor and the feedback resistor; The source degeneration circuit includes a source degeneration capacitor and a source degeneration resistor, and is connected to the source of the first transistor in the input stage circuit; The load circuit comprises: a control signal receiving end, a feedback transistor, and a cascode transistor; The gate of the feedback transistor is the control signal receiving end, the source is connected to the input stage circuit, and the drain is connected to the voltage output end; The cascode transistor is connected in parallel at both ends of the source and drain of the feedback transistor to improve circuit stability; The control signal receiving end is used to receive the control voltage, and the control voltage is used to control the conduction state of the feedback transistor to adjust the gain.

2. The equalization circuit according to claim 1, characterized in that: When the input signal is high frequency, the source degeneration capacitor is regarded as an open circuit; When the input signal is high frequency, the impedance of the source degeneration capacitor decreases and is regarded as a short circuit, and the equalization circuit is converted into a source amplifier to amplify the signal; the source degeneration circuit provides gain for the high frequency signal.

3. The equalizing circuit according to claim 1, characterized in that: The feedback capacitor and the feedback resistor introduce a first zero point and a first pole into the equalization circuit; The position of the first zero point is moved to a low frequency by adjusting the capacitance of the feedback capacitor, thereby obtaining a balancing effect at a low frequency; By setting the capacitance of the feedback capacitor and the resistance of the feedback resistor, the positions of the first zero point and the first pole are adjusted to adjust the strength of low-frequency equalization; The feedback capacitor is a variable capacitor; the feedback resistor is a variable resistor.

4. An equalizing circuit as claimed in claim 3, characterized in that: The position of the first pole is half the position of the first zero.

5. The equalizing circuit according to claim 1, characterized in that: The load circuit introduces a second zero point and a second pole; By setting the capacitance of the source degeneration capacitor and the resistance of the source degeneration resistor, the positions of the second zero point and the second pole are adjusted to achieve the adjustment of the high-frequency boost effect; The source degeneration capacitor is a variable capacitor; the source degeneration resistor is a variable resistor.

6. An equalizing circuit according to any one of claims 1 to 5, characterized in that: A bias circuit is also included, and the bias circuit includes a plurality of current mirrors for providing a bias current.

7. The equalizing circuit according to claim 1, characterized in that: The feedback transistor is also used to receive a dynamic current from a preceding circuit. The gain provided by the load circuit is related to the equivalent on-resistance of the feedback transistor and has nothing to do with the bias state of the preceding circuit.

8. The equalizing circuit according to claim 1, characterized in that: The first transistor M1 is a PMOS, with a gate connected to a positive input voltage, a drain connected to a drain of the second transistor M3, and a source connected to the source degeneration circuit; the second transistor M3 is an NMOS, with a source connected to a power supply voltage, and a gate connected to a drain of the switch tube M5; the first transistor M1 and the second transistor M3 are complementary; The first transistor M2 is a PMOS, a gate of which is connected to a negative input voltage, a drain of which is connected to a drain of the second transistor M4, and a source of which is connected to the source degeneration circuit; the second transistor M4 is an NMOS, a source of which is connected to a power supply voltage, and a gate of which is connected to a drain of the switch tube M6; the first transistor M2 and the second transistor M4 are complementary.

9. The equalizing circuit according to claim 1, characterized in that: The switch tube M5 is a PMOS, whose gate is connected to the enable signal, the source is connected to one end of the feedback capacitor Cf1, and the drain is connected to one end of the feedback resistor Rf1; the other end of the feedback capacitor Cf1 is connected to the gate of the first transistor M1; the other end of the feedback resistor Rf1 is connected to the reference voltage; The switch tube M6 is a PMOS, whose gate is connected to the enable signal, the source is connected to one end of the feedback capacitor Cf2, and the drain is connected to one end of the feedback resistor Rf2; the other end of the feedback capacitor Cf2 is connected to the gate of the first transistor M2; the other end of the feedback resistor Rf2 is connected to the reference voltage; The enable signal is used to control the switch tube.

10. A continuous time linear equalizer, characterized in that: At least comprising an equalizing circuit as described in any one of claims 1-9.

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