Clock signal control circuit and switching power supply

Abstract

The embodiments of the present disclosure provide a control circuit of a clock signal and a switching power supply. The control circuit of the clock signal includes: a frequency hopping control circuit for generating a first comparison voltage and a second comparison voltage based on an output error voltage of the switching power supply, and generating a frequency hopping signal according to a comparison result between the first comparison voltage and the second comparison voltage; an oscillator logic control circuit for generating a frequency hopping enable signal, and when the frequency hopping signal is a valid signal, controlling the clock signal to stop outputting, and when the frequency hopping signal is an invalid signal, controlling the clock signal to output; the frequency hopping control circuit for comparing the first comparison voltage with the second comparison voltage when the frequency hopping enable signal is a low level, and when the first comparison voltage is equal to the second comparison voltage, the generated frequency hopping signal is an invalid signal, and when the first comparison voltage is greater than the second comparison voltage, the generated frequency hopping signal is a valid signal.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of integrated circuits, and in particular to a clock signal control circuit and a switching power supply. Background Art

[0002] PCM (peak current mode) BUCK control is a dual-loop system that controls both output voltage and peak current. Figure 1 As shown in the schematic diagram of the PCM BUCK circuit 100, the output voltage V OUT The feedback voltage V FB With reference voltage V REF The output error voltage Vcomp is obtained after passing through the error amplifier EA. The output error voltage Vcomp is proportional to the peak current i of the sampled upper power tube HS. L The voltage V SENSE The comparison is made through the comparator PWM, and the high level is output as the shutdown logic signal of the upper power tube HS, while the rising edge of the clock signal CLK is used as the start logic signal of the upper power tube HS. The switching time of the upper power tube HS and the lower power tube LS is controlled by the logic circuit LOGIC to maintain the stability of the output voltage and output current. Among them, according to the different load currents, the PCM BUCK circuit has two working modes, namely CCM (Continuous Conduction Mode) and DCM (Discontinuous Conduction Mode). When the load current gradually decreases, the output voltage V OUT As the output error voltage Vcomp decreases, the output error voltage Vcomp decreases. When the output error voltage Vcomp decreases to a certain value, the frequency hopping control circuit Skip is triggered. This circuit is used to control the output of the clock signal CLK to achieve frequency reduction. Figure 2 As shown in the waveform diagram, when the PCM BUCK circuit works in CCM, when the rising edge of the clock signal CLK arrives, the upper power tube HS is turned on, and the inductor current I L When the inductor current I L When the peak current Ipeak is reached, the comparator PWM outputs a high-level signal to turn off the upper power tube HS and turn on the lower power tube LS. The inductor current I L When the PCM BUCK circuit works in DCM, the inductor current I LAfter falling to 0, the lower power tube LS is turned off, because the upper power tube HS cannot be turned on again until the next clock signal CLK arrives, so in a clock cycle T, both the upper power tube HS and the lower power tube LS are turned off, during which the load current is provided by the output capacitor Cout. Figure 3 As shown in FIG. 1 , when the load current decreases to a certain value, the PCM BUCK circuit enters a light-load frequency reduction operation mode, triggering the frequency hopping control circuit Skip, which controls the oscillator circuit Oscillator to select a clock signal CLK that skips several cycles, which is called pulse skip modulation (PSM).

[0003] When the existing PCM BUCK circuit is working under light load, it will generally switch to PSM mode, and can skip several cycles of the clock signal CLK to ensure small output ripple and high efficiency. Generally, the mode switching is achieved by comparing the output error voltage Vcomp with a fixed voltage Vr. However, when the switching frequency of the PCM BUCK circuit is very high, the output error voltage Vcomp reacts slowly, delaying the control signal output by the frequency hopping control circuit Skip, causing the circuit to output two or more clock signals CLK at a time, resulting in the upper power tube HS being turned on twice or more, such as Figure 4 As shown, this phenomenon is called double pulse or group pulse, which causes the ripple of the output voltage Vout to be larger and the efficiency to be reduced. Summary of the invention

[0004] The purpose of the embodiments of the present disclosure is to provide a clock signal control circuit and a switching power supply, which control the frequency hopping signal through a frequency hopping enable signal, so that each clock signal has a relatively long and identical time interval, thereby improving the efficiency of light load operation and avoiding the problem of double pulses or group pulses.

[0005] In order to achieve the above-mentioned purpose, the first aspect of the embodiment of the present disclosure provides a clock signal control circuit, which is applied to a switching power supply, and includes: a frequency hopping control circuit and an oscillator logic control circuit. The frequency hopping control circuit is configured to generate a first comparison voltage and a second comparison voltage based on the output error voltage of the switching power supply, and generate a frequency hopping signal according to the comparison result of the first comparison voltage and the second comparison voltage; the oscillator logic control circuit is configured to generate a frequency hopping enable signal, and when the frequency hopping signal is a valid signal, control the clock signal to stop output, and when the frequency hopping signal is an invalid signal, control the clock signal to output; the frequency hopping control circuit is also configured to compare the first comparison voltage and the second comparison voltage when the frequency hopping enable signal is a low level, and when the first comparison voltage is equal to the second comparison voltage, the generated frequency hopping signal is an invalid signal, and when the first comparison voltage is greater than the second comparison voltage, the generated frequency hopping signal is a valid signal.

[0006] In some embodiments of the present disclosure, the frequency hopping control circuit includes: a first current generating circuit, a first comparison voltage generating circuit, a second comparison voltage generating circuit and a comparison circuit. The first current generating circuit is configured to generate a first current signal based on the output error voltage of the switching power supply; the first comparison voltage generating circuit is configured to generate the first comparison voltage based on the first mirror signal of the first current signal; the second comparison voltage generating circuit is configured to generate the second comparison voltage based on the second mirror signal of the first current signal, the mirror signal of the second current signal and the frequency hopping enable signal; the comparison circuit is configured to generate the frequency hopping signal according to the comparison result of the first comparison voltage and the second comparison voltage.

[0007] In some embodiments of the present disclosure, the oscillator logic control circuit includes: a periodic signal generating circuit and a clock signal generating circuit. The periodic signal generating circuit is configured to generate a periodic signal according to a comparison result between an oscillator reference voltage and a ramp voltage; and the clock signal generating circuit is configured to generate the frequency hopping enable signal and the clock signal according to the periodic signal and the frequency hopping signal.

[0008] In some embodiments of the present disclosure, the first current generating circuit includes: a first transistor, a second transistor, a third transistor and a first current source. The first electrode of the first transistor is coupled to the first voltage terminal, the control electrode of the first transistor is coupled to the second electrode of the first transistor, the second electrode of the second transistor and the output terminal of the first current generating circuit; the first electrode of the second transistor is coupled to the control electrode of the third transistor and the output error voltage output terminal of the switching power supply, the control electrode of the second transistor is coupled to the second terminal of the first current source and the second electrode of the third transistor; the first electrode of the third transistor is coupled to the second voltage terminal; and the first terminal of the first current source is coupled to the first voltage terminal.

[0009] In some embodiments of the present disclosure, the first comparison voltage generating circuit includes: a fourth transistor and a first resistor. The control electrode of the fourth transistor is coupled to the output end of the first current generating circuit, the first electrode of the fourth transistor is coupled to the first voltage end, the second electrode of the fourth transistor is coupled to the first end of the first resistor and the output end of the first comparison voltage generating circuit; and the second end of the first resistor is coupled to the second voltage end.

[0010] In some embodiments of the present disclosure, the second comparison voltage generating circuit includes: a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a second current source, and a first capacitor. The control electrode of the fifth transistor is coupled to the output end of the first current generating circuit, the first electrode of the fifth transistor is coupled to the first voltage end, the second electrode of the fifth transistor is coupled to the first end of the second current source, the control electrode of the sixth transistor, the second electrode of the sixth transistor, and the control electrode of the seventh transistor; the first electrode of the sixth transistor is coupled to the first voltage end; the first electrode of the seventh transistor is coupled to the first voltage end, the second electrode of the seventh transistor is coupled to the second electrode of the eighth transistor, the first end of the first capacitor, and the output end of the second comparison voltage generating circuit; the control electrode of the eighth transistor is coupled to the frequency hopping enable signal output end of the oscillator logic control circuit, the first electrode of the eighth transistor is coupled to the second voltage end; the second end of the second current source is coupled to the second voltage end; and the second end of the first capacitor is coupled to the second voltage end.

[0011] In some embodiments of the present disclosure, the comparison circuit includes: a first voltage comparator, wherein the non-inverting input terminal of the first voltage comparator is coupled to the output terminal of the first comparison voltage generating circuit, the inverting input terminal of the first voltage comparator is coupled to the output terminal of the second comparison voltage generating circuit, and the output terminal of the first electrical comparator is coupled to the frequency hopping signal output terminal of the frequency hopping control circuit.

[0012] In some embodiments of the present disclosure, the periodic signal generating circuit includes: a third current source, a second capacitor, a ninth transistor and a second voltage comparator. The first end of the third current source is coupled to the first voltage end, the second end of the third current source is coupled to the first end of the second capacitor, the second electrode of the ninth transistor and the non-inverting input end of the second voltage comparator; the second end of the second capacitor is coupled to the second voltage end; the first electrode of the ninth transistor is coupled to the second voltage end, the control electrode of the ninth transistor is coupled to the clock signal output end of the oscillator logic control circuit; the inverting input end of the second voltage comparator is coupled to the oscillator reference voltage input end, and the output end of the second voltage comparator is coupled to the output end of the periodic signal generating circuit.

[0013] In some embodiments of the present disclosure, the clock signal generating circuit includes: a first NOR gate, a second NOR gate, a first inverter, a second inverter, a first NAND gate, a third inverter and a delay circuit. Wherein, the first input end of the first NOR gate is coupled to the output end of the periodic signal generating circuit, the second input end of the first NOR gate is coupled to the enable signal end, the third input end of the first NOR gate is coupled to the output end of the second NOR gate, and the output end of the first NOR gate is coupled to the first input end of the second NOR gate, the input end of the second inverter and the frequency hopping enable signal output end of the oscillator logic control circuit; the second input end of the second NOR gate is coupled to the reset signal output end of the clock signal generating circuit; the input end of the first inverter is coupled to the frequency hopping signal output end of the frequency hopping control circuit, and the output end of the first inverter is coupled to the first input end of the first NAND gate; the second input end of the first NAND gate is coupled to the output end of the second inverter, and the output end of the first NAND gate is coupled to the input end of the third inverter; the output end of the third inverter is coupled to the clock signal output end of the oscillator logic control circuit; the input end of the delay circuit is coupled to the clock signal output end of the oscillator logic control circuit, and the output end of the delay circuit is coupled to the reset signal output end of the clock signal generating circuit.

[0014] According to a second aspect of the present disclosure, a switching power supply is provided. The switching power supply includes the clock signal control circuit provided by the first aspect of the present disclosure.

[0015] Other features and advantages of the embodiments of the present disclosure will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the embodiments of the present disclosure, but do not constitute a limitation on the embodiments of the present disclosure. In the accompanying drawings:

[0017] Figure 1 This is a schematic diagram of a PCM BUCK circuit;

[0018] Figure 2 It is a waveform diagram of the PCM BUCK circuit working in CCM and DCM;

[0019] Figure 3 This is a schematic diagram of the PSM waveform when the PCM BUCK circuit works under light load;

[0020] Figure 4 It is a waveform diagram of the double pulse and group pulse generated by the PCM BUCK circuit;

[0021] Figure 5 is a schematic block diagram of a clock signal control circuit according to an embodiment of the present disclosure;

[0022] Figure 6 is an exemplary circuit diagram of a frequency hopping control circuit in a clock signal control circuit according to an embodiment of the present disclosure;

[0023] Figure 7 is an exemplary circuit diagram of an oscillator logic control circuit in a clock signal control circuit according to an embodiment of the present disclosure;

[0024] Figure 8 is a waveform diagram of a signal in a frequency hopping control circuit according to an embodiment of the present disclosure;

[0025] Fig. 9 is a waveform diagram of signals in an oscillator logic control circuit according to an embodiment of the present disclosure.

[0026] Elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0028] In all embodiments of the present disclosure, since the source and drain of a metal oxide semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, in the embodiments of the present disclosure, the controlled middle terminal of the MOS transistor is referred to as a control terminal, and the remaining two terminals of the MOS transistor are referred to as a first terminal and a second terminal, respectively. In addition, terms such as "first" and "second" are only used to distinguish one component (or a portion of a component) from another component (or another portion of a component).

[0029] Figure 5 FIG. 5 is a schematic block diagram of a clock signal control circuit 500 provided according to an embodiment of the present disclosure. Figure 5 As shown, the clock signal control circuit 500 is applied to the switching power supply and may include: a frequency hopping control circuit 510 and an oscillator logic control circuit 520. The frequency hopping control circuit 510 may be coupled to the oscillator logic control circuit 520, the output error voltage output terminal V COMP , a first voltage terminal V1 and a second voltage terminal V2. The oscillator logic control circuit 520 can be coupled to the frequency hopping control circuit 510, the clock signal output terminal CLK, the first voltage terminal V1 and the second voltage terminal V2.

[0030] The frequency hopping control circuit 510 is configured to output an error voltage V COMP Generate a first comparison voltage and a second comparison voltage, and generate a frequency hopping signal Skip according to the comparison result of the first comparison voltage and the second comparison voltage. The oscillator logic control circuit 520 is configured to generate a frequency hopping enable signal V K , and when the frequency hopping signal Skip is a valid signal, the clock signal CLK is controlled to stop outputting, and when the frequency hopping signal Skip is an invalid signal, the clock signal CLK is controlled to output. The frequency hopping control circuit 510 is also configured to K When the first comparison voltage is at a low level, the first comparison voltage is compared with the second comparison voltage, and when the first comparison voltage is equal to the second comparison voltage, the generated frequency hopping signal Skip is an invalid signal, and when the first comparison voltage is greater than the second comparison voltage, the generated frequency hopping signal Skip is a valid signal.

[0031] Through the clock signal control circuit 500 of the embodiment of the present disclosure, when the switching power supply operates in a light-load state, a frequency hopping signal is generated based on the comparison result of the first comparison voltage generated by the output error voltage of the switching power supply and the second comparison voltage, and when the frequency hopping enable signal is at a low level and the first comparison voltage is greater than the second comparison voltage, the frequency hopping signal is a valid signal, prohibiting the output of the clock signal, and when the first comparison voltage is equal to the second comparison voltage, the frequency hopping signal is an invalid signal, ensuring the normal output of the clock signal. Therefore, through the clock signal control circuit 500 of the embodiment of the present disclosure, even if the output error voltage is very low and the response is slow, the frequency hopping signal will not continuously output multiple invalid signals, and only when the first comparison voltage is equal to the second comparison voltage can an invalid signal be output, thereby achieving that each clock signal has a relatively long and identical time interval, improving the efficiency of light-load operation, and avoiding the problem of double pulses or group pulses.

[0032] Figure 6 FIG. 5 shows an exemplary circuit diagram of a frequency hopping control circuit 510 in a clock signal control circuit 500 according to an embodiment of the present disclosure. Figure 6 As shown, the frequency hopping control circuit 510 may include: a first current generating circuit 511, a first comparison voltage generating circuit 512, a second comparison voltage generating circuit 513 and a comparison circuit 514. The first current generating circuit 511 is configured to generate a first current based on the output error voltage V COMP The first comparison voltage generating circuit 512 is configured to generate the first comparison voltage V based on the first mirror signal Ie of the first current signal I0. RES The second comparison voltage generating circuit 513 is configured to generate a second comparison voltage based on the second mirror signal Ic of the first current signal I0, the mirror signal Icap of the second current signal Ia, and the frequency hopping enable signal V K , generating the second comparison voltage V CAP The comparison circuit 514 is configured to RES Compared with the second voltage V CAP The comparison result generates the frequency hopping signal Skip.

[0033] The first current generating circuit 511 may include: a first transistor M1, a second transistor M2, a third transistor M3 and a first current source I1. The first electrode of the first transistor M1 is coupled to the first voltage terminal V1, the control electrode of the first transistor M1 is coupled to the second electrode of the first transistor M1, the second electrode of the second transistor M2 and the output terminal of the first current generating circuit 511. The first electrode of the second transistor M2 is coupled to the control electrode of the third transistor M3 and the output error voltage output terminal V COMP, the control electrode of the second transistor M2 is coupled to the second end of the first current source I1 and the second electrode of the third transistor M3. The first electrode of the third transistor M3 is coupled to the second voltage terminal V2. The first end of the first current source I1 is coupled to the first voltage terminal V1. The first comparison voltage generating circuit 512 may include: a fourth transistor M4 and a first resistor R1. The control electrode of the fourth transistor M4 is coupled to the output end of the first current generating circuit 511, the first electrode of the fourth transistor M4 is coupled to the first voltage terminal V1, and the second electrode of the fourth transistor M4 is coupled to the first end of the first resistor R1 and the output end of the first comparison voltage generating circuit 512. The second end of the first resistor R1 is coupled to the second voltage terminal V2. The second comparison voltage generating circuit 513 may include: a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a second current source I2 and a first capacitor C1. The control electrode of the fifth transistor M5 is coupled to the output terminal of the first current generating circuit 511, the first electrode of the fifth transistor M5 is coupled to the first voltage terminal V1, the second electrode of the fifth transistor M5 is coupled to the first terminal of the second current source I2, the control electrode of the sixth transistor M6, the second electrode of the sixth transistor M6 and the control electrode of the seventh transistor M7. The first electrode of the sixth transistor M6 is coupled to the first voltage terminal V1. The first electrode of the seventh transistor M7 is coupled to the first voltage terminal V1, the second electrode of the seventh transistor M7 is coupled to the second electrode of the eighth transistor M8, the first terminal of the first capacitor C1 and the output terminal of the second comparison voltage generating circuit 513. The control electrode of the eighth transistor M8 is coupled to the frequency hopping enable signal output terminal of the oscillator logic control circuit 520, and the first electrode of the eighth transistor M8 is coupled to the second voltage terminal V2. The second terminal of the second current source I2 is coupled to the second voltage terminal V2. The second terminal of the first capacitor C1 is coupled to the second voltage terminal V2. The comparison circuit 514 may include: a first voltage comparator COMP1. Among them, the non-inverting input terminal of the first voltage comparator COMP1 is coupled to the output terminal of the first comparison voltage generating circuit 512, the inverting input terminal of the first voltage comparator COMP1 is coupled to the output terminal of the second comparison voltage generating circuit 513, and the output terminal of the first electrical comparator COMP1 is coupled to the frequency hopping signal output terminal Skip of the frequency hopping control circuit 510.

[0034] like Figure 7 FIG. 5 shows an exemplary circuit diagram of an oscillator logic control circuit 520 in a clock signal control circuit 500 according to an embodiment of the present disclosure. Figure 7As shown, the oscillator logic control circuit 520 may include: a period signal generating circuit 521 and a clock signal generating circuit 522. The period signal generating circuit 521 is configured to generate a period signal according to the oscillator reference voltage V OSC The comparison result with the ramp voltage Vramp generates a periodic signal CLK0. The clock signal generating circuit 522 is configured to generate the frequency hopping enable signal V according to the periodic signal CLK0 and the frequency hopping signal Skip. K and the clock signal CLK.

[0035] The periodic signal generating circuit 521 may include: a third current source I3, a second capacitor C2, a ninth transistor M9 and a second voltage comparator COMP2. The first end of the third current source I3 is coupled to the first voltage terminal V1, the second end of the third current source I3 is coupled to the first end of the second capacitor C2, the second electrode of the ninth transistor M9 and the non-inverting input terminal of the second voltage comparator COMP2. The second end of the second capacitor C2 is coupled to the second voltage terminal V2. The first electrode of the ninth transistor M9 is coupled to the second voltage terminal V2, and the control electrode of the ninth transistor M9 is coupled to the clock signal output terminal CLK of the oscillator logic control circuit 520. The inverting input terminal of the second voltage comparator COMP2 is coupled to the oscillator reference voltage input terminal V OSC , the output end of the second voltage comparator COMP2 is coupled to the output end of the period signal generating circuit 521. The clock signal generating circuit 522 may include: a first NOR gate G1, a second NOR gate G2, a first inverter D1, a second inverter D2, a first NAND gate G3, a third inverter D3 and a delay circuit DLY. The first input end of the first NOR gate G1 is coupled to the output end of the period signal generating circuit 521, the second input end of the first NOR gate G1 is coupled to the enable signal end EN, the third input end of the first NOR gate G1 is coupled to the output end of the second NOR gate G2, and the output end of the first NOR gate G1 is coupled to the first input end of the second NOR gate G2, the input end of the second inverter D2 and the frequency hopping enable signal output end V of the oscillator logic control circuit 520. K. The second input terminal of the second NOR gate G2 is coupled to the reset signal output terminal Reset of the clock signal generating circuit 522. The input terminal of the first inverter D1 is coupled to the frequency hopping signal output terminal Skip of the frequency hopping control circuit 510, and the output terminal of the first inverter D1 is coupled to the first input terminal of the first NAND gate G3. The second input terminal of the first NAND gate G3 is coupled to the output terminal of the second inverter D2, and the output terminal of the first NAND gate G3 is coupled to the input terminal of the third inverter D3. The output terminal of the third inverter D3 is coupled to the clock signal output terminal of the oscillator logic control circuit 520. The input terminal of the delay circuit DLY is coupled to the clock signal output terminal of the oscillator logic control circuit 520, and the output terminal of the delay circuit DLY is coupled to the reset signal output terminal Reset of the clock signal generating circuit 522.

[0036] exist Figure 6 and Figure 7 In the example, a 5V power supply voltage VDD is input from the first voltage terminal V1. The second voltage terminal V2 is grounded. The oscillator reference voltage V OSC Input a fixed voltage, for example, 1V. For the signal input to the enable signal terminal EN, before the third current source I3 in the periodic signal generating circuit 521 is enabled, the enable signal terminal EN input is a high level, and after the third current source I3 is enabled, the input to the enable signal terminal EN is always a low level. For the setting of the delay circuit DLY, as long as the clock signal CLK is delayed by 10ns, the specific circuit setting of the delay circuit DLY is not limited in the disclosed embodiment. The first transistor M1, the fourth transistor M4 to the seventh transistor M7 are all PMOS transistors, and the second transistor M2, the third transistor M3, the eighth transistor M8 and the ninth transistor M9 are all NMOS transistors. Those skilled in the art should understand that based on the above-mentioned inventive concept, Figure 6 and Figure 7 Variations of the circuit shown in the figure should also fall within the scope of protection of the present disclosure. In this variation, the transistor and the voltage terminal may also have the same Figure 6 , 7 Examples of different setups are shown.

[0037] Combine the following Figure 6 , 7 The working process of the clock signal control circuit 500 according to the embodiment of the present disclosure is explained by an example.

[0038] like Figure 6As shown, the current signal generated by the second current source I2 is Ib, the current signal flowing through the fifth transistor M5 is Ic, the current signal flowing through the sixth transistor M6 is Ia, and the current signal flowing through the seventh transistor is Icap. Among them, since Ib is a fixed current, it can be known through circuit analysis that: when Ic≤Ib, Ia=Ib-Ic; when Ic>Ib, the circuit will change the state of the fifth transistor M5, reduce the current signal Ic to be equal to the current signal Ib, then Ia=0.

[0039] When the switching power supply operates under light load, the output voltage of the switching power supply increases, so that its feedback voltage V FB increases, so the output error voltage V COMP Lower, at this time the gate-source voltage V GS is larger, so the second transistor M2 is turned on, generating the first current signal I0, thereby generating the first mirror signal Ie and the second mirror signal Ic. Therefore, the first comparison voltage V RES =Ie*R1. Since the generated second image signal Ic is greater than Ib, the second current signal Ia=0, and its image signal Icap=0, the corresponding second comparison voltage V CAP =0. The first comparison voltage V RES and the second comparison voltage V CAP After passing through the first voltage comparator COMP1, the generated frequency hopping signal Skip is a valid signal, i.e., a high-level signal. Then, the high-level signal controls the clock signal CLK to stop output through the oscillator logic control circuit 520, thereby completing the control of the clock signal CLK by the frequency hopping signal Skip and realizing the frequency reduction function.

[0040] After that, because there is no clock signal CLK output, the feedback voltage V FB will decrease again, resulting in the output error voltage V COMP The first current signal I0 decreases, so the first mirror signal Ie and the second mirror signal Ic are also reduced, resulting in the first comparison voltage V RES When the second mirror signal Ic decreases to less than Ib, the second current signal Ia=Ib-Ic, and the first capacitor C1 is charged by the mirror signal Icap, and the second comparison voltage V CAP Reaching the first comparison voltage V RES At the time, the frequency hopping signal Skip outputs an invalid signal, that is, a low-level signal, and the clock signal CLK is output normally. The specific waveform is as follows Figure 8 shown.

[0041] When the switching power supply is working in a heavy load state, the feedback voltage V FBlower, thus the output error voltage V COMP is larger, at this time the gate-source voltage V GS The second transistor M2 is turned off, so the first current signal I0 is 0, the first mirror signal Ie and the second mirror signal Ic are also 0, that is, Ib>Ie=Ic=0. Through the above analysis, Ia=Ib is obtained, and the mirror signal Icap of the second current signal Ia is used to charge the first capacitor C1 to form the second comparison voltage V CAP Since the first mirror signal Ie is 0, the first comparison voltage V RES =0. The first comparison voltage V RES and the second comparison voltage V CAP The frequency hopping signal Skip is obtained through the first comparator COMP1. The frequency hopping signal Skip is always an invalid signal, ie, a low level signal. Therefore, when the switching power supply works in a heavy load state, the clock signal CLK is always output normally, and the frequency is the same as the setting.

[0042] In addition, when the switching power supply is working in a heavy load state, in order to avoid the first comparison voltage V RES and the second comparison voltage V CAP In the case where both are 0, in the embodiment of the present disclosure, an offset value offset is set at the inverting input terminal of the first voltage comparator COMP1, for example, 10mv or 50mv, so that the output of the first voltage comparator COMP1 is 0.

[0043] In addition, the mirror ratio relationship between the first transistor M1 and the fourth transistor M4 and the fifth transistor M5 in the frequency hopping control circuit 510 is 1:K, and K may be less than 1 or greater than 1, which is not limited in the embodiment of the present disclosure.

[0044] like Figure 7 As shown, when the oscillator logic control circuit 520 receives the frequency hopping signal Skip, if the frequency hopping signal Skip is a low level signal, the clock signal CLK is normally output, and after the reset signal Reset is obtained by the delay circuit DLY and fed back, the frequency hopping enable signal V K Set to a high level signal, so Figure 6 The eighth transistor M8 in the circuit is turned on, and the second comparison voltage V CAP is discharged, the frequency hopping signal Skip is a valid signal, that is, a high-level signal, and the clock signal CLK stops outputting, so that the control method can also avoid the problem of double pulses or group pulses at high frequencies. By working repeatedly like this, the PSM working mode is formed.

[0045] When the switching power supply is working under light load, the output error voltage V COMP Regardless of the output error voltage VCOMP Regardless of the speed of the response, it must be detected again at the end of the next normal cycle of the clock signal CLK, so that enough output error voltage V COMP Specifically, after the normal cycle of the clock signal CLK ends, the frequency hopping enable signal V K Set low, if the output error voltage V COMP Very low but slow to react, the frequency hopping signal Skip will not be a low level signal quickly and continuously, and it will be delayed at least until the output error voltage V COMP The second comparison voltage V CAP Equal to the first comparison voltage V RES , in order to output the low-level signal of the frequency hopping signal Skip, so that each clock signal CLK has a relatively long and same time interval, which improves the efficiency of light-load operation. The specific waveform is as follows Fig. 9 shown.

[0046] In addition, the frequency hopping enable signal V K When the eighth transistor M8 is turned on, the second comparison voltage V CAP Always 0, no need to compare the first comparison voltage V RES and the second comparison voltage V CAP The generated frequency hopping signal Skip is a valid signal, that is, a high-level signal. K When it is a low level signal, the first comparison voltage V RES and the second comparison voltage V CAP When the first comparison voltage V RES is equal to the second comparison voltage V CAP , the generated frequency hopping signal Skip is an invalid signal, that is, a low level signal. When the first comparison voltage V RES is greater than the second comparison voltage V CAP , the generated frequency hopping signal Skip is a valid signal, that is, a high level signal.

[0047] In summary, when the switching power supply is working in a light-load state, a frequency hopping signal is generated based on the comparison result of the first comparison voltage and the second comparison voltage generated by the output error voltage of the switching power supply, and when the frequency hopping enable signal is at a low level and the first comparison voltage is greater than the second comparison voltage, the frequency hopping signal is a valid signal, prohibiting the output of the clock signal, and when the first comparison voltage is equal to the second comparison voltage, the frequency hopping signal is an invalid signal, ensuring the normal output of the clock signal. Therefore, even if the output error voltage is very low and the response is slow, the frequency hopping signal will not continuously output multiple invalid signals, and only when the first comparison voltage is equal to the second comparison voltage can an invalid signal be output, thereby achieving a relatively long and identical time interval for each clock signal, improving the efficiency of light-load operation, and avoiding the problem of double pulses or group pulses.

[0048] In addition, the clock signal control circuit 500 of the embodiment of the present disclosure is described by taking the BUCK topology as an example, and after modification, it can also be applied to various topologies such as BOOST, BUCK-BOOST, SWITCH CAP, etc.

[0049] The embodiment of the present disclosure further provides a switching power supply. The switching power supply includes a clock signal control circuit 500 according to the embodiment of the present disclosure. The switching power supply can be used in new energy vehicles, white appliances, etc.

[0050] Unless the context clearly indicates otherwise, the singular form of the words used herein and in the appended claims includes the plural and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the words "comprise" and "include" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it is located after a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0051] Further aspects and scopes of adaptability become apparent from the description provided herein. It should be understood that various aspects of the present application can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended for purposes of illustration only and are not intended to limit the scope of the present application.

[0052] Several embodiments of the present disclosure are described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the attached claims.

Claims

1. A clock signal control circuit, applied to a switching power supply, characterized in that: include: Frequency hopping control circuit and oscillator logic control circuit, Wherein, the frequency hopping control circuit is configured to generate a first comparison voltage and a second comparison voltage based on the output error voltage of the switching power supply, and generate a frequency hopping signal according to a comparison result of the first comparison voltage and the second comparison voltage; The oscillator logic control circuit is configured to generate a frequency hopping enable signal, and when the frequency hopping signal is a valid signal, control the clock signal to stop outputting, and when the frequency hopping signal is an invalid signal, control the clock signal to output; The frequency hopping control circuit is further configured to compare the first comparison voltage with the second comparison voltage when the frequency hopping enable signal is at a low level, and when the first comparison voltage is equal to the second comparison voltage, the generated frequency hopping signal is an invalid signal, and when the first comparison voltage is greater than the second comparison voltage, the generated frequency hopping signal is a valid signal. The frequency hopping control circuit includes: a first current generating circuit, a first comparison voltage generating circuit, a second comparison voltage generating circuit and a comparison circuit. The first current generating circuit is configured to generate a first current signal based on an output error voltage of the switching power supply; The first comparison voltage generating circuit is configured to generate the first comparison voltage based on a first mirror signal of the first current signal; The second comparison voltage generating circuit is configured to generate the second comparison voltage based on the second mirror signal of the first current signal, the mirror signal of the second current signal and the frequency hopping enable signal; The comparison circuit is configured to generate the frequency hopping signal according to a comparison result between the first comparison voltage and the second comparison voltage.

2. The clock signal control circuit according to claim 1, characterized in that: The oscillator logic control circuit includes: a periodic signal generating circuit and a clock signal generating circuit, Wherein, the periodic signal generating circuit is configured to generate a periodic signal according to a comparison result between an oscillator reference voltage and a ramp voltage; The clock signal generating circuit is configured to generate the frequency hopping enable signal and the clock signal according to the period signal and the frequency hopping signal.

3. The clock signal control circuit according to claim 1, characterized in that: The first current generating circuit includes: a first transistor, a second transistor, a third transistor and a first current source. Wherein, the first electrode of the first transistor is coupled to the first voltage terminal, and the control electrode of the first transistor is coupled to the second electrode of the first transistor, the second electrode of the second transistor and the output terminal of the first current generating circuit; A first electrode of the second transistor is coupled to a control electrode of the third transistor and an output error voltage output terminal of the switching power supply, and a control electrode of the second transistor is coupled to a second terminal of the first current source and a second electrode of the third transistor; The first electrode of the third transistor is coupled to the second voltage terminal; The first terminal of the first current source is coupled to the first voltage terminal.

4. The clock signal control circuit according to claim 1, characterized in that: The first comparison voltage generating circuit comprises: a fourth transistor and a first resistor, The control electrode of the fourth transistor is coupled to the output terminal of the first current generating circuit, the first electrode of the fourth transistor is coupled to the first voltage terminal, and the second electrode of the fourth transistor is coupled to the first terminal of the first resistor and the output terminal of the first comparison voltage generating circuit; The second end of the first resistor is coupled to a second voltage end.

5. The clock signal control circuit according to claim 1, characterized in that: The second comparison voltage generating circuit includes: a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a second current source and a first capacitor. wherein the control electrode of the fifth transistor is coupled to the output end of the first current generating circuit, the first electrode of the fifth transistor is coupled to the first voltage end, the second electrode of the fifth transistor is coupled to the first end of the second current source, the control electrode of the sixth transistor, the second electrode of the sixth transistor, and the control electrode of the seventh transistor; The first electrode of the sixth transistor is coupled to the first voltage terminal; A first electrode of the seventh transistor is coupled to the first voltage terminal, and a second electrode of the seventh transistor is coupled to the second electrode of the eighth transistor, the first terminal of the first capacitor, and the output terminal of the second comparison voltage generating circuit; The control electrode of the eighth transistor is coupled to the frequency hopping enable signal output terminal of the oscillator logic control circuit, and the first electrode of the eighth transistor is coupled to the second voltage terminal; The second terminal of the second current source is coupled to the second voltage terminal; The second terminal of the first capacitor is coupled to the second voltage terminal.

6. The clock signal control circuit according to claim 1, characterized in that: The comparison circuit comprises: a first voltage comparator, Among them, the non-inverting input terminal of the first voltage comparator is coupled to the output terminal of the first comparison voltage generating circuit, the inverting input terminal of the first voltage comparator is coupled to the output terminal of the second comparison voltage generating circuit, and the output terminal of the first voltage comparator is coupled to the frequency hopping signal output terminal of the frequency hopping control circuit.

7. The clock signal control circuit according to claim 2, characterized in that: The periodic signal generating circuit comprises: a third current source, a second capacitor, a ninth transistor and a second voltage comparator. Wherein, a first terminal of the third current source is coupled to the first voltage terminal, and a second terminal of the third current source is coupled to the first terminal of the second capacitor, the second electrode of the ninth transistor and the non-inverting input terminal of the second voltage comparator; The second terminal of the second capacitor is coupled to the second voltage terminal; A first electrode of the ninth transistor is coupled to the second voltage terminal, and a control electrode of the ninth transistor is coupled to the clock signal output terminal of the oscillator logic control circuit; The inverting input terminal of the second voltage comparator is coupled to the reference voltage input terminal of the oscillator, and the output terminal of the second voltage comparator is coupled to the output terminal of the period signal generating circuit.

8. The clock signal control circuit according to claim 2, characterized in that: The clock signal generating circuit comprises: a first NOR gate, a second NOR gate, a first inverter, a second inverter, a first NAND gate, a third inverter and a delay circuit. Wherein, the first input terminal of the first NOR gate is coupled to the output terminal of the periodic signal generating circuit, the second input terminal of the first NOR gate is coupled to the enable signal terminal, the third input terminal of the first NOR gate is coupled to the output terminal of the second NOR gate, and the output terminal of the first NOR gate is coupled to the first input terminal of the second NOR gate, the input terminal of the second inverter and the frequency hopping enable signal output terminal of the oscillator logic control circuit; The second input terminal of the second NOR gate is coupled to the reset signal output terminal of the clock signal generating circuit; The input terminal of the first inverter is coupled to the frequency hopping signal output terminal of the frequency hopping control circuit, and the output terminal of the first inverter is coupled to the first input terminal of the first NAND gate; The second input terminal of the first NAND gate is coupled to the output terminal of the second inverter, and the output terminal of the first NAND gate is coupled to the input terminal of the third inverter; The output terminal of the third inverter is coupled to the clock signal output terminal of the oscillator logic control circuit; An input end of the delay circuit is coupled to a clock signal output end of the oscillator logic control circuit, and an output end of the delay circuit is coupled to a reset signal output end of the clock signal generating circuit.

9. A switching power supply, characterized in that: include: A clock signal control circuit according to any one of claims 1 to 8.

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