Master-slave mode multi-AD module sampling architecture
Through the main mode of multi -AD module sampling architecture, the problem of increasing hardware costs and design difficulty in traditional synchronization methods, achieving better synchronization effects and reducing hardware design cost effects.
Patent Information
- Application Number
- CN202411352751.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-26
- Publication Date
- 2025-01-24
AI Technical Summary
The traditional multi-AD module sampling and pre-processing synchronization methods rely on dedicated clock synchronization modules, increasing hardware cost and design difficulty, and the clock frequency division phase relationship is uncontrollable, resulting in poor synchronization effect.
Adopting a master-slave mode multi-AD module sampling architecture, the master AD sampling module realizes clock frequency division and distribution, reducing hardware design costs, and achieving better synchronization effects through ADC chip synchronization and synchronization pulse design.
It reduces hardware design costs, saves radar installation space, improves synchronization effects, and meets the synchronization requirements for multi-subarray digital intermediate frequency reception.
Smart Images
Figure CN119363111A_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the technical field of airborne active phased array radar AD sampling and receiving, and in particular, relates to a master-slave mode multi-AD module sampling architecture. Background Art
[0002] The rapid development and application of active phased array radar and digital array radar have increased the demand for the number of RF receiving channels, and the digital intermediate frequency signal sampling, receiving and preprocessing have developed towards a multi-module, multi-channel architecture. Multi-module multi-channel AD sampling, receiving and preprocessing synchronization technology is the key to the airborne active phased array multi-channel receiving system.
[0003] Traditionally, the sampling and preprocessing synchronization of multiple AD modules is usually achieved by a dedicated clock synchronization module, and the dedicated synchronization module only provides synchronization clocks to each AD module, that is, the intermediate frequency signal sampling synchronization is achieved by the synchronization clocks with the same phase or fixed phase difference. Each AD module implements digital down-conversion preprocessing of the sampled intermediate frequency signal based on FPGA, and packages the preprocessed baseband signal to the processor for subsequent radar signal processing. For a system composed of N AD sampling modules, the traditional method synchronization implementation architecture is as follows Figure 1 shown.
[0004] This traditional synchronization method only uses a dedicated clock synchronization module, relies on the fixed phase relationship of the clocks received by each module, and does not restrict the digital down-conversion preprocessing of the intermediate frequency signal after sampling. The traditional synchronization method has the following main disadvantages:
[0005] (1) Increase in the number and cost of hardware modules: A dedicated clock synchronization module must be used to achieve synchronous processing of multiple AD modules, which increases the number of airborne radar installed modules and the hardware design cost. At the same time, the physical limitations of the airborne radar installed weight and volume increase the design difficulty.
[0006] (2) The phase relationship of the clock division within each module is uncontrollable: After the clock synchronization module provides the synchronous clock to each AD module, it needs to be divided and distributed through the clock chip inside each AD module. When the clock chip inside each module divides the clock, the phase relationship may not be fixed, which makes it difficult to debug the multi-module hardware circuit, resulting in poor synchronization effect. Summary of the invention
[0007] In order to solve the above problems, the present application provides a master-slave mode multi-AD module sampling architecture, including multiple AD sampling modules,
[0008] The AD sampling module is divided into a main AD sampling module and multiple slave AD sampling modules. The main AD sampling module includes a clock frequency division submodule, a clock distribution submodule, an ADC submodule and an FPGA submodule; the slave AD sampling module includes a clock distribution submodule, an ADC submodule and an FPGA submodule;
[0009] The clock frequency division submodule received by the main AD sampling module receives the reference clock signal and generates multiple identical synchronous clock signals, one of which is transmitted to the clock distribution submodule of the main AD sampling module. In the main AD sampling module, the clock distribution submodule transmits it to the ADC submodule, and the ADC submodule transmits the generated pulse signal to the FPGA submodule.
[0010] The remaining synchronous clock signals of the master AD sampling module are respectively transmitted to the clock distribution submodules of all slave AD sampling modules, and in each slave AD sampling module, the clock distribution submodule transmits them to the ADC submodule, and the ADC submodule then transmits the generated data signal to the FPGA submodule.
[0011] Preferably, the main AD sampling module also has a switch submodule, the structure of the slave AD sampling module is exactly the same as that of the main AD sampling module, the input end of the switch submodule includes an external pin and a clock division submodule, the switch submodule of the main AD sampling module selects to receive the synchronous clock signal of the clock division submodule, and the slave AD sampling module selects to receive the synchronous clock signal generated by the main AD sampling module and input by the external pin.
[0012] Preferably, the ADC submodule includes a plurality of ADC units distributed in a tree structure, the first ADC unit in the ADC units distributed in the tree structure includes a clock input terminal, a pulse input terminal, a pulse output terminal connected to the pulse input terminals of other ADC units in the tree structure, and a pulse output terminal with an external pin, and the first ADC units of all AD sampling modules are connected in series with the pulse output terminal with an external pin through the pulse input terminal.
[0013] Preferably, the pulse input terminal of the first ADC unit connected in series has no input.
[0014] Preferably, the FPGA submodule includes an interface FPGA unit, a driver chip, a switch module, and a signal processing FPGA unit;
[0015] The interface FPGA unit generates a synchronization pulse, the driver chip divides the synchronization pulse generated by the interface FPGA unit into a master synchronization pulse and a plurality of slave synchronization pulses, and the switch module has an external input terminal and an internal input terminal for receiving the master synchronization pulse;
[0016] Connecting multiple slave synchronization pulses of one FPGA submodule to the external input terminals of the switch modules of the other FPGA submodules respectively, and transmitting the master synchronization pulse thereof to the signal processing FPGA unit after passing through the switch module;
[0017] The switch modules of the remaining FPGA sub-modules select the synchronization pulses received from the external input end and transmit them to the corresponding signal processing FPGA units. The signal processing FPGA units obtain data in combination with the corresponding ADC sub-modules. The structures of all FPGA sub-modules are the same.
[0018] The advantages of the present application include: the method of the present invention removes the dedicated clock synchronization module in the traditional synchronization design, adopts AD modules with completely identical hardware and logic algorithm designs, and selects one of them as the main module to realize clock frequency division distribution and other synchronization design control, and realizes multi-module multi-channel AD sampling and pre-processing synchronization. The advantages are mainly reflected in:
[0019] (1) Reduce hardware design costs: This method does not require a dedicated clock synchronization module, saving the design, manufacturing and production costs of related circuits and module hardware.
[0020] (2) Saving radar installation space: Reducing one module slot can save installation space and weight for airborne radar equipment with increasingly higher integration.
[0021] (3) Better synchronization design architecture: In addition to the traditional clock synchronization, the synchronization method based on the master-slave mode also adds ADC chip synchronization, multi-module synchronization pulse design, and FPGA-based intermediate frequency signal digital down-conversion pre-processing synchronization. The synchronization solution is more complete and the synchronization effect is better.
[0022] The method of the present invention can be widely used in the design of multi-module multi-channel AD sampling receiving software and hardware of airborne active phased array radar, and can meet the multi-subarray digital intermediate frequency receiving synchronization requirements of digital array radar. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 Block diagram of the traditional method multi-module AD sampling synchronization design.
[0024] Figure 2 The master-slave mode clock synchronization design block diagram of this method.
[0025] Figure 3 The master-slave mode ADC chip synchronization design block diagram of this method.
[0026] Figure 4 The master-slave mode synchronization pulse design block diagram of this method.
[0027] Figure 5 The master-slave mode digital down-conversion preprocessing synchronization design block diagram of this method. DETAILED DESCRIPTION
[0028] In order to make the technical solution and advantages of the present application clearer, the technical solution of the present application will be further described in detail in detail and in detail in conjunction with the accompanying drawings. It can be understood that the specific embodiments described here are only partial embodiments of the present application, which are only used to explain the present application, not to limit the present application. It should be noted that, for the convenience of description, only the parts related to the present application are shown in the accompanying drawings, and other related parts can refer to the general design. In the absence of conflict, the embodiments in the present application and the technical features in the embodiments can be combined with each other to obtain new embodiments.
[0029] The implementation content of the master-slave mode multi-AD module sampling and pre-processing synchronization method includes: master-slave module clock synchronization design, master-slave module ADC sampling circuit synchronization design, master-slave module synchronization pulse circuit design, digital down-conversion pre-processing synchronization design. The specific implementation steps are as follows:
[0030] (1) Master-slave module clock synchronization design
[0031] Depend on Figure 2 The clock synchronization design architecture shown in the figure uses a clock chip with frequency division, distribution and phase adjustment in the AD sampling main module, taking into full account the differences in clock network layout and wiring, to achieve phase synchronization between the main module itself and the clock output to each slave module. According to the hardware design and the spatial layout of the airborne radar, the phase and delay relationship of the main module clock chip is adjusted to synchronize the clocks reaching the master and slave modules. The master and slave module synchronized clocks are then distributed to each ADC chip through the clock distribution chip in the module.
[0032] Since the hardware design of the master and slave AD sampling modules must be consistent, the slave module must switch the reference clock input or the master module clock input. The clock switch is distinguished as a master module or a slave module according to the number of each module, and is implemented by FPGA logic control. This design can ensure the consistency of the FPGA logic of each module, so that the digital receiving module does not need to be fixed in a certain slot during the installation process, and the logic control selection is only realized by the motherboard's module number.
[0033] (2) Synchronous design of ADC sampling circuit of master and slave modules
[0034] Depend on Figure 3 The high-speed ADC chip synchronization design architecture shown in the figure shows that in addition to sampling clock synchronization, synchronization between multiple ADC chips is also critical. High-speed ADC chips usually provide input and output interfaces for chip synchronization. In an airborne radar system composed of multiple AD sampling modules, the ADC selection must select a chip with a synchronization interface.
[0035] The synchronous output of the ADC chip 1 of the master module is used as the synchronization source of all modules and ADC chips. In the module, the synchronization signal of ADC chip 1 is output to other ADC chips of the module, and synchronization is achieved through parallel and cascade connection of ADC chips; between modules, the master module outputs AD synchronization signal to slave module 1, and slave module 1 uses this synchronization signal as the synchronization signal source of the ADC chip of the module, and outputs the synchronization signal to slave module 2 at the same time. Slave module 2 adopts the same processing method as slave module 1. By analogy, the parallel and cascade synchronization design of ADC chips of N modules is realized.
[0036] The synchronization interfaces of ADC chips of different models may be slightly different, but they can all be used Figure 3 The ADC chip synchronization design method shown.
[0037] (3) Master-slave module synchronization pulse circuit design
[0038] In addition to clock synchronization and ADC chip synchronization, hardware synchronization circuits usually need to be supplemented by synchronization pulse design as a synchronization processing benchmark for logic such as ADC sampling intermediate frequency signal data analysis, digital down-conversion, and data packaging output. This is an indispensable design that is based on hardware synchronization and supplemented by logic synchronization.
[0039] Depend on Figure 4 The pulse synchronization design architecture shown uses a similar processing method to the synchronous clock. The master module FPGA generates the synchronous clock and distributes it to each slave module through the motherboard routing. When the synchronous pulse is used in the module, after confirming whether it is a master or slave module according to the module number, the synchronous pulse switching is realized by controlling the hardware switch through the FPGA.
[0040] (4) Digital down-conversion preprocessing synchronization design
[0041] The hardware design circuit composed of clock synchronization and ADC chip synchronization realizes the synchronization of ADC intermediate frequency sampling signal. However, when the intermediate frequency signal is further processed based on FPGA, data asynchrony may still occur between modules. It is necessary to control the digital down-conversion pre-processing synchronization design through synchronization pulse.
[0042] Depend on Figure 5 The digital down-conversion pre-processing synchronization design architecture shown in the figure, after the FPGA receives the synchronization pulse, the synchronization pulse simultaneously starts the intermediate frequency sampling signal analysis, digital mixing, digital low-pass filtering and extraction, data packaging and other algorithm logic functions based on the FPGA, thereby realizing the digital down-conversion pre-processing synchronization.
[0043] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.
Claims
1. A master-slave mode multi-AD module sampling architecture, characterized in that: Including multiple AD sampling modules, The AD sampling module is divided into a main AD sampling module and multiple slave AD sampling modules. The main AD sampling module includes a clock frequency division submodule, a clock distribution submodule, an ADC submodule and an FPGA submodule; the slave AD sampling module includes a clock distribution submodule, an ADC submodule and an FPGA submodule; The clock frequency division submodule received by the main AD sampling module receives the reference clock signal and generates multiple identical synchronous clock signals, one of which is transmitted to the clock distribution submodule of the main AD sampling module. In the main AD sampling module, the clock distribution submodule transmits it to the ADC submodule, and the ADC submodule transmits the generated pulse signal to the FPGA submodule. The remaining synchronous clock signals of the master AD sampling module are respectively transmitted to the clock distribution submodules of all slave AD sampling modules, and in each slave AD sampling module, the clock distribution submodule transmits them to the ADC submodule, and the ADC submodule then transmits the generated data signal to the FPGA submodule.
2. The master-slave mode multi-AD module sampling architecture as claimed in claim 1, characterized in that: The main AD sampling module also has a switch submodule. The structure of the slave AD sampling module is exactly the same as that of the main AD sampling module. The input end of the switch submodule includes an external pin and a clock division submodule. The switch submodule of the main AD sampling module selects to receive the synchronous clock signal of the clock division submodule, and the slave AD sampling module selects to receive the synchronous clock signal generated by the main AD sampling module input by the external pin.
3. The master-slave mode multi-AD module sampling architecture as claimed in claim 1, characterized in that: The ADC submodule includes multiple ADC units distributed in a tree structure. The first ADC unit in the ADC units distributed in the tree structure includes a clock input terminal, a pulse input terminal, a pulse output terminal connected to the pulse input terminals of other ADC units in the tree structure, and a pulse output terminal with an external pin. The first ADC units of all AD sampling modules are connected in series with the pulse output terminal with an external pin through the pulse input terminal.
4. The master-slave mode multi-AD module sampling architecture as claimed in claim 3, characterized in that: There is no input at the pulse input terminal of the first ADC unit in series.
5. The master-slave mode multi-AD module sampling architecture as claimed in claim 3, characterized in that: The FPGA submodule includes an interface FPGA unit, a driver chip, a switch module, and a signal processing FPGA unit; The interface FPGA unit generates a synchronization pulse, the driver chip divides the synchronization pulse generated by the interface FPGA unit into a master synchronization pulse and a plurality of slave synchronization pulses, and the switch module has an external input terminal and an internal input terminal for receiving the master synchronization pulse; Connecting multiple slave synchronization pulses of one FPGA submodule to the external input terminals of the switch modules of the other FPGA submodules respectively, and transmitting the master synchronization pulse thereof to the signal processing FPGA unit after passing through the switch module; The switch modules of the remaining FPGA sub-modules select the slave synchronization pulses received at the external input end and transmit them to the corresponding signal processing FPGA units, and the signal processing FPGA units obtain data in combination with the corresponding ADC sub-modules.
6. The master-slave mode multi-AD module sampling architecture as claimed in claim 5, characterized in that: The structures of the FPGA submodules are all the same.