Analog-to-digital conversion implementation method based on phase-locked loop

Abstract

The invention discloses an analog-to-digital conversion implementation method based on a phase-locked loop, and belongs to the technical field of CMOS integrated circuits. By means of the phase-locked loop added in the circuit, the linearity of the whole circuit can be guaranteed within a large input range by reasonably adjusting the input and output relation and correcting signals between the voltage-controlled oscillator and the phase-locked loop circuit, and higher stability is achieved; meanwhile, the pressure of a subsequent counter is relieved by means of a frequency divider in the phase-locked loop, and a more digitized circuit is obtained. And the time for the output signal frequency to reach the stability can be accurately judged by checking the voltage change of the input signal of the voltage-controlled oscillator in the phase-locked loop.

Description

Technical Field

[0001] The invention belongs to the technical field of CMOS integrated circuits, and in particular relates to a method for realizing analog-to-digital conversion based on a phase-locked loop. Background Art

[0002] Nowadays, as the CMOS process size continues to shrink, the voltage margin of analog circuits continues to decrease, and the voltage gain is gradually reduced. In order to compensate for these losses, increasing the width-to-length ratio of MOS tubes or increasing the number of analog circuits will lead to a significant increase in circuit area and power consumption, which makes it difficult to optimize the overall performance of the circuit. In the face of the ever-decreasing CMOS process size, digital circuits have faster switching speeds, smaller areas, and lower power consumption, so they have great advantages.

[0003] In the field of analog-to-digital converter (ADC) technology, many architectures require analog circuit modules, such as comparator circuits and digital-to-analog conversion circuits. Especially in the field of high-precision ADC, these analog circuits have high requirements. As the size of CMOS continues to decrease, these analog circuits need to be continuously iterated and the design difficulty is increasing. One solution is to reduce the number of analog circuit modules in the ADC. An ADC based on voltage-controlled oscillator (VCO) is Figure 1 As shown, it uses a voltage-controlled oscillator to convert the amplitude information of the input signal into frequency information, and then uses a counter to convert the frequency information into time information. The time information is represented by a digital binary code, which is digital information, thus realizing the analog-to-digital conversion from analog signal to digital signal. The voltage-controlled oscillator and the counter can both be constructed with simple digital modules. However, there are some problems with this structure: the output of the voltage-controlled oscillator is connected to a large counter, which has a large load and will fluctuate over time, so the output frequency of the voltage-controlled oscillator will no longer be a constant linearly related to the input signal amplitude, which will bring great nonlinearity; in addition, the input and output of the voltage-controlled oscillator usually have a narrow range of approximately linear changes, and if an analog-to-digital converter needs to be designed, only this linear range can be used, resulting in a small input amplitude range; at the same time, since the input end of the voltage-controlled oscillator is directly connected to the input analog signal, it is not easy to determine the time node when the frequency of the output signal of the voltage-controlled oscillator reaches stability, which brings difficulties to the design of the subsequent counter control clock. Summary of the invention

[0004] In view of the above problems, the present invention proposes a method for realizing analog-to-digital conversion based on a phase-locked loop.

[0005] The technical solution of the present invention is as follows:

[0006] A method for implementing analog-to-digital conversion based on a phase-locked loop, the steps of which include:

[0007] 1) Inputting an analog signal Analog Input into a sampling and holding circuit module S / H, the amplitude of the analog signal Analog Input is αV, the output end of the sampling and holding circuit module S / H is connected to the input end of a voltage-controlled oscillator VCO1, the output signal frequency of the voltage-controlled oscillator VCO1 is in a positive linear relationship with the input signal amplitude, and outputs a fixed frequency signal;

[0008] 2) The output end of the voltage controlled oscillator VCO1 is connected to the output end of the calibration cell, and the frequency of the output signal of the voltage controlled oscillator VCO1 is fixed to β Hz, β = K vco α, where K vco =25MHz / V;

[0009] 3) The output end of the calibration cell is connected to the input end of the phase-locked loop circuit module PLL, and the phase-locked loop circuit module PLL is used to lock the frequency β Hz of the output signal to β·γ Hz, where γ is a constant value;

[0010] 4) The output end of the phase-locked loop circuit module PLL is connected to the input end of the counter module Counter, and the counter module Counter uniquely outputs a binary count δ in a unit time t as a digital output DigitalOutput.

[0011] Furthermore, the range of αV is between 0.5V and 2.5V.

[0012] Furthermore, the input analog signal Analog Input is a sinusoidal waveform signal or a ramp analog signal.

[0013] Further, the phase-locked loop circuit module PLL includes a phase frequency detector module PFD, a charge pump module CP, a low-pass filter module LPF, a voltage-controlled oscillator module VCO2 and a frequency divider module Divider, wherein a first input end of the phase frequency detector module PFD serves as an input end of the phase-locked loop circuit module PLL, an output end of the phase frequency detector module PFD is connected to an input end of the charge pump module CP, an output end of the charge pump module CP is connected to an input end of the low-pass filter module LPF, an output end of the low-pass filter module LPF is connected to an input end of the voltage-controlled oscillator module VCO2, an input end of the frequency divider module Divider is connected to an output end of the voltage-controlled oscillator module VCO2, a second input end of the phase frequency detector module PFD is connected to an output end of the frequency divider module Divider, and an output end of the frequency divider module Divider serves as an output end of the phase-locked loop circuit module PLL.

[0014] Furthermore, the γ value is the same as the frequency division number of the frequency divider Divider.

[0015] Furthermore, the phase-locked loop module is a charge pump phase-locked loop or other types of phase-locked loops.

[0016] Furthermore, the VCO2 uses a LOOP-VCO structure to generate multiple Phases with consistent frequencies and different phases, and then outputs one or more of the Phases to an equal number of counter modules Counter through a divider module Divider, and finally accumulates all the count values ​​of one or more counter modules Counter within a unit time t to obtain a final count output.

[0017] The technical effects of the present invention are:

[0018] First, compared with the traditional analog-to-digital conversion method, the present invention adds a phase-locked loop in the circuit, and by reasonably adjusting the input-output relationship and correcting the signal between the voltage-controlled oscillator and the phase-locked loop circuit, the linearity of the overall circuit can be guaranteed within a larger input range, and the circuit has higher stability.

[0019] Second, the existing analog-to-digital converter based on voltage-controlled oscillator usually requires a larger counter, while the present invention relieves the pressure of the subsequent counter by means of the frequency divider in the phase-locked loop, thereby obtaining a more digital circuit;

[0020] Third, after the present invention adds a phase-locked loop to the circuit, the time when the output signal frequency reaches stability can be accurately determined by observing the input signal voltage change of the voltage-controlled oscillator in the phase-locked loop, and then the counter can be controlled to start working; the resolution of the analog-to-digital conversion theoretically depends only on the clock frequency of the counter. The higher the clock frequency, the higher the resolution, which is easier to control and estimate. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0022] Figure 1 A schematic diagram of an analog-to-digital converter based on a voltage-controlled oscillator in the prior art;

[0023] Figure 2 It is a schematic diagram of the analog-to-digital conversion structure based on a phase-locked loop of the present invention;

[0024] Figure 3 The waveform diagram of the digital signal Digital Output outputted when a sinusoidal signal Analog Input with a bias of 1.5V and an amplitude of 1V is inputted in a specific embodiment of the present invention;

[0025] Figure 4 It is a waveform diagram of the digital signal Digital Output output when a sinusoidal signal AnalogInput with a bias of 1.5V and an amplitude of 0.00005V is input according to a specific embodiment of the present invention;

[0026] Figure 5 This is a waveform diagram of the digital signal Digital Output output when the ramp signal Analog Input with an amplitude range of 0.5V to 2.5V is input according to a specific embodiment of the present invention. DETAILED DESCRIPTION

[0027] The present invention will be further clearly and completely described below through specific embodiments in conjunction with the accompanying drawings.

[0028] The present invention is based on the phase-locked loop analog-to-digital conversion implementation method, such as Figure 2 As shown, the steps include:

[0029] 1) Inputting an analog signal Analog Input into a sampling and holding circuit module S / H, the amplitude of the analog signal Analog Input is αV, αV is 0.5V to 2.5V, the output end of the sampling and holding circuit module S / H is connected to the input end of a voltage-controlled oscillator VCO1, the output signal frequency of the voltage-controlled oscillator VCO1 is in a positive linear relationship with the input signal amplitude, and outputs a fixed frequency signal;

[0030] 2) The output end of the voltage controlled oscillator VCO1 is connected to the output end of the calibration cell, and the frequency of the output signal of the voltage controlled oscillator VCO1 is fixed to β Hz, β = K vco α, where K vco =25MHz / V;

[0031] 3) The output end of the calibration cell is connected to the input end of the phase-locked loop circuit module PLL, and the phase-locked loop circuit module PLL is used to lock the frequency β Hz of the output signal to β·γ Hz, where γ is a fixed value, such as γ=10 in the embodiment;

[0032] 4) The output end of the phase-locked loop circuit module PLL is connected to the input end of the counter module Counter. The counter module Counter uniquely outputs a binary count δ in a unit time t as a digital output DigitalOutput, where t can be understood as the period of a single conversion, and in this embodiment t is 0.1ms.

[0033] The phase-locked loop circuit module PLL includes a phase frequency detector module PFD, a charge pump module CP, a low-pass filter module LPF, a second voltage-controlled oscillator module VCO2, and a frequency divider module Divider; wherein, the first input end of the phase frequency detector module PFD serves as the input end of the phase frequency detector module PLL, the input end of the charge pump module CP is connected to the output end of the phase frequency detector module PFD, the input end of the low-pass filter module LPF is connected to the output end of the charge pump module CP, the input end of the second voltage-controlled oscillator module VCO2 is connected to the output end of the low-pass filter module LPF, the input end of the frequency divider module Divider is connected to the output end of the second voltage-controlled oscillator module VCO2, the frequency division number of the frequency divider Divider is γ, the second input end of the phase frequency detector module PFD is connected to the output end of the frequency divider module Divider, and the output end of the frequency divider module Divider serves as the output end of the phase-locked loop circuit module PLL. If the VCO2 uses a LOOP-VCO structure to generate multiple Phases with the same frequency but different phases, then one or more of the Phases are output to an equal number of counter modules Counter through a divider module Divider, and finally the count values ​​of one or more counter modules Counter within a unit time t are all accumulated to obtain a final count output.

[0034] Embodiment 1

[0035] In order to facilitate understanding of the present invention, the DC bias of the input sinusoidal analog signal Analog Input is set to 1.5V and the amplitude is set to 0.5V. The sample-and-hold circuit S / H performs a sample-and-hold operation on the input analog signal and outputs a step-shaped signal. Each step output by the sample-and-hold circuit S / H can be equivalent to a DC input in the holding time interval. Figure 3 The following is an input and output waveform diagram of a specific embodiment of the present invention in a Simulink simulation environment when a sinusoidal signal with a bias of 1.5V and an amplitude of 1V is input. The waveform diagram above is the output waveform of the sample-and-hold circuit S / H, and the waveform diagram below is the output waveform of the counter Counter, wherein the count value at each peak position is the output digital code corresponding to the input analog signal at that moment. When the input amplitude range is a sinusoidal signal of 0.5V to 2.5V, 27 samples are taken for one cycle, and the output digital code basically restores the sinusoidal waveform. It can be seen that the overall amplitude range of the input sinusoidal analog signal Analog Input has a larger input analog voltage amplitude: 0.5V to 2.5V. If the DC bias of the input sinusoidal analog signal Analog Input is 1.5V and the amplitude is 0.00005V, the overall amplitude range is 1.49995V to 1.50005V, the sample-and-hold circuit S / H performs a sample-and-hold operation on the input analog signal, and outputs a step-shaped signal, which can be equivalent to a DC input in the holding time interval. Figure 4 The input and output waveforms of the specific embodiment of the present invention under the Simulink simulation environment when a sine signal with a 1.5V bias and an amplitude of 0.00005V is input, the waveform above is the output waveform of the sample and hold circuit S / H, and the waveform below is the output waveform of the counter Counter, where the count value at each peak position is the output digital code corresponding to the input analog signal at that moment. When the input amplitude range is 1.49995V to 1.50005V, 27 samples are taken for one cycle, and the output digital code basically restores the sine waveform. The results show that it has a high resolution:

[0036] Embodiment 2

[0037] The ramp analog signal Analog Input with an input amplitude range of 0.5V to 2.5V is input, and the sample-and-hold circuit S / H performs a sample-and-hold operation on the input signal and outputs a step-shaped signal, which can be equivalent to a DC input in the holding time interval. Figure 5The following is an input and output waveform diagram of a ramp signal with an amplitude range of 0.5V to 2.5V in a specific embodiment of the present invention under the Simulink simulation environment. The waveform diagram above is the output waveform of the sample and hold circuit S / H, and the waveform diagram below is the output waveform of the counter Counter, wherein the count value at each peak position is the output digital code corresponding to the input analog signal at that moment. It can be seen that when the amplitude of the input analog signal is 0.5V, 0.6V, 0.7V, 0.8V, 0.9V, 1.0V, 1.1V, 1.2V, 1.3V, 1.4V, 1.5V, 1.6V, 1.7V, 1.8V, 1.9V, 2.0V, 2.1V, 2.2V, 2.3V, 2.4V, 2.5V, the output digital code of the analog-to-digital converter based on the phase-locked loop is (Since the simulator records data to three decimal places, the latter part is discarded to increase the error tolerance rate) They are: 1250, 1490, 1740, 1989, 2239, 2488, 2737, 2987, 3235, 3487, 3736, 3986, 4233, 4483, 4733, 4979, 5233, 5480, 5731, 5980, 6229. Calculate the increment of the digital code output each time, which is: 240, 250, 249, 250, 249, 249, 250, 248, 252, 249, 250, 247, 250, 250, 246, 254, 247, 251, 249, 249. The results show that it has good linearity in the amplitude range of 0.5V to 2.5V.

[0038] Finally, it should be noted that the purpose of publishing the embodiments is to help further understand the present invention, but those skilled in the art can understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the contents disclosed in the embodiments, and the scope of protection claimed by the present invention shall be based on the scope defined in the claims.

Claims

1. A method for implementing analog-to-digital conversion based on a phase-locked loop, the steps comprising: 1) Inputting an analog signal Analog Input into a sampling and holding circuit module S / H, the amplitude of the analog signal Analog Input is αV, the output end of the sampling and holding circuit module S / H is connected to the input end of a voltage-controlled oscillator VCO1, the output signal frequency of the voltage-controlled oscillator VCO1 is in a positive linear relationship with the input signal amplitude, and outputs a fixed frequency signal; 2) The output end of the voltage controlled oscillator VCO1 is connected to the output end of the calibration cell, and the frequency of the output signal of the voltage controlled oscillator VCO1 is fixed to β Hz, β = K vco α, where K vco =25MHz / V; 3) The output end of the calibration cell is connected to the input end of the phase-locked loop circuit module PLL, and the phase-locked loop circuit module PLL is used to lock the frequency β Hz of the output signal to β·γ Hz, where γ is a constant value; 4) The output end of the phase-locked loop circuit module PLL is connected to the input end of the counter module Counter, and the counter module Counter uniquely outputs a binary count δ in a unit time t as a digital output Digital Output.

2. The method for implementing analog-to-digital conversion based on a phase-locked loop as claimed in claim 1, characterized in that: The range of αV is between 0.5V and 2.5V.

3. The method for implementing analog-to-digital conversion based on a phase-locked loop as claimed in claim 1, characterized in that: The input analog signal Analog Input is a sinusoidal waveform signal or a ramp analog signal.

4. The method for implementing analog-to-digital conversion based on a phase-locked loop as claimed in claim 1, characterized in that: The phase-locked loop circuit module PLL includes a phase frequency detector module PFD, a charge pump module CP, a low-pass filter module LPF, a voltage-controlled oscillator module VCO2 and a frequency divider module Divider, wherein the first input end of the phase frequency detector module PFD serves as the input end of the phase-locked loop circuit module PLL, the output end of the phase frequency detector module PFD is connected to the input end of the charge pump module CP, the output end of the charge pump module CP is connected to the input end of the low-pass filter module LPF, the output end of the low-pass filter module LPF is connected to the input end of the voltage-controlled oscillator module VCO2, the input end of the frequency divider module Divider is connected to the output end of the voltage-controlled oscillator module VCO2, the second input end of the phase frequency detector module PFD is connected to the output end of the frequency divider module Divider, and the output end of the frequency divider module Divider serves as the output end of the phase-locked loop circuit module PLL.

5. The method for implementing analog-to-digital conversion based on a phase-locked loop as claimed in claim 4, characterized in that: The γ value is the same as the frequency division number of the frequency divider Divider.

6. The method for implementing analog-to-digital conversion based on a phase-locked loop as claimed in claim 4, characterized in that: The phase-locked loop module is a charge pump phase-locked loop or other types of phase-locked loops.

7. The method for implementing analog-to-digital conversion based on a phase-locked loop as claimed in claim 4, characterized in that: The VCO2 uses a LOOP-VCO structure to generate multiple Phases with consistent frequencies and different phases, and then outputs one or more of the Phases to equal counter modules Counter through a divider module Divider. Finally, all count values ​​of one or more counter modules Counter within a unit time t are accumulated to obtain a final count output.

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