CTDSM circuit capable of compensating overshoot loop delay in any period

Abstract

The invention belongs to the technical field of analog integrated circuits, and particularly relates to a CTDSM circuit capable of compensating overshoot loop delay in any period. A direct feedback loop is introduced into each output end of an m-channel TI ADC, code words generated by each channel are ranked from high to low according to the quantization degree, and then the code words are selectively fed back to the input end of the TI ADC through unit period delay which is gradually reduced from m to 1, so that overshoot loop delay is compensated, and the frequency of the TI ADC is increased. According to the method, the overshoot loop delay of any period in the CTDSM with the TI ADC as the quantizer can be compensated, and the limitation that only one-period overshoot loop delay can be compensated in an existing scheme is broken through. The method is suitable for the situation that the TI ADC with any number of channels serves as the CTDSM quantizer, the stability of the CTDSM circuit is improved, and support is provided for development of the CTDSM in the high-speed and high-precision field.

Description

Technical Field

[0001] The invention belongs to the technical field of analog integrated circuits, and in particular relates to a CTDSM circuit capable of compensating for any period overshoot loop delay. Background Art

[0002] Continuous-Time Delta-Sigma Modulator (CTDSM) has been widely studied and applied in the field of analog integrated circuit technology due to its high precision and high bandwidth. The quantizer in CTDSM is usually implemented by cascading ADC and DAC. Due to the resolution limitation of the quantizer, it takes some time to complete the conversion, resulting in a delay in the output sequence. The DAC works after the ADC, so it can only be driven by the clock signal later, further increasing the delay. The excess loop delay (ELD) in CTDSM will cause the circuit to become unstable.

[0003] Assume a non-return-to-zero (NRZ) coded first-order CTDSM with a value of t d The overshoot loop delay of the circuit is shown in the attached Figure 1 As shown, the noise transfer function (NTF) of the CTDSM circuit can be expressed as:

[0004]

[0005] It can be seen that compared with the CTDSM without overshoot loop delay, this circuit has two more poles, and the pole positions are related to td. d The larger the value, the more unstable the circuit is. d When it is greater than one cycle, the circuit is in an unstable state.

[0006] Regarding the compensation problem of overshoot loop delay, a design method for direct feedback path around the quantizer is proposed in the literature. Figure 2 This design method introduces a feedback path at the output of the quantizer and also passes through t d The delay to the quantizer input is introduced by introducing a feedback path to offset the overshoot loop delay.

[0007] However, the above scheme is only applicable to the case where the compensation overshoot loop delay is less than one cycle. If CTDSM uses a time-interleaved (TI) ADC with multi-channel input as its quantizer, the overshoot loop delay will be greater than 1 cycle. If the above quantizer direct feedback compensation scheme is used to compensate for the overshoot loop delay of the TIADC, the incomplete quantized signal will be fed back to the input, resulting in instability of the overall circuit; if the TIADC with 2 channels is used to compensate for the overshoot loop delay, the input of the quantizer is:

[0008] D[n]=X[n]-Y[n-1]-Y[n-2]

[0009] Wherein, D[n] is the quantizer input signal of the nth period, X[n] is the discretized signal of the first-order CTDSM input signal of the nth period after passing through the loop filter, and Y[n] is the quantizer output signal of the nth period.

[0010] It can be seen that in the nth cycle, the quantizer output values ​​of the n-1th cycle and the n-2th cycle need to be fed back, but for the 2-channel TIADC, the n-1th cycle is still in the quantization stage and cannot feed back the correct output signal, resulting in errors in the overall circuit. This limits the development of CTDSM in the field of high speed and high precision, so how to compensate for the overshoot loop delay greater than one cycle is an urgent problem to be solved in the research of high-performance CTDSM. Summary of the invention

[0011] In view of the above problems or shortcomings, the present invention provides a CTDSM circuit that can compensate for any period overshoot loop delay, which is suitable for the case where a TI ADC with any number of channels is used as a CTDSM quantizer. By introducing multiple feedback paths that meet the design conditions from the output of the quantizer to the input of the quantizer, the overshoot loop delay is compensated.

[0012] A CTDSM circuit that can compensate for any periodic overshoot loop delay consists of the following four modules: Figure 3 As shown, it includes module 001, module 002, module 003 and module 004.

[0013] If the number of channels of the TI ADC used as the CTDSM quantizer is m, then for the CTDSM, an overshoot loop delay of m cycles will be generated. According to the working principle of the TIADC, when sampling is performed in the mth cycle, quantization has already begun in the previous m-1 cycles, which means that the signal sampled in the previous m-1 cycles already has codeword output.

[0014] The module 001 includes three parts: an adder ADDER0, a loop filter and a sampling switch connected in sequence. The adder ADDER0 is used as the input of the module 001, and is connected to the input signal X of the entire CTDSM circuit and the output signal D1 of the module 004; the output of the sampling switch is used as the output of the module 001 and is connected to the input end of the module 002. The module 001 performs a differential operation on the input signals X and D1 through the adder ADDER0, and after loop filtering, discretization is achieved through the sampling switch.

[0015] The module 002 is composed of m adders, which are cascaded sequentially from ADDER1 to ADDERm. The input of adder ADDER1 is connected to the output (sampling switch) of module 001 and the output signal D1 of module 004, the input of adder ADDER2 is connected to the output of ADDER1 and the output signal D2 of module 004, ... the input of adder ADDERm is connected to the output of ADDERm-1 and the output signal D2 of module 004. m ; The output of adder ADDERm is connected to the input of module 003 as the output of module 002.

[0016] The module 003 is composed of m channels of TIADC and a multi-channel selector MCS.

[0017] The TI ADC with m channels is divided into channels CH1-CHm, and the outputs MSB1 to MSB correspond one by one. m m-way signal.

[0018] The multi-channel selector MCS sorts the sub-ADCs of each channel in the TI ADC according to the quantization degree from high to low. The signal of the channel CH1 with the highest quantization degree, i.e., the signal that has been fully quantized, is used as the first output signal MSB1 of module 003. The remaining channels are used as the second output signal MSB2 to the mth output signal MSB of module 003 in order of quantization degree from high to low. m And the first output signal MSB1 of module 003 is used as the output signal Y of the entire CTDSM circuit.

[0019] The specific principle is: set the current working cycle to be the m+1th working cycle, and the working cycle includes the sampling cycle and quantization cycle of the CTDSM circuit. According to the working principle of TI ADC, when sampling is performed in the m+1th working cycle, the sub-ADC of channel CH1 can output a fully quantized signal, while the sub-ADCs from channel CH2 to channel CHm are still in the quantization stage and can only output a part of the codeword in the m+1 cycle. The function of module 003 is to sort the sub-ADCs of each channel in TIADC from high to low according to the degree of quantization through the multi-channel selector in the current working cycle, i.e., the m+1th cycle. The signal of channel CH1 with the highest degree of quantization, i.e., the signal that has been fully quantized, is used as the first output signal MSB1 of module 003, and the remaining channels are used as the second output signal MSB2 of module 003 to the mth output signal MSB in order from high to low according to the degree of quantization. m And the first output signal MSB1 of module 003 is used as the output signal Y of the entire CTDSM circuit.

[0020] The module 004 is composed of m independent feedback delay loops, and the number of delay cycles of each loop decreases from m to 1. Its input is connected to the module 003 from MSB1 to MSB m m-way output, signal MSB1 to MSB m After the delay of m feedback delay loops corresponding to each other, the corresponding (MSB m Corresponding to D m ) signal D1 to D m ; At the same time, the first output signal D1 of module 004 is also connected to the input end of module 001 (adder ADDER0).

[0021] The function of module 004 is to convert the input signal from MSB1 to MSB. m , the number of delay cycles is decreased from m to 1 in a one-to-one correspondence, and the output signal D1 to D m .

[0022] Furthermore, the module 002 performs a differential operation on the output signal of the module 001 and the D1 signal to obtain the output of ADDER1, and then performs a differential operation on the output signal of ADDER1 and the D2 signal to obtain the output of ADDER2. The above steps are repeated to obtain the output of ADDERm. The output signal of ADDERm is the output signal of the module 002, which is connected to the input of the module 003.

[0023] Furthermore, the loop filter adopts a cascade integrator CIFB with feedback or a cascade integrator CIFF with feedforward.

[0024] Furthermore, the multiplexer MCS is composed of m multiplexers MUX connected in parallel, as shown in the attached diagram. Figure 4 shown.

[0025] In summary, the present invention introduces a direct feedback loop at each output end of the m-channel TI ADC, sorts the codewords generated by each channel from high to low by quantization degree, and then selectively feeds back to the TI ADC input end through a unit cycle delay decreasing from m to 1 to compensate for the overshoot loop delay. This method can compensate for the overshoot loop delay of any cycle in the CTDSM with TIADC as the quantizer, breaking through the limitation that the existing scheme can only compensate for one cycle of overshoot loop delay. The present invention is applicable to the case where TI ADC with any number of channels is used as the CTDSM quantizer, improves the stability of the CTDSM circuit, and provides support for the development of CTDSM in the field of high speed and high precision. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 For d Schematic diagram of a first-order CTDSM circuit with overshoot loop delay;

[0027] Figure 2 A schematic diagram of a first-order CTDSM circuit with overshoot loop delay using a quantizer direct feedback compensation scheme;

[0028] Figure 3 A schematic diagram of the compensation scheme of the present invention when an m-channel TIADC is used as a CTDSM quantizer;

[0029] Figure 4 This is a schematic diagram of the multi-channel selector circuit in module 003;

[0030] Figure 5 is a circuit block diagram of a 2-cycle overshoot loop delay compensation in a CTDSM in an embodiment;

[0031] Figure 6 FIG. 4 is a schematic diagram of a loop filter structure used in an embodiment. DETAILED DESCRIPTION

[0032] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.

[0033] A CTDSM circuit that can compensate for any cycle overshoot loop delay is shown in the attached figure. Figure 5As shown in FIG. 1 , the CTDSM in this embodiment is based on a 2-channel time-interleaved noise-shaping successive approximation analog-to-digital converter (TI NSSAR ADC) with a 2-cycle overshoot loop delay. The loop filter architecture used by the CTDSM is a cascade integrator CIFF with a feedforward structure. The system block diagram is shown in FIG. Figure 6 shown.

[0034] First, assume that the input of the CTDSM circuit is signal X, the output of the CTDSM circuit is Y, the input of the TI NSSARADC is signal D, and the output of the TI NSSARADC is MSB+LSB.

[0035] By attaching Figure 5 We can get:

[0036] Y=MSB+LSB-Z -1 LSB

[0037] At the same time, it can be seen that in the first-order CTDSM, the input signal has an overshoot loop delay t d The corresponding expression for sampling is:

[0038]

[0039] Where τ is the number of delayed cycles, which is a positive integer.

[0040] According to the attached Figure 5 , we can get formula 1 as:

[0041]

[0042] The formula 2 is:

[0043]

[0044] (DY)Z -1 +D·(1-Z -1 )+E(1-Z -1 )-Z -1 (1-Z -1 )LSB=Y(1-Z -1 )

[0045] D+E(1-Z -1 )-Z -1 (1-Z -1 )LSB=Y (2)

[0046] Substituting equation 1 into equation 2, we get:

[0047] Z -3 XZ -2YZ -1 (1-Z -1 )[MSB+LSB-Z -1 LSB]+(1-Z -1 ) 2 E=(1-Z -1 )Y

[0048] because:

[0049] Y=MSB+LSB-Z -1 LSB

[0050] but:

[0051] Z -3 XZ -2 YZ -1 (1-Z -1 )Y-(1-Z -1 ) 2 E=(1-Z -1 )Y

[0052] Y=Z -3 X+(1-Z -1 ) 2 E

[0053] Finally, the signal transfer function of the CTDSM circuit is Z -3 , the noise transfer function is (1-Z -1 ) 2 .

[0054] It can be seen from the above embodiments that the present invention selectively feeds back the codewords generated by each channel to the input end of the quantizer through a direct feedback loop to compensate for the overshoot loop delay. This method can compensate for the overshoot loop delay of any period in the CTDSM with TIADC as the quantizer, breaking through the limitation that the existing scheme can only compensate for the overshoot loop delay of one period; it is suitable for the situation where TI ADC with any number of channels is used as the CTDSM quantizer, improves the stability of the CTDSM circuit, and provides support for the development of CTDSM in the field of high speed and high precision.

Claims

1. A CTDSM circuit capable of compensating for any periodic overshoot loop delay, characterized in that: It includes four modules: module 001, module 002, module 003 and module 004; The module 001 comprises three parts, namely, an adder ADDER0, a loop filter and a sampling switch, which are connected in sequence; the input of the adder ADDER0 is used as the input of the module 001, and is connected to the input signal X of the entire CTDSM circuit and the output signal D1 of the module 004; the output of the sampling switch is used as the output of the module 001 and is connected to the input end of the module 002; the module 001 performs a differential operation on the input signals X and D1 through the adder ADDER0, and after the loop filtering, realizes discretization through the sampling switch; The module 002 is composed of m adders, which are cascaded sequentially from ADDER1 to ADDERm; wherein the input of adder ADDER1 is connected to the output of module 001 and the output signal D1 of module 004, the input of adder ADDER2 is connected to the output of ADDER1 and the output signal D2 of module 004, ... the input of adder ADDERm is connected to the output of ADDERm-1 and the output signal D2 of module 004. m The output of adder ADDERm is connected to the input of module 003 as the output of module 002; The module 003 is composed of m channels of TIADC and a multi-channel selector MCS; The m-channel TIADC is divided into channels CH1-CHm, and the outputs MSB1 to MSB correspond to each other. m m-way signal; The multi-channel selector MCS sorts the sub-ADCs of each channel in the TI ADC according to the quantization degree from high to low. The signal of the channel CH1 with the highest quantization degree, i.e., the signal that has been fully quantized, is used as the first output signal MSB1 of module 003. The remaining channels are used as the second output signal MSB2 to the mth output signal MSB of module 003 in order of quantization degree from high to low. m And the first output signal MSB1 of module 003 is used as the output signal Y of the entire CTDSM circuit; The module 004 is composed of m independent feedback delay loops, and the delay period of each loop decreases from m to 1; its input is connected to the module 003 from MSB1 to MSB in a one-to-one correspondence. m m-way output, signal MSB1 to MSB m After the corresponding m feedback delay loops, the corresponding signals D1 to D m , MSB m Corresponding to D m ; At the same time, the first output signal D1 of module 004 is also connected to the input end of module 001.

2. The CTDSM circuit capable of compensating for any periodic overshoot loop delay as claimed in claim 1, characterized in that: The TIADC uses TI NSSAR ADC.

3. The CTDSM circuit capable of compensating for any periodic overshoot loop delay as claimed in claim 1, characterized in that: The module 002 performs a differential operation on the output signal of module 001 and the D1 signal to obtain the output of ADDER1, and then performs a differential operation on the output signal of ADDER1 and the D2 signal to obtain the output of ADDER2. The above steps are repeated to obtain the output of ADDERm. The output signal of ADDERm is the output signal of module 002.

4. The CTDSM circuit capable of compensating for any periodic overshoot loop delay as claimed in claim 1, characterized in that: The loop filter adopts a cascade integrator CIFB with feedback or a cascade integrator CIFF with feedforward.

5. The CTDSM circuit capable of compensating for any periodic overshoot loop delay as claimed in claim 1, characterized in that: The multiplexer MCS is composed of m multiplexers MUX connected in parallel.

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