Display image 90-degree rotation control method and device, equipment and storage medium
By controlling the alternating cache reading and writing of the video line data in DDR, and the writing of a specific order, combined with the reading and rotation of the rotating unit, the problem of decreased DDR utilization rate is solved, and the high -definition image rotation is achieved. Quality and reliability.
Patent Information
- Application Number
- CN202411475029.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-22
- Publication Date
- 2025-01-24
AI Technical Summary
The prior art realizes the image rotation of 90 degrees in DDR, resulting in a decrease in the utilization rate of DDR. In order to solve this problem, the prior art usually reduces the output frame rate or uses YCbCr4:2:2 and other means, resulting in the video picture not being Fluid or color information is lost.
By controlling the DDR input cache module to alternate the cache read and write the video line data, control the DDR writing address calculation module alternately in accordance with a specific order, control the DDR reading address calculation module The output cache module alternate cache read and write to achieve a 90 -degree rotation of the image.
A 90 -degree rotation of high -definition images was effectively carried out by a single DDR, avoiding the loss of effective information of the video, improving the display quality, and improving reliability.
Smart Images
Figure CN119363902A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of image processing technology, and in particular to a method, device, equipment and storage medium for controlling 90° rotation of a displayed image. Background Art
[0002] In video display application technology, 90-degree rotation of the displayed image is a relatively important function. It is a common practice to realize 90-degree rotation of the image through DDR. Since 90-degree rotation will inevitably perform non-continuous reading and writing of DDR, the utilization rate of DDR is reduced. In the prior art, the problem of reduced DDR utilization is solved by reducing the output frame rate or using YCbCr4:2:2 and other means to reduce the video bandwidth. However, this method will lose effective information, which is likely to cause the video picture to be not smooth or the color information to be lost.
[0003] Therefore, how to reliably and efficiently solve the problem of realizing 90° rotation control of displayed images based on DDR has become an urgent problem to be solved by technicians in this field. Summary of the invention
[0004] In view of the above defects, the embodiments of the present invention provide a method, device, equipment and storage medium for controlling 90° rotation of a displayed image, so as to solve the problems existing in the prior art.
[0005] In order to solve the above technical problems, an embodiment of the present invention provides a method for controlling a 90° rotation of a displayed image, the method comprising:
[0006] Control the DDR input buffer module to perform alternate buffer reading and writing of input video line data;
[0007] Controlling the DDR write address calculation module to alternately write the video row data according to a specific order;
[0008] Controlling the DDR read address calculation module to read the video row data in sequence in units of one rotation unit;
[0009] Controlling the DDR read address calculation module to rotate the rotation unit until the entire picture is read;
[0010] The DDR output buffer module is controlled to perform alternate buffer reading and writing on the rotated video row data, so as to output the rotated video data.
[0011] Preferably, the controlling the DDR input buffer module to perform alternate buffer reading and writing on the input video line data comprises:
[0012] The DDR input buffer module is configured as a dual-port BLOCKRAM storage structure, each dual-port buffer has a depth of 2 lines, and the dual-port BLOCKRAM storage structure is used to alternately cache read and write input video line data.
[0013] Preferably, it is characterized in that the controlling the DDR input buffer module to perform alternate buffer reading and writing on the input video line data further comprises:
[0014] Control the dual-port BLOCKRAM storage structure to synchronously read multiple lines of cache;
[0015] Controlling the dual-port BLOCKRAM storage structure to combine the multiple lines of cache into a length that satisfies a preset number of DDR bursts;
[0016] The dual-port BLOCKRAM storage structure is controlled to reassemble the video line data in the input buffer.
[0017] Preferably, the controlling the DDR write address calculation module to alternately write the video row data according to a specific order comprises:
[0018] Control the DDR write address calculation module to use four variables WR_ADDR0, WR_ADDR1, WR_ADDR2, and WR_ADDR3 to store the frequency row data; wherein the four variables correspond to the addresses of multiple preset row data to be written into the DDR respectively;
[0019] Taking the preset pixel data in one rotation unit as a combination, the writing of one rotation unit is completed through a preset number of address bursts;
[0020] The DDR write address calculation module is controlled to alternately complete the storage of the remaining video line data according to the above storage order, so as to realize the mapping between the original address of the video line data and the DDR address.
[0021] Preferably, the controlling the DDR read address calculation module to sequentially read the video line data in units of one rotation unit comprises:
[0022] The preset column data is read sequentially from top to bottom in units of one rotation unit;
[0023] After the DR read address calculation module has finished reading a preset number of rotation units in a continuous address manner, a non-continuous address read operation is performed.
[0024] Preferably, in the preset number of address bursts, the preset number is:
[0025] (Input screen width / width of one rotation unit)*number of bursts of one rotation unit.
[0026] Preferably, the controlling DDR output buffer module to perform alternate buffer reading and writing on the rotated video row data to achieve output of the rotated video data comprises:
[0027] The DDR output buffer module is configured as a dual-port BLOCKRAM storage structure, each dual-port buffer has a depth of 2 lines, and the dual-port BLOCKRAM storage structure is used to alternately cache read and write output video line data.
[0028] In order to solve the above technical problems, an embodiment of the present invention provides a 90° rotation control device for a displayed image, the device comprising:
[0029] DDR input buffer module, used for alternate buffering reading and writing of input video line data;
[0030] A DDR write address calculation module, used for alternately writing the video row data according to a specific order;
[0031] A DDR read address calculation module, used to read the video line data in units of a rotation unit in sequence, and rotate the rotation unit until the entire picture is read;
[0032] The DDR output buffer module is used to perform alternate buffer reading and writing on the rotated video row data to realize output of the rotated video data.
[0033] To solve the above technical problems, an embodiment of the present invention provides a 90° rotation control device for a displayed image, comprising: at least one processor, at least one memory, and computer program instructions stored in the memory. When the computer program instructions are executed by the processor, the method of the first aspect in the above embodiment is implemented.
[0034] To solve the above technical problem, an embodiment of the present invention provides a storage medium on which computer program instructions are stored. When the computer program instructions are executed by a processor, the method of the first aspect in the above embodiment is implemented.
[0035] In summary, the embodiments of the present invention provide a method, device, equipment and storage medium for controlling the 90° rotation of a display image. The present invention controls the DDR input cache module to perform alternate cache reading and writing of the input video row data; controls the DDR write address calculation module to perform alternate writing of the video row data according to a specific order; controls the DDR read address calculation module to read the video row data in units of a rotation unit in sequence; controls the DDR read address calculation module to rotate the rotation unit until the entire picture is read; controls the DDR output cache module to perform alternate cache reading and writing of the rotated video row data, thereby outputting the rotated video data. Therefore, the present invention can realize 90-degree rotation control of high-definition images through a single DDR without losing effective video information, thereby improving display quality and having high reliability. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] In order to more clearly illustrate the technical solution of the embodiment of the present invention, the following briefly introduces the drawings required for use in the embodiment of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0037] Figure 1 The figure is a flow chart of a method for controlling a 90° rotation of a displayed image according to an embodiment of the present invention.
[0038] Figure 2 It is a flow chart of controlling a DDR input buffer module to perform alternate buffer reading and writing on input video line data according to an embodiment of the present invention.
[0039] Figure 3 Schematic diagram of a combination method for recombining data in an input buffer according to an embodiment of the present invention
[0040] Figure 4 It is a flow chart of controlling the DDR write address calculation module to alternately write the video row data according to a specific order according to an embodiment of the present invention.
[0041] Figure 5 It is a mapping diagram of the relationship between an image and a DDR row address according to an embodiment of the present invention.
[0042] Figure 6 It is a flow chart of an embodiment of the present invention for controlling a DDR read address calculation module to sequentially read the video row data in units of a rotation unit.
[0043] Figure 7 It is a schematic diagram of a rotation method of a rotation unit according to an embodiment of the present invention.
[0044] Figure 8It is a schematic diagram of the principle of alternately caching and reading and writing the rotated video row data by a DDR output buffer module according to an embodiment of the present invention.
[0045] Fig. 9 It is a schematic structural diagram of a display image 90° rotation control device according to an embodiment of the present invention.
[0046] Fig.10 It is a schematic structural diagram of a display image 90° rotation control device according to an embodiment of the present invention. DETAILED DESCRIPTION
[0047] The features and exemplary embodiments of various aspects of the present invention will be described in detail below. In order to make the purpose, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and Examples. It should be understood that the specific embodiments described herein are only configured to explain the present invention and are not configured to limit the present invention. For those skilled in the art, the present invention can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present invention by illustrating examples of the present invention.
[0048] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.
[0049] See also Figure 1 , Figure 1 A method for controlling a 90° rotation of a displayed image is provided in the present application, and the method comprises the following steps:
[0050] S1, control the DDR input buffer module to perform alternate buffering reading and writing of input video line data;
[0051] Specifically, in this embodiment, the DDR input buffer module is set to double buffer or circular buffer mode, and the DDR write address calculation module can process the cached data while reading new video line data. This alternating read and write method can ensure the continuity and real-time performance of data processing and avoid processing delays caused by waiting for data.
[0052] S2, controlling the DDR write address calculation module to alternately write the video row data according to a specific order;
[0053] Specifically, in this embodiment, the DDR write address calculation module calculates and allocates addresses according to a preset specific order (such as WR_ADDR0, WR_ADDR1, WR_ADDR2, WR_ADDR3) to ensure that the video line data is written into the DDR in order. Therefore, the present application ensures the orderliness of data writing, avoids data confusion, and improves the memory utilization and writing speed.
[0054] S3, controlling the DDR read address calculation module to read the video row data in sequence in units of one rotation unit;
[0055] Specifically, in this embodiment, the DDR read address calculation module performs address calculation according to a rotation unit (e.g., 4x4 pixels) to read data from the DDR. Therefore, the present application ensures the integrity of data reading and facilitates subsequent data processing, such as image rotation or scaling.
[0056] S4, controlling the DDR read address calculation module to rotate the rotation unit until the entire picture is read;
[0057] Specifically, in this embodiment, the DDR read address calculation module not only reads data, but is also used to control each rotation unit to rotate 90 degrees according to an algorithm to meet different display requirements.
[0058] S5. Control the DDR output buffer module to perform alternate buffer reading and writing on the rotated video row data to achieve output of the rotated video data.
[0059] Specifically, in this embodiment, the DDR output buffer module is set as a double buffer or circular buffer mechanism, which is used to cache the rotated video line data and output it alternately for further processing or display. Therefore, the present application ensures the stable output of the rotated data, reduces the output delay, and improves the response speed of the entire system.
[0060] In summary, the present application provides a method for controlling the 90° rotation of a display image. In this solution, the DDR input cache module is controlled to perform alternate cache reading and writing of the input video line data; the DDR write address calculation module is controlled to perform alternate writing of the video line data according to a specific order; the DDR read address calculation module is controlled to read the video line data in units of a rotation unit in sequence; the DDR read address calculation module is controlled to rotate the rotation unit until the entire picture is read; the DDR output cache module is controlled to perform alternate cache reading and writing of the rotated video line data to realize the output of the rotated video data. Therefore, the present invention can realize the 90-degree rotation control of high-definition images through a single DDR without losing effective video information, thereby improving display quality and having high reliability.
[0061] Based on the above embodiments:
[0062] Please refer to Figure 2 , Figure 2 The present application provides a flow chart for controlling a DDR input buffer module to perform alternate buffering reading and writing of input video line data.
[0063] As a preferred embodiment, the controlling the DDR input buffer module to perform alternate buffer reading and writing on the input video line data comprises:
[0064] The DDR input buffer module is configured as a dual-port BLOCKRAM storage structure, each dual-port buffer has a depth of 2 lines, and the dual-port BLOCKRAM storage structure is used to alternately cache read and write input video line data.
[0065] Specifically, in this embodiment, the DDR input buffer module is configured as four dual-port BLOCKRAM storage structures. The dual-port BLOCKRAM storage structure enables each storage unit to perform read and write operations from two different ports, thereby improving the flexibility of data processing.
[0066] Specifically, in this embodiment, the depth of each dual-port BLOCKRAM storage structure is 2 rows.
[0067] As a preferred embodiment, it is characterized in that the controlling the DDR input buffer module to perform alternate buffer reading and writing on the input video line data further comprises:
[0068] S11, controlling the dual-port BLOCKRAM storage structure to synchronously read multiple lines of cache;
[0069] S12, controlling the dual-port BLOCKRAM storage structure to combine the multiple cache lines into a length that satisfies a preset number of DDR bursts;
[0070] S13, controlling the dual-port BLOCKRAM storage structure to reassemble the video line data in the input buffer.
[0071] Specifically, for a 1080P 60Hz 24-bit signal, each dual-port BLOCKRAM storage structure can store 3840 pixels (because each row of the 1080P resolution has 1920 pixels, each pixel is 24 bits, so one row is 1920*24 bits=3840 bits), thereby avoiding bandwidth waste.
[0072] See also Figure 3 , Figure 3 A schematic diagram of a combination method for recombining data in an input buffer provided in the present application.
[0073] Specifically, in this embodiment, the length of a DDR burst write operation is 128 bits, and the data in the input buffer needs to be reassembled in the following manner: Figure 3 Therefore, the present application can reduce the number of data transmissions on the DDR bus by combining pixel data to match the burst write length of DDR, thereby more efficiently utilizing bandwidth and reducing bandwidth waste.
[0074] Please refer to Figure 4 , Figure 4 The present application provides a flow chart for controlling a DDR write address calculation module to alternately write the video row data according to a specific order.
[0075] Please refer to Figure 5 , Figure 5 A mapping diagram of the relationship between an image and a DDR row address is provided for this application.
[0076] As a preferred embodiment, the controlling the DDR write address calculation module to alternately write the video row data according to a specific order comprises:
[0077] S21, controlling the DDR write address calculation module to use four variables WR_ADDR0, WR_ADDR1, WR_ADDR2, and WR_ADDR3 to store the frequency row data; wherein the four variables correspond to the addresses of multiple preset row data to be written into the DDR respectively;
[0078] Specifically, the DDR write address is stored in four variables WR_ADDR0, WR_ADDR1, WR_ADDR2, and WR_ADDR3. These variables represent the starting addresses of different rows written into DDR. Each variable corresponds to the address of 4 rows of data, covering a total of 16 rows of video data.
[0079] Specifically, when data is written into DDR, it is performed alternately in the order of WR_ADDR0, WR_ADDR1, WR_ADDR2, and WR_ADDR3 until data of all rows are written.
[0080] S22, using the preset pixel data in one rotation unit as a combination, completing the writing of one rotation unit through a preset number of address bursts;
[0081] Specifically, in this embodiment, one rotation unit is composed of 4*4 pixel data, that is, 16 pixels. One rotation unit is written through 3 burst write operations, and 384 bits (16 pixels) are written in 3 bursts.
[0082] S23, controlling the DDR write address calculation module to alternately complete the storage of the remaining video row data according to the above storage order, so as to achieve mapping between the original address of the video row data and the DDR address.
[0083] Specifically, in this embodiment, the address interval of each rotation unit in the DDR is 24 addresses, because each burst write operation occupies 8 addresses, and 3 bursts are 24 addresses.
[0084] Therefore, by using four variables to manage addresses, the present application can simplify the complexity of address calculation and management, making address allocation more orderly; by pre-calculating addresses and writing them according to a fixed pattern, the efficiency of DDR writes can be improved and the time for address calculation can be reduced; through reasonable address intervals and burst write operations, the bandwidth of DDR memory can be maximized and the delay of memory access can be reduced; fixed address structures and burst times help ensure data alignment in memory.
[0085] Please refer to Figure 6 , Figure 6 The present application provides a flow chart for controlling a DDR read address calculation module to sequentially read the video row data in units of a rotation unit.
[0086] Please refer to Figure 7 , Figure 7 A schematic diagram of a rotation method of a rotation unit provided in the present application.
[0087] As a preferred embodiment, the controlling the DDR read address calculation module to sequentially read the video line data in units of one rotation unit comprises:
[0088] S31, sequentially reading the preset column data in a top-down manner with one rotation unit as a unit;
[0089] S32, controlling the DR read address calculation module to perform a non-continuous address read operation after reading a preset number of rotation units in a continuous address manner.
[0090] Specifically, in this embodiment, 4 columns of data are read in sequence from top to bottom in a rotation unit, and the rotation unit is rotated until the current 4 columns are read, and then the next 4 columns are switched to read until the entire picture is read.
[0091] Therefore, this application is carried out with 4 columns of data as a unit. In this unit, the data is read from top to bottom in sequence, and the data of each unit is rotated. After processing the current 4 columns, continue to process the next group of 4 columns until the entire image is processed.
[0092] Specifically, in this embodiment, the number of bursts required for DDR to complete 4-column reading is: (input picture height / height of one rotation unit)*3, and for the 1920x1080 input picture in this example, it is: 1080 / 4*3=810.
[0093] Therefore, the burst number of the present application is equal to the screen height divided by the rotation unit height, multiplied by 3. In a 1920x1080 resolution screen, the height of each rotation unit is 4 pixels, so the burst number is 810.
[0094] Specifically, since the four rotation units of each four columns have been written into continuous addresses during DDR writing, the read address module performs a non-continuous address read operation after reading the four rotation units in a continuous address manner, thereby reducing the utilization rate of the DDR write operation and improving the bandwidth utilization rate of the DDR read operation.
[0095] Specifically, in this embodiment, the interval length of the non-continuous address of the read operation is: (input picture width / width of a rotation unit)*number of bursts of a rotation unit*8. For the 1920x1080 input picture in this example, the non-continuous address interval length is (1920 / 4)*3*8=11520.
[0096] As a preferred embodiment, in the preset number of address bursts, the preset number is:
[0097] (Input screen width / width of one rotation unit)*number of bursts of one rotation unit.
[0098] Please refer to Figure 8 , Figure 8 A schematic diagram of the principle of alternately caching and reading and writing the rotated video row data by a DDR output buffer module provided in the present application.
[0099] As a preferred embodiment, the controlling DDR output buffer module to perform alternate buffer reading and writing on the rotated video row data to realize output of the rotated video data includes:
[0100] The DDR output buffer module is configured as a dual-port BLOCKRAM storage structure, each dual-port buffer has a depth of 2 lines, and the dual-port BLOCKRAM storage structure is used to alternately cache read and write output video line data.
[0101] Please refer to Fig. 9 , Fig. 9 This is a schematic structural diagram of a 90° rotation control device for a display image provided in the present application.
[0102] An embodiment of the present invention provides a device for controlling 90° rotation of a displayed image, the device comprising:
[0103] DDR input buffer module 1, used for alternately buffering and reading and writing input video line data;
[0104] DDR write address calculation module 2, used for alternately writing the video row data according to a specific order;
[0105] The DDR read address calculation module 3 is used to read the video line data in units of a rotation unit in sequence, and rotate the rotation unit until the entire picture is read;
[0106] The DDR output buffer module 4 is used to perform alternate buffering, reading and writing of the rotated video row data to realize output of the rotated video data.
[0107] In addition, combined Figure 1 The display image 90° rotation control method of the embodiment of the present invention described above can be implemented by a display image 90° rotation control device. Fig.10 A schematic diagram of the hardware structure of a display image 90° rotation control device provided by an embodiment of the present invention is shown.
[0108] The display image 90° rotation control device may include a processor 401 and a memory 402 storing computer program instructions.
[0109] Specifically, the processor 401 may include a central processing unit (CPU), or an application specific integrated circuit (ASIC), or may be configured to implement one or more integrated circuits of the embodiment of the present invention.
[0110] Memory 402 may include a large capacity memory for data or instructions. For example, but not limitation, memory 402 may include a hard disk drive (HDD), a floppy disk drive, a flash memory, an optical disk, a magneto-optical disk, a magnetic tape, or a universal serial bus (USB) drive or a combination of two or more of these. In appropriate cases, memory 402 may include a removable or non-removable (or fixed) medium. In appropriate cases, memory 402 may be inside or outside a data processing device. In a specific embodiment, memory 402 is a non-volatile solid-state memory. In a specific embodiment, memory 402 includes a read-only memory (ROM). In appropriate cases, the ROM may be a mask-programmed ROM, a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), an electrically rewritable ROM (EAROM) or a flash memory or a combination of two or more of these.
[0111] The processor 401 reads and executes the computer program instructions stored in the memory 402 to implement any one of the display image 90° rotation control methods in the above embodiments.
[0112] In one example, the display image 90° rotation control device may further include a communication interface 403 and a bus 410. Fig.10 As shown, the processor 401, the memory 402, and the communication interface 403 are connected via a bus 410 and communicate with each other.
[0113] The communication interface 403 is mainly used to implement the communication between the modules, devices, units and / or equipment in the embodiment of the present invention.
[0114] Bus 410 includes hardware, software or both, and the components of the display image 90 ° rotation control device are coupled to each other. For example, but not limitation, the bus may include accelerated graphics port (AGP) or other graphics bus, enhanced industrial standard architecture (EISA) bus, front side bus (FSB), hypertransport (HT) interconnection, industrial standard architecture (ISA) bus, infinite bandwidth interconnection, low pin count (LPC) bus, memory bus, micro channel architecture (MCA) bus, peripheral component interconnection (PCI) bus, PCI-Express (PCI-X) bus, serial advanced technology attachment (SATA) bus, video electronics standard association local (VLB) bus or other suitable bus or two or more of these combinations. In appropriate cases, bus 410 may include one or more buses. Although the embodiment of the present invention describes and shows a specific bus, the present invention considers any suitable bus or interconnection.
[0115] In addition, in combination with the display image 90° rotation control method in the above embodiment, the embodiment of the present invention can provide a computer-readable storage medium for implementation. The computer-readable storage medium stores computer program instructions; when the computer program instructions are executed by a processor, any one of the display image 90° rotation control methods in the above embodiment is implemented.
[0116] It should also be noted that the exemplary embodiments mentioned in the present invention describe some methods or systems based on a series of steps or devices. However, the present invention is not limited to the order of the above steps, that is, the steps can be performed in the order mentioned in the embodiments, or in a different order from the embodiments, or several steps can be performed simultaneously.
[0117] The above is only a specific implementation of the present invention. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working process of the system, module and unit described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here. It should be understood that the protection scope of the present invention is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present invention, and these modifications or replacements should be covered within the protection scope of the present invention.
Claims
1. A method for controlling a 90° rotation of a displayed image, characterized in that: The method comprises: Control the DDR input buffer module to perform alternate buffer reading and writing of input video line data; Controlling the DDR write address calculation module to alternately write the video row data according to a specific order; Controlling the DDR read address calculation module to read the video row data in sequence in units of one rotation unit; Controlling the DDR read address calculation module to rotate the rotation unit until the entire picture is read; The DDR output buffer module is controlled to perform alternate buffer reading and writing on the rotated video row data, so as to output the rotated video data.
2. The method for controlling the 90° rotation of a displayed image according to claim 1, characterized in that: The controlling the DDR input buffer module to perform alternate buffering reading and writing of input video line data comprises: The DDR input buffer module is configured as a dual-port BLOCKRAM storage structure, each dual-port buffer has a depth of 2 lines, and the dual-port BLOCKRAM storage structure is used to alternately cache read and write input video line data.
3. The method for controlling the 90° rotation of a displayed image according to claim 2, characterized in that The controlling the DDR input buffer module to perform alternate buffer reading and writing on the input video line data also includes: Control the dual-port BLOCKRAM storage structure to synchronously read multiple lines of cache; Controlling the dual-port BLOCKRAM storage structure to combine the multiple lines of cache into a length that satisfies a preset number of DDR bursts; The dual-port BLOCKRAM storage structure is controlled to reassemble the video line data in the input buffer.
4. The method for controlling the 90° rotation of a displayed image according to claim 3, characterized in that: The controlling the DDR write address calculation module to alternately write the video row data according to a specific order comprises: Control the DDR write address calculation module to use four variables WR_ADDR0, WR_ADDR1, WR_ADDR2, and WR_ADDR3 to store the frequency row data; wherein the four variables correspond to the addresses of multiple preset row data to be written into the DDR respectively; Taking the preset pixel data in one rotation unit as a combination, the writing of one rotation unit is completed through a preset number of address bursts; The DDR write address calculation module is controlled to alternately complete the storage of the remaining video line data according to the above storage order, so as to realize the mapping between the original address of the video line data and the DDR address.
5. The method for controlling the 90° rotation of a displayed image according to claim 1, characterized in that: The controlling the DDR read address calculation module to sequentially read the video row data in units of one rotation unit comprises: The preset column data is read sequentially from top to bottom in units of one rotation unit; After the DR read address calculation module has finished reading a preset number of rotation units in a continuous address manner, a non-continuous address read operation is performed.
6. The method for controlling the 90° rotation of a displayed image according to claim 4, characterized in that: In the preset number of address bursts, the preset number is: (Input screen width / width of one rotation unit)*number of bursts of one rotation unit.
7. The method for controlling the 90° rotation of a displayed image according to claim 1, characterized in that: The controlling DDR output buffer module to perform alternate buffering reading and writing on the rotated video row data to realize output of the rotated video data comprises: The DDR output buffer module is configured as a dual-port BLOCKRAM storage structure, each dual-port buffer has a depth of 2 lines, and the dual-port BLOCKRAM storage structure is used to alternately cache read and write output video line data.
8. A 90° rotation control device for a displayed image, characterized in that: The device comprises: DDR input buffer module, used for alternate buffering reading and writing of input video line data; A DDR write address calculation module, used for alternately writing the video row data according to a specific order; A DDR read address calculation module, used to read the video line data in units of a rotation unit in sequence, and rotate the rotation unit until the entire picture is read; The DDR output buffer module is used to perform alternate buffer reading and writing on the rotated video row data to realize output of the rotated video data.
9. A display image 90° rotation control device, characterized in that: include: At least one processor, at least one memory and computer program instructions stored in the memory, when the computer program instructions are executed by the processor, implement the method according to any one of claims 1 to 7.
10. A storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method according to any one of claims 1 to 7 is implemented.