Video processing system and control method based on single-port SDRAM pseudo ping-pong read-write

Abstract

The invention discloses a video processing system based on single-port SDRAM pseudo ping-pong read-write and a control method. The system comprises a data stream input device, a software layer, a hardware layer, a video output display device and an infrared remote control device. The control method comprises the following steps: acquiring a to-be-played video and control parameters; performing read-write data preprocessing on the to-be-played video based on pseudo ping-pong operation of the single-port SDRAM controller in combination with the control parameters, and outputting the preprocessed playing video; and performing display adjustment on the video output display device, and displaying the preprocessed playing video. According to the embodiment of the invention, the video frame data can be continuously processed, and high-quality video processing can be completed in a relatively small storage space. The method can be widely applied to the technical field of digital image processing.

Description

Technical Field

[0001] The present application relates to the technical field of digital image processing, and in particular to a video processing system and a control method based on single-port SDRAM pseudo ping-pong reading and writing. Background Art

[0002] With the rapid development of multimedia devices, video processing systems play an increasingly important role in various electronic products. Modern video processing systems usually need to process a large amount of data, which places higher requirements on the system's memory bandwidth, data transmission efficiency, and processor computing power. In the field of video processing, the use of System on Chip (SoC) for processing has become a mainstream trend. SoC integrates processors, memory controllers, I / O interfaces, and other functional modules, which can not only provide high-performance computing capabilities, but also effectively reduce system power consumption and costs.

[0003] In the relevant video processing architecture, the computer system (PC) is usually relied on to process and manage video data. The computer, as the host computer, undertakes the main computing tasks and transmits the processed data to the display device. However, this method requires high-performance hardware support from the computer, which increases the complexity and cost of the system and is not suitable for embedded devices or resource-constrained environments.

[0004] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the invention

[0005] The main purpose of the embodiments of the present application is to propose a video processing system and control method based on single-port SDRAM pseudo ping-pong reading and writing, which can continuously process video frame data and complete high-quality video processing in a smaller storage space.

[0006] To achieve the above-mentioned purpose, an embodiment of the present application provides a video processing system based on single-port SDRAM pseudo ping-pong reading and writing, the system comprising a data stream input device, a software layer, a hardware layer, a video output display device and an infrared remote control device, the output end of the data stream input device is connected to the first input end of the hardware layer, the output end of the hardware layer is connected to the input end of the video output display device, the first output end of the software layer is connected to the input end of the data stream input device, the second output end of the software layer is connected to the second input end of the hardware layer, and the third output end of the software layer is connected to the input end of the infrared remote control device, wherein:

[0007] The data stream input device is used to provide the video to be played;

[0008] The software layer is used to generate control parameters;

[0009] The hardware layer is used for pseudo ping-pong operation based on a single-port SDRAM controller, and performs read and write data preprocessing on the video to be played in combination with the control parameters, and outputs the preprocessed playback video;

[0010] The video output display device is used to display the pre-processed playback video;

[0011] The infrared remote control device is used to adjust the display of the video output display device.

[0012] In some embodiments, the software layer includes an ARM processor debugging module, an AHB bus, an input and output module, an image processing algorithm module, an instruction bus, a data bus, an AHB-APB conversion module, a serial communication module and a host computer module. The ARM processor debugging module bridges the input and output module, the image processing algorithm module, the instruction bus, the data bus and the AHB-APB conversion module through the AHB bus. The AHB-APB conversion module is connected to the host computer module through the serial communication module, and the host computer module is feedback connected to the ARM processor debugging module.

[0013] In some embodiments, the hardware layer includes a processing unit, a single-port SDRAM controller and a VGA module, the output end of the processing unit is connected to the input end of the single-port SDRAM controller, and the output end of the single-port SDRAM controller is connected to the input end of the VGA module, wherein:

[0014] The processing unit is used to perform image data preprocessing on the video to be played to obtain a preliminary preprocessed playing video;

[0015] The single-port SDRAM controller is used to perform a read and write pseudo ping-pong operation on the preliminary pre-processed playback video, and output the pre-processed playback video;

[0016] The VGA module is used to transmit the pre-processed playback video to the video output display device.

[0017] In some embodiments, the single-port SDRAM controller includes an input FIFO port, an SDRAM arbitration module, an SDRAM initialization module, an SDRAM write module, an SDRAM read module, an SDRAM refresh module and an output FIFO port, the input FIFO port is interconnected with the SDRAM arbitration module, the SDRAM arbitration module is respectively interconnected with the SDRAM initialization module, the SDRAM write module, the SDRAM read module, and the SDRAM refresh module, the output end of the SDRAM data exchange module is connected to the input end of the output FIFO port, and the output FIFO port is interconnected with the SDRAM arbitration module, wherein:

[0018] The input FIFO port is used to characterize the current data volume of the single-port SDRAM controller to prevent the writing of invalid data;

[0019] The output FIFO port is used to characterize the current number of free positions of the single-port SDRAM controller to prevent data loss;

[0020] The SDRAM initialization module is used to initialize the single-port SDRAM controller;

[0021] The SDRAM write module is used to control the single-port SDRAM controller to perform data write operations;

[0022] The SDRAM read module is used to control the single-port SDRAM controller to perform a data read operation;

[0023] The SDRAM refresh module is used to refresh the internal storage data of the single-port SDRAM controller;

[0024] The SDRAM arbitration module is used to determine the priority order of the operations executed by the single-port SDRAM controller.

[0025] To achieve the above object, another aspect of the embodiment of the present application provides a control method for a video processing system based on single-port SDRAM pseudo ping-pong reading and writing, the control method comprising the following steps:

[0026] Get the video to be played and the control parameters;

[0027] Based on the pseudo ping-pong operation of the single-port SDRAM controller, and in combination with the control parameters, the video to be played is preprocessed for reading and writing data, and the preprocessed video is output;

[0028] The video output display device is adjusted to display the preprocessed playback video.

[0029] In some embodiments, the pseudo ping-pong operation based on the single-port SDRAM controller and the preprocessing of the read and write data of the video to be played in combination with the control parameters, and outputting the preprocessed video to be played, include:

[0030] Preprocessing the image data of the video to be played according to the control parameters to obtain a preliminary preprocessed playing video;

[0031] Based on a single-port SDRAM controller, performing a read-write pseudo ping-pong operation process on the preliminary pre-processed playback video, and outputting the pre-processed playback video;

[0032] The pre-processed playback video is transmitted to the video output display device.

[0033] In some embodiments, the single-port SDRAM controller is used to perform a read and write pseudo ping-pong operation on the preliminary pre-processed playback video, and output the pre-processed playback video, including:

[0034] Initializing the single-port SDRAM controller to obtain a single-port SDRAM controller that enters a standby state;

[0035] Based on the burst transmission mode, the single-port SDRAM controller in the standby state performs a read-write pseudo ping-pong operation on the preliminary preprocessed playback video, and outputs the preprocessed playback video.

[0036] In some embodiments, the step of initializing the single-port SDRAM controller to obtain the single-port SDRAM controller entering a standby state includes:

[0037] Initializing the single-port SDRAM controller to obtain an initialized single-port SDRAM controller;

[0038] Performing a precharge process on the initialized single-port SDRAM controller to obtain a precharged single-port SDRAM controller;

[0039] The pre-charged single-port SDRAM controller is automatically refreshed and enters the execution mode in sequence to obtain the single-port SDRAM controller that enters the standby state.

[0040] In some embodiments, the read-write pseudo ping-pong operation processing includes a read-write request operation, a read request operation and a write request operation at the same time, wherein:

[0041] For the read and write request operations, the single-port SDRAM controller processes the write request operation first, and when the pointer of the write request operation reaches the bottom of the bank, the read request operation is executed;

[0042] For the read request operation, the single-port SDRAM controller determines whether the read pointer reaches the bottom of the bank. If the read pointer reaches the bottom of the bank but the write pointer does not reach the bottom of the bank, the single-port SDRAM controller will repeatedly read the current frame data. If both the read pointer and the write pointer reach the bottom of the bank, the single-port SDRAM controller will perform a bank switching operation and execute the read request operation to read the next frame of image data.

[0043] For the write request operation, the single-port SDRAM controller determines whether the write pointer reaches the bottom of the bank. If the write pointer reaches the bottom of the bank but the read pointer does not reach the bottom of the bank, the single-port SDRAM controller sends an interrupt instruction to suspend data writing. If both the read pointer and the write pointer reach the bottom of the bank, the single-port SDRAM controller will perform a bank switching operation and execute the write request operation to write the next frame of image data.

[0044] In some embodiments, it also includes setting a priority order for data read and write operations, wherein the automatic refresh is processed as a first priority, the write request operation is processed as a second priority, and the read request operation is processed as a third priority.

[0045] The embodiments of the present application include at least the following beneficial effects: The present application provides a video processing system and control method based on single-port SDRAM pseudo ping-pong reading and writing. The scheme obtains the video to be played and the control parameters, further performs pseudo ping-pong operation based on the single-port SDRAM controller, and pre-processes the read and write data of the video to be played in combination with the control parameters, and completely implements video processing on the FPGA without the participation of the host computer. Efficient ping-pong operation is achieved through the single-port SDRAM controller to ensure that the processor can continuously process video frame data, and the circuit complexity and cost of the design can be reduced by avoiding image tearing and video frame loss. Through the efficient use of the single-port SDRAM and the optimized pseudo ping-pong operation, the maximum utilization of storage resources is achieved, and high-quality video processing can be completed in a smaller storage space. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 It is a structural schematic diagram of a video processing system based on single-port SDRAM pseudo ping-pong reading and writing provided by an embodiment of the present application;

[0047] Figure 2 It is a schematic flow chart of the steps of a control method of a video processing system based on single-port SDRAM pseudo ping-pong reading and writing provided by an embodiment of the present application;

[0048] Figure 3It is a structural diagram of a single-port SDRAM controller provided in an embodiment of the present application;

[0049] Figure 4 It is a memory strategy diagram of a single-port SDRAM controller provided in an embodiment of the present application. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present application. They are only examples of systems and methods consistent with some aspects of the embodiments of the present application as detailed in the attached claims.

[0051] It is understood that the terms "first", "second", etc. used in this application can be used to describe various concepts in this article, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another concept. For example, without departing from the scope of the embodiment of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" and "if" as used herein can be interpreted as "at the time of" or "when" or "in response to determination".

[0052] The terms "at least one", "multiple", "each", "any", etc. used in this application, at least one includes one, two or more, multiple includes two or more, each refers to each of the corresponding multiple, and any refers to any one of the multiple.

[0053] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0054] Reference Figure 1 , Figure 1 A structural diagram of a video processing system based on single-port SDRAM pseudo ping-pong reading and writing provided by an embodiment of the present invention, referring to Figure 1The system includes a data stream input device, a software layer, a hardware layer, a video output display device and an infrared remote control device, wherein the output end of the data stream input device is connected to the first input end of the hardware layer, the output end of the hardware layer is connected to the input end of the video output display device, the first output end of the software layer is connected to the input end of the data stream input device, the second output end of the software layer is connected to the second input end of the hardware layer, and the third output end of the software layer is connected to the input end of the infrared remote control device, wherein:

[0055] The data stream input device is used to provide the video to be played;

[0056] In this embodiment, an SD card is used to store the video to be played to simulate data stream input; in other embodiments, other data stream input methods can be used.

[0057] The software layer is used to generate control parameters;

[0058] Specifically, the software layer includes an ARM processor debugging module, an AHB bus, an input-output module, an image processing algorithm module, an instruction bus, a data bus, an AHB-APB conversion module, a serial communication module and a host computer module. The ARM processor debugging module bridges the input-output module, the image processing algorithm module, the instruction bus, the data bus and the AHB-APB conversion module through the AHB bus. The AHB-APB conversion module is connected to the host computer module through the serial communication module, and the host computer module is feedback-connected to the ARM processor debugging module.

[0059] In this embodiment, the software layer system is based on the ARM Cortex-M0 soft core, and various peripheral modules such as GPIO (input and output module), ISP (image processing algorithm module), DTCM (data bus), and ITCM (instruction bus) are bridged through the AHB bus. Among them, GPIO is connected to the running light, and the software program is written and generated by the Kei KKμVision tool to control the running light, so as to realize the online real-time debugging of the software program running on the SoC to confirm that the program runs correctly. ISP is connected to the video data processing module (processing module Ke), and realizes the processing of white balance, sharpening, saturation adjustment, filtering, noise reduction, etc. of the video data, with the intention of restoring a more realistic video scene that meets the needs of users. And ITCM is the instruction transmission bus in the cortex kernel, and DTCM is the data transmission bus in the cortex kernel. The AHB bus bridges APB, and the APB bus transmits data to the PC end through the UART serial communication interface. It should be noted that the PC host computer is only used in the debugging and troubleshooting process. After the device is debugged, the overall execution process does not require the participation of the PC host computer.

[0060] The hardware layer is used for pseudo ping-pong operation based on a single-port SDRAM controller, and performs read and write data preprocessing on the video to be played in combination with control parameters, and outputs the preprocessed video to be played;

[0061] Specifically, the hardware layer includes a processing unit, a single-port SDRAM controller and a VGA module. The output end of the processing unit is connected to the input end of the single-port SDRAM controller, and the output end of the single-port SDRAM controller is connected to the input end of the VGA module. The processing unit is used to preprocess the image data of the video to be played to obtain a preliminary preprocessed playback video; the single-port SDRAM controller is used to perform read and write pseudo ping-pong operations on the preliminary preprocessed playback video and output the preprocessed playback video; the VGA module is used to transmit the preprocessed playback video to a video output display device.

[0062] Further, such as Figure 3 As shown, the single-port SDRAM controller includes an input FIFO port, an SDRAM arbitration module, an SDRAM initialization module, an SDRAM write module, an SDRAM read module, an SDRAM refresh module and an output FIFO port. The input FIFO port is connected to the SDRAM arbitration module, the SDRAM arbitration module is respectively connected to the SDRAM initialization module, the SDRAM write module, the SDRAM read module and the SDRAM refresh module, the output end of the SDRAM data exchange module is connected to the input end of the output FIFO port, and the output FIFO port is connected to the SDRAM arbitration module.

[0063] Among them, the input FIFO port is used to characterize the current data volume of the single-port SDRAM controller to prevent the writing of invalid data;

[0064] Specifically, the input FIFO port is placed between the SD card and the SDRAM controller as a buffer for cross-clock domain transmission, and provides a Kmost_empty_fKag to indicate whether the current data volume of the FIFO is greater than 256. If so, it is pulled low, allowing the SDRAM controller to request data and write it into the single-port SDRAM, effectively preventing the writing of invalid data.

[0065] The output FIFO port is used to characterize the current number of free positions of the single-port SDRAM controller to prevent data loss;

[0066] Specifically, the output FIFO port is placed between the SDRAM controller and VGA as a buffer for cross-clock domain transmission, and at the same time provides a Kmost_fu K K_f Kag to characterize whether the current number of free positions in the FIFO is greater than 256. If it is greater, it is pulled low, allowing the SDRAM controller to output the data stored in the single-port SDRAM to the VGA for display, effectively preventing the output data from being lost due to insufficient FIFO capacity and ensuring the data validity.

[0067] The SDRAM initialization module is used to initialize the single-port SDRAM controller;

[0068] Specifically, the SDRAM initialization module is responsible for configuring some register parameters inside the SDRAM, and completing the power-on and pre-charging operations to prepare for the next step.

[0069] The SDRAM write module is used to control the single-port SDRAM controller to perform data write operations;

[0070] Specifically, a read operation of the single-port SDRAM is started, and a burst transmission mode is adopted to read out 256 data at a time.

[0071] The SDRAM read module is used to control the single-port SDRAM controller to perform data read operations;

[0072] Specifically, a read operation of the single-port SDRAM is started, a burst transmission mode is adopted, and 256 data are written at one time.

[0073] The SDRAM refresh module is used to refresh the internal storage data of the single-port SDRAM controller;

[0074] Specifically, since SDRAM needs to be refreshed regularly to maintain the validity of the data, the controller must effectively arbitrate between read and write operations and data refresh. According to the official manual of SDRAM, the refresh rate must reach at least 4096 times / 64ms. The refresh module is responsible for refreshing the SDRAM, refreshing the current data according to the stored high and low bits, maintaining the data unchanged, and ensuring the correctness of the data stored in the SDRAM.

[0075] The SDRAM arbitration module is used to determine the priority order of operations performed by the single-port SDRAM controller.

[0076] Specifically, it is used to ensure the timed refresh of data. Based on the time count, the module sets the refresh instruction to the highest priority, giving priority to meeting the refresh rate requirement of 4096 times / 64ms of the single-port SDRAM. Only after the refresh operation is completed, the system will allow other read and write operations. This design effectively prevents the problem of data loss caused by power failure. When processing multiple requests, the arbitration module will make a selection according to the predetermined priority rules. If the refresh, read, and write requests are issued at the same time, the arbitration module will process them in the priority order of refresh>write>read. This priority setting ensures the integrity and validity of the data: first perform the refresh operation to protect the data, then perform the write operation to update the storage content, and finally perform the read operation to ensure the accuracy of the system output.

[0077] These modules work together to ensure that the single-port SDRAM can stably and efficiently perform data storage and reading operations.

[0078] In this embodiment, the hardware layer includes a complete DMA (direct memory access) path, and the data processing process is implemented in the hardware layer without going through the processor, which saves resources for the processor and improves the efficiency of data processing. It includes a series of ISP modules, which are connected to the ISP configuration module of the software layer to obtain specific parameters, and the data processing is completed in the Processing Module in the hardware layer to achieve rich ISP functions such as white balance, sharpening, saturation adjustment, filtering, noise reduction and other processing. In the hardware layer, a single-port SDRAM is used to implement pseudo ping-pong operation to prevent image tearing and video frame loss. There is a FIFO before and after the single-port SDRAM as a cross-clock domain data processing buffer unit to ensure data validity.

[0079] The video output display device is used to display the pre-processed playback video;

[0080] In this embodiment, a VGA screen is used to output and display the processed video. In other embodiments, other data display devices may be used.

[0081] The infrared remote control device is used to adjust the display of the video output display device.

[0082] In this embodiment, the infrared remote control device is connected to the LCD screen to provide the user with a screen that displays debugging input parameter information, making the user operation more flexible and convenient.

[0083] See also Figure 2 The embodiment of the present application also provides a control method of a video processing system based on a single-port SDRAM pseudo ping-pong read-write, which can realize the above-mentioned video processing system based on a single-port SDRAM pseudo ping-pong read-write, and the control method includes:

[0084] S100, obtaining the video to be played and control parameters;

[0085] S200, based on the pseudo ping-pong operation of the single-port SDRAM controller, and in combination with the control parameters, preprocessing the read and write data of the video to be played, and outputting the preprocessed video to be played;

[0086] It should be noted that, in some embodiments, step S200 may include: S210, preprocessing the image data of the video to be played according to the control parameters to obtain a preliminary preprocessed playback video; S220, based on a single-port SDRAM controller, performing read and write pseudo ping-pong operations on the preliminary preprocessed playback video, and outputting the preprocessed playback video; S230, transmitting the preprocessed playback video to a video output display device.

[0087] In some specific embodiments, a single-port SDRAM controller is initialized to obtain a single-port SDRAM controller that enters a standby state; based on a burst transmission mode, the single-port SDRAM controller in the standby state performs a read and write pseudo ping-pong operation on the preliminary preprocessed playback video and outputs the preprocessed playback video.

[0088] The initialization process includes: initializing the single-port SDRAM controller to obtain an initialized single-port SDRAM controller; precharging the initialized single-port SDRAM controller to obtain a precharged single-port SDRAM controller; and automatically refreshing and entering execution mode in turn on the precharged single-port SDRAM controller to obtain a single-port SDRAM controller in standby state.

[0089] In this embodiment, when the system starts, the SDRAM controller first enters the initialization state machine and performs a series of configuration operations, including timing parameter setting, mode register configuration, etc. The initialization process is the basis for subsequent operations, ensuring that the SDRAM is in a stable working state. After the initialization is completed, the controller performs a precharge operation to release the charge in all banks, ensuring that all storage units of the SDRAM are in a unified state, and preparing for subsequent operations. After the precharge is completed, the SDRAM controller will perform two automatic refresh operations. Due to its DRAM characteristics, SDRAM needs to be refreshed regularly to maintain the validity of stored data. The automatic refresh operation will refresh all storage units according to a predetermined refresh cycle to prevent data from being lost due to charge leakage. In the subsequent read and write process, the SDRAM still needs to refresh the stored data to prevent data loss. After the refresh is completed, the controller enters a standby state and waits for the arrival of external read and write commands. At this time, the SDRAM is ready to receive and execute data read and write operations. At the same time, if the automatic refresh module issues a refresh request, the execution mode also determines whether to execute it.

[0090] Furthermore, when a read or write command is received, the single-port SDRAM controller will perform the corresponding operation according to the command type. Since the single-port SDRAM uses a shared data line, read and write operations cannot be performed at the same time. The controller will select the appropriate operation mode and perform data transmission based on the current command type. In particular, the read and write operations of the single-port SDRAM both use a burst transmission mode, which significantly improves the transmission efficiency. Specifically, after the controller sends an address once, the single-port SDRAM will continuously transmit data to 256 addresses, thereby reducing the delay caused by instruction sending and response. When the transmission operation is completed, the single-port SDRAM controller will stop using the data line and wait for the next command (read, write or refresh). At this time, the controller will re-enter the standby state or perform other operations as needed.

[0091] In summary, the overall working logic of SDRAM is: initialization, precharge, automatic refresh, execution mode (waiting for read and write commands), read or write (shared data line, cannot be performed at the same time), and transmission stop. Since SDRAM needs to be refreshed regularly to maintain the validity of data, an arbitration module needs to be designed between reading, writing, and refreshing to ensure that the data is refreshed regularly and effectively, and its refresh rate is at least 4096 times / 64ms. Therefore, the arbitration module is set to count according to time, and the refresh instruction is the highest priority. Only after the refresh instruction is satisfied can the read and write operation be performed to prevent the data from losing power and causing the data validity to be lost. At the same time, if the refresh, read, and write requests are issued at the same time, the priority is: refresh>write>read to prevent data loss. In addition, a large part of the limitation of SDRAM read and write speed comes from the process of repeated sending and repeated response of commands. Therefore, this design adopts burst transmission for both reading and writing of SDRAM, which greatly improves the transmission efficiency. After sending an address to SDRAM once, 256 consecutive addresses of SDRAM will be read or written in accordance with the burst transmission method, avoiding the delay problem of repeated sending of instructions and repeated response. In order to read and write using burst transmission, this design introduces two FIFOs as read and write buffers respectively. Since burst transmission needs to transmit 256 data at a time, FIFO is needed to prevent data loss. Specifically: a Kmost_empty_f Kag of the write FIFO and a Kmost_fu K K_f Kag of the read FIFO are used as control signals for burst transmission. Only when there are no less than 256 data in the write FIFO, can burst transmission be used to transfer 256 data to SDRAM; conversely, only when there are no less than 256 data vacancies in the read FIFO, can burst transmission be used to read 256 data from SDRAM to FIFO, thus ensuring the validity of the data.

[0092] Furthermore, it should be noted that the biggest problem with single-port SDRAM is that it is impossible to read and write at the same time because the read and write ports share a common port. The current common solution is to use a dual-port device to control the read and write ports separately, so that the read and write operations can be completed simultaneously. However, this device will increase the complexity of circuit design and increase cost and power consumption. The embodiment of the present invention uses a dual pointer and divides the memory into two blocks (one for reading and one for writing) to achieve pseudo ping-pong operation using a single-port SDRAM. This method not only reduces costs, but also reduces the demand for large-capacity storage, which is a common requirement of many modern systems. By using a single-port SDRAM and an efficient control strategy, this design significantly reduces costs and storage space occupancy while maintaining performance.

[0093] Single-port read-write SDRAM poses a great challenge to VGA video reading, because VGA needs to read data at a certain frequency all the time, that is, if SDRAM is in a write state for a long time, VGA will not be able to read data, resulting in black screen and image tearing. In order to meet the requirements of reading speed, the read and write requests designed in this design are executed by row, that is, after burst reading a row (256 data) or writing a row (256 data), the next read and write request to SDRAM will be judged to meet the needs of VGA reading video data. Another problem comes from the fact that the VGA reading speed is faster than the SD card reading speed, that is, when the video display module's demand for data reading and writing speed is greater than the read and write capabilities that the data stream input module can provide, VGA needs to repeatedly read the same frame to prevent image tearing until the next frame of the image is loaded. Therefore, it is necessary to use the arbitration module to judge the memory usage of SDRAM, that is, when to read or write.

[0094] Specifically, it should be noted that Figure 4 As shown, the read-write pseudo ping-pong operation processing includes simultaneous read-write request operations, read request operations, and write request operations.

[0095] For read and write request operations, the single-port SDRAM controller prioritizes write request operations, and when the pointer of the write request operation reaches the bottom of the bank, it executes the read request operation;

[0096] Specifically, when there are read and write requests at the same time, the system will give priority to writing requests. After the write operation is completed, the read request will be processed immediately. This priority arrangement is to ensure that new image data can be written in time, thereby avoiding blank display of subsequent frames. When the read and write pointers reach the bottom of their respective banks at the same time, the system will immediately switch banks and continue with the next round of read and write operations. If the write pointer reaches the bottom but the read pointer has not yet reached it, the write operation will be temporarily interrupted at this time, and the reading of the current frame will be completed first to prevent the VGA display from reading incomplete image data. Conversely, if the read pointer reaches the bottom but the write pointer has not yet reached the bottom, the system will repeatedly read the current frame until the write operation is completed. This design ensures that the image display will not be interrupted or abnormal even if the write operation has not yet been completed.

[0097] For a read request operation, the single-port SDRAM controller determines whether the read pointer reaches the bottom of the bank. If the read pointer reaches the bottom of the bank but the write pointer does not, the single-port SDRAM controller will repeatedly read the current frame data. If both the read pointer and the write pointer reach the bottom of the bank, the single-port SDRAM controller will perform a bank switching operation and execute a read request operation to read the next frame of image data.

[0098] Specifically, in the case of only a read request, when the system only receives a read request, it first determines whether the read pointer has reached the last row of the bank. If the read pointer has reached the bottom and the write pointer has not yet reached the bottom, the system will repeatedly read the current frame data. The purpose of this practice is to meet the continuity requirements of VGA display and avoid image tearing or flickering on the display. If the write pointer also reaches the bottom at this time, the system will perform a bank switching operation and then continue to read the next frame of image data. If the read pointer has not yet reached the last row, the system will continue to read data row by row until the read pointer reaches the bottom.

[0099] For write request operations, the single-port SDRAM controller determines whether the write pointer reaches the bottom of the bank. If the write pointer reaches the bottom of the bank but the read pointer does not, the single-port SDRAM controller sends an interrupt command to suspend data writing. If both the read pointer and the write pointer reach the bottom of the bank, the single-port SDRAM controller will perform a bank switching operation and execute a write request operation to write the next frame of image data.

[0100] Specifically, there is only a write request. In this case, the focus of the system is to ensure that the write operation does not overwrite the data that has not been read. The system will first determine whether the write pointer has reached the last row of the bank. If the write pointer has reached the bottom, the system will further check the position of the read pointer. If the read pointer has also reached the bottom, the system will perform a bank switching operation to perform read and write operations at the same time. However, if the read pointer has not reached the bottom, it means that there is still data that has not been read. If writing continues at this time, it may cause data overwriting. To prevent this from happening, the system will send an interrupt instruction to the SD card to suspend data writing until the read operation is completed. If the write pointer has not reached the bottom, the system will continue normal read and write operations until the switching conditions are met.

[0101] In summary, a single-port SDRAM is used and divided into two different banks for reading and writing. Each bank is used as an independent storage unit to implement pseudo ping-pong operation. The core purpose of this operation is to efficiently and stably complete the processing and output of video data when the read and write operations cannot be performed at the same time, thereby avoiding instability, tearing, video frame loss and other phenomena in image display. The pseudo ping-pong operation method for single-port SDRAM is as follows: Two banks constitute read and write storage units respectively, which are used to store a complete frame of image data. The key to the design of the entire storage structure is how to read previously stored data while writing new data without causing data conflict or loss. In order to avoid reading empty frames, the system writes two frames of data in the initial stage. This ensures that at any time, at least one complete frame of the image can be read and output to the VGA display. The two pointers point to the row numbers of the banks currently being read and written, respectively. This dual pointer strategy allows the system to switch efficiently between different banks, thereby realizing alternating read and write operations. The system will only trigger bank switching when the two pointers reach the bottom of their respective banks at the same time. The advantage of this design is that in most cases, conflicts between read and write operations can be avoided, thereby improving the overall efficiency of the system. It should be noted that the dual pointer mechanism requires extremely fine granularity control, so the present invention adopts row-based read and write operations, that is, after each read or write of a row of data (256×32 bits=8192 bits) of a single-port SDRAM, the pointer state is judged to meet the rate requirements of VGA reading and displaying video.

[0102] Therefore, the pseudo ping-pong operation method for the single-port SDRAM adopted in the embodiment of the present invention can overcome the technical limitation that the single-port SDRAM cannot read and write at the same time, resulting in image tearing, video frame loss and other problems. The memory of the single-port SDRAM is flexibly arranged by using a dual pointer mechanism, so that the VGA can display video images normally and smoothly, which is close to the ping-pong process of the conventional dual-port SDRAM. At the same time, the memory required by the embodiment of the present invention is extremely small, and only the space size that can store two frames of images is required to complete the pseudo ping-pong operation. In addition, the introduction of the burst transmission mode of the present invention not only reduces the number of instruction interactions between the controller and the SDRAM, but also significantly reduces the communication delay, ensuring the stability and response speed of the system under high data throughput conditions.

[0103] S300: Perform display adjustment on the video output display device to display the pre-processed playback video.

[0104] In summary, the present invention innovatively adopts a single-port SDRAM (Synchronous Dynamic Random-Access Memory) to implement storage operations in video processing. Although a single-port SDRAM can only perform read or write operations at one time, through reasonable architecture design and dual-pointer management, the embodiment of the present invention can still achieve performance comparable to that of a dual-port RAM. The SDRAM is divided into two independent banks, one for reading data and the other for writing data. The system uses dual pointers to point to the current read and write positions respectively, ensuring that the processing of video data remains smooth without increasing the complexity of the storage hardware. This design not only reduces the hardware cost of the system, but also reduces the complexity of the circuit.

[0105] The SoC system of the embodiment of the present invention adopts a highly integrated FPGA design, which is significantly different from the traditional video processing architecture that requires the participation of a computer system. Our system can completely independently complete the tasks of reading, processing and displaying video data without relying on any computing or storage resources of the host computer. This not only simplifies the design of the system, but also further reduces the overall cost and improves the reliability and stability of the system.

[0106] In terms of system control, the design of the embodiment of the present invention adopts infrared remote control technology, which further enhances the user's operating experience. Infrared remote control has been widely used in consumer electronic products due to its advantages such as low cost, simple operation, strong anti-interference ability and low energy consumption. However, traditional video processing systems usually rely on computers or other complex input devices for control, and rarely use infrared remote controls. This makes our design have obvious advantages in terms of ease of operation and user experience. Infrared remote control is not only easy to use, but also has good privacy, because infrared signals can only be transmitted within the line of sight, reducing the possibility of accidental interference.

[0107] At the same time, the system also ensures the stable transmission of data between different modules by designing an effective cross-clock domain transmission mechanism, thereby improving the reliability and performance of the system.

[0108] Compared with the related art, the embodiments of the present invention have the following differences and beneficial effects:

[0109] 1) Video processing is completely implemented on FPGA without the involvement of the host computer. This design is significantly different from traditional computer systems: it adopts a highly integrated SoC architecture, integrating functional modules such as processors, memory controllers, and video display controllers into one chip, which can independently complete the tasks of reading, processing, and displaying video data, reducing dependence on external hardware.

[0110] 2) In terms of storage management, a single-port SDRAM (Synchronous Dynamic Random-Access Memory) is used to achieve low-cost video data storage. Traditional video processing systems usually use dual-port RAM (Dual-Port RAM) or more complex multi-port memory architecture to achieve efficient ping-pong operation (Ping-Pong Operation) to ensure that the processor can continuously process video frame data.

[0111] 3) Although the memory has excellent performance, it is expensive and difficult to apply to low-cost embedded systems. The embodiment of the present invention realizes efficient management of single-port SDRAM through the coordinated control of software and hardware of the ARM core, combined with the requirements of the VGA display system. Specifically, we divide the single-port SDRAM into two independent banks (areas), one for reading data and the other for writing data. Through dual pointer operations, they point to the memory addresses currently read and written, respectively, to ensure the continuity and synchronization of video data during the reading and writing process. This design not only effectively avoids the problems of image tearing and video frame loss in video processing, but also strictly meets the requirements of VGA display timing, while reducing the cost required for the design.

[0112] 4) The FPGA in the embodiment of the present invention undertakes all video processing tasks to ensure the real-time performance of data processing and the stability of the system. Compared with the traditional video processing method that requires the participation of a computer system, the design of the SoC system greatly reduces the hardware cost and system complexity, while improving the integration and reliability.

[0113] 5) By designing an effective cross-clock domain transmission mechanism, the synchronization problem of data transmission between different modules is solved, ensuring the integrity and transmission efficiency of the data. At the same time, the integrated infrared remote control system further enhances the ease of use of the system and can realize remote control of the video processing system.

[0114] To sum up, the embodiment of the present invention adopts a single-port SDRAM as a memory in the SoC system, combines the ARM core hardware and software collaborative control, cross-clock domain data transmission mechanism and infrared remote control system, to provide a high-performance, low-cost video processing solution that does not require the participation of a host computer, and has broad application prospects.

[0115] It can be understood that the contents of the above method embodiments are all applicable to the present system embodiments, the functions specifically implemented by the present system embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0116] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the present invention is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present invention should be within the scope of the rights of the present invention.

Claims

1. A video processing system based on single-port SDRAM pseudo ping-pong reading and writing, characterized in that: The system comprises a data stream input device, a software layer, a hardware layer, a video output display device and an infrared remote control device, wherein the output end of the data stream input device is connected to the first input end of the hardware layer, the output end of the hardware layer is connected to the input end of the video output display device, the first output end of the software layer is connected to the input end of the data stream input device, the second output end of the software layer is connected to the second input end of the hardware layer, and the third output end of the software layer is connected to the input end of the infrared remote control device, wherein: The data stream input device is used to provide the video to be played; The software layer is used to generate control parameters; The hardware layer is used for pseudo ping-pong operation based on a single-port SDRAM controller, and performs read and write data preprocessing on the video to be played in combination with the control parameters, and outputs the preprocessed playback video; The video output display device is used to display the pre-processed playback video; The infrared remote control device is used to adjust the display of the video output display device.

2. The system according to claim 1, characterized in that The software layer includes an ARM processor debugging module, an AHB bus, an input-output module, an image processing algorithm module, an instruction bus, a data bus, an AHB-APB conversion module, a serial communication module and a host computer module. The ARM processor debugging module bridges the input-output module, the image processing algorithm module, the instruction bus, the data bus and the AHB-APB conversion module through the AHB bus. The AHB-APB conversion module is connected to the host computer module through the serial communication module, and the host computer module is feedback-connected to the ARM processor debugging module.

3. The system according to claim 1, characterized in that The hardware layer includes a processing unit, a single-port SDRAM controller and a VGA module, wherein the output end of the processing unit is connected to the input end of the single-port SDRAM controller, and the output end of the single-port SDRAM controller is connected to the input end of the VGA module, wherein: The processing unit is used to perform image data preprocessing on the video to be played to obtain a preliminary preprocessed playing video; The single-port SDRAM controller is used to perform a read and write pseudo ping-pong operation on the preliminary pre-processed playback video, and output the pre-processed playback video; The VGA module is used to transmit the pre-processed playback video to the video output display device.

4. The system according to claim 3, characterized in that The single-port SDRAM controller includes an input FIFO port, an SDRAM arbitration module, an SDRAM initialization module, an SDRAM write module, an SDRAM read module, an SDRAM refresh module and an output FIFO port, wherein the input FIFO port is interconnected with the SDRAM arbitration module, the SDRAM arbitration module is respectively interconnected with the SDRAM initialization module, the SDRAM write module, the SDRAM read module and the SDRAM refresh module, the output end of the SDRAM data exchange module is connected with the input end of the output FIFO port, and the output FIFO port is interconnected with the SDRAM arbitration module: The input FIFO port is used to characterize the current data volume of the single-port SDRAM controller to prevent the writing of invalid data; The output FIFO port is used to characterize the current number of free positions of the single-port SDRAM controller to prevent data loss; The SDRAM initialization module is used to initialize the single-port SDRAM controller; The SDRAM write module is used to control the single-port SDRAM controller to perform data write operations; The SDRAM read module is used to control the single-port SDRAM controller to perform a data read operation; The SDRAM refresh module is used to refresh the internal storage data of the single-port SDRAM controller; The SDRAM arbitration module is used to determine the priority order of the operations executed by the single-port SDRAM controller.

5. A control method for a video processing system based on single-port SDRAM pseudo ping-pong reading and writing, characterized in that: The control method comprises the following steps: Get the video to be played and the control parameters; Based on the pseudo ping-pong operation of the single-port SDRAM controller, and in combination with the control parameters, the video to be played is preprocessed for reading and writing data, and the preprocessed video is output; The video output display device is adjusted to display the preprocessed playback video.

6. The method according to claim 5, characterized in that The pseudo ping-pong operation based on the single-port SDRAM controller and preprocessing the read and write data of the video to be played in combination with the control parameters, and outputting the preprocessed video to be played, includes: Preprocessing the image data of the video to be played according to the control parameters to obtain a preliminary preprocessed playing video; Based on a single-port SDRAM controller, performing a read-write pseudo ping-pong operation process on the preliminary pre-processed playback video, and outputting the pre-processed playback video; The pre-processed playback video is transmitted to the video output display device.

7. The method according to claim 6, characterized in that The single-port SDRAM controller is based on which the preliminarily preprocessed playback video is subjected to a read-write pseudo ping-pong operation process, and outputs the preprocessed playback video, including: Initializing the single-port SDRAM controller to obtain a single-port SDRAM controller that enters a standby state; Based on the burst transmission mode, the single-port SDRAM controller in the standby state performs a read-write pseudo ping-pong operation on the preliminary preprocessed playback video, and outputs the preprocessed playback video.

8. The method according to claim 7, characterized in that The step of initializing the single-port SDRAM controller to obtain a single-port SDRAM controller that enters a standby state includes: Initializing the single-port SDRAM controller to obtain an initialized single-port SDRAM controller; Performing a precharge process on the initialized single-port SDRAM controller to obtain a precharged single-port SDRAM controller; The pre-charged single-port SDRAM controller is automatically refreshed and enters the execution mode in sequence to obtain the single-port SDRAM controller that enters the standby state.

9. The method according to claim 7, characterized in that: The read-write pseudo ping-pong operation processing includes a read-write request operation, a read request operation and a write request operation at the same time, wherein: For the read and write request operations, the single-port SDRAM controller processes the write request operation first, and when the pointer of the write request operation reaches the bottom of the bank, the read request operation is executed; For the read request operation, the single-port SDRAM controller determines whether the read pointer reaches the bottom of the bank. If the read pointer reaches the bottom of the bank but the write pointer does not reach the bottom of the bank, the single-port SDRAM controller will repeatedly read the current frame data. If both the read pointer and the write pointer reach the bottom of the bank, the single-port SDRAM controller will perform a bank switching operation and execute the read request operation to read the next frame of image data. For the write request operation, the single-port SDRAM controller determines whether the write pointer reaches the bottom of the bank. If the write pointer reaches the bottom of the bank but the read pointer does not reach the bottom of the bank, the single-port SDRAM controller sends an interrupt instruction to suspend data writing. If both the read pointer and the write pointer reach the bottom of the bank, the single-port SDRAM controller will perform a bank switching operation and execute the write request operation to write the next frame of image data.

10. The method according to claim 9, characterized in that It also includes setting a priority order for data read and write operations, wherein the automatic refresh is processed as a first priority, the write request operation is processed as a second priority, and the read request operation is processed as a third priority.

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