Sensor pixel unit, signal processing circuit and electronic equipment

Abstract

The embodiment of the invention discloses a sensor pixel unit, a signal processing circuit and electronic equipment, and the sensor pixel unit comprises a photosensitive unit, a pulse triggering unit, and a pulse latch unit. The light sensing unit is used for receiving the light signal in the exposure duration to generate a first signal, responding to the condition that the first signal reaches a preset threshold value, and sending the first signal to the pulse triggering unit through the first output end; when the photosensitive period is reached, a second signal is output through a second output end; the pulse triggering unit is used for sending a reading request signal to the outside according to the first signal and outputting a third signal according to a feedback allowing signal; the pulse latch unit is used for latching a fourth signal according to the control of the reset signal, and switching on the path of the pulse trigger unit for sending the read request signal when the fourth signal is in a high level; and in response to the permission signal received in one photosensitive period, disconnecting the path of the pulse trigger unit for sending the read request signal.

Description

Technical Field

[0001] The present disclosure relates to the field of sensor technology, and in particular to a sensor pixel unit, a signal processing circuit and an electronic device. Background Art

[0002] Pulse sequence image sensors reflect light intensity by detecting the time required for photogenerated charge to accumulate to a certain threshold. The stronger the light, the shorter the time required for photogenerated charge to accumulate to the threshold. In actual imaging, the light intensity received by each pixel unit in the pixel array is different, and the time it takes for its photogenerated charge to reach the threshold is also different. For signal reading, if the pixel array signal is read synchronously at a fixed frame rate, there will inevitably be pixel units that have reached the threshold early, but have to wait for all other pixel units to reach the threshold before they can be output together. Obviously, this reading method has low time efficiency and cannot reflect the light intensity corresponding to each pixel unit. Summary of the invention

[0003] Embodiments of the present disclosure provide a sensor pixel unit, a signal processing circuit, and an electronic device.

[0004] In one aspect of an embodiment of the present disclosure, a sensor pixel unit is provided, comprising: a photosensitive unit, a pulse trigger unit, and a pulse latch unit;

[0005] The photosensitive unit is used to receive a light signal within an exposure time to generate a first signal, and in response to the first signal reaching a preset threshold, send the first signal to the pulse trigger unit through a first output terminal; and output a second signal through a second output terminal when a photosensitive period is reached;

[0006] The pulse trigger unit is used to send a read request signal to the outside according to the first signal, and output a third signal according to the feedback permission signal;

[0007] The pulse latch unit is used to latch the fourth signal according to the control of the reset signal, and in response to the fourth signal being at a high level, to open the path for the pulse trigger unit to send the read request signal; in response to receiving the enable signal within a photosensitive cycle, to disconnect the path for the pulse trigger unit to send the read request signal.

[0008] Optionally, the photosensitive unit includes a first photodiode, a second photodiode, a reset transistor, a transfer transistor and an auxiliary circuit;

[0009] The first photodiode is used to receive a light signal within an exposure time to generate a voltage signal, and in response to reaching the light-sensitive period, transmit the voltage signal to the second photodiode through the transfer transistor;

[0010] The second photodiode is used to receive a light signal within an exposure time to generate a voltage signal, and in response to the voltage signal reaching a preset threshold value during the photosensitive period, output the first signal at the first output terminal based on the voltage signal, and in response to reaching the photosensitive period, receive the voltage signal transmitted by the first photodiode, and output the voltage signal to the auxiliary circuit;

[0011] The reset transistor is used to control the second photodiode to perform reset according to a reset signal;

[0012] The transfer transistor is used to provide a connection path between the first photodiode and the second photodiode;

[0013] The auxiliary circuit is used to control the second output terminal to output the second signal according to the received voltage signal when the light-sensitive period is reached.

[0014] Optionally, the auxiliary circuit includes a source follower transistor and a readout transistor;

[0015] One end of the first photodiode is grounded, and the other end is connected to the drain end of the transfer transistor;

[0016] One end of the second photodiode is grounded, and the other end is connected to the source end of the transfer transistor, the drain end of the reset transistor, and the gate end of the source follower transistor, and the connection point is used as the first output end;

[0017] The source terminal of the reset transistor is connected to the power supply signal, the drain terminal is connected to the other end of the second photodiode, and the gate terminal receives a reset signal;

[0018] The transfer transistor connects the first photodiode and the second photodiode via a source terminal and a drain terminal, receives a transfer signal at a gate terminal, and conducts a connection path between the first photodiode and the second photodiode according to control of the transfer signal;

[0019] The source follower transistor has a source terminal connected to a power signal, a gate terminal connected to the first output terminal, and a drain terminal connected to a drain terminal of the readout transistor;

[0020] The drain terminal of the readout transistor is connected to the drain terminal of the source follower transistor, the gate terminal receives a readout signal, and the source terminal serves as a second output terminal.

[0021] Optionally, the pulse trigger unit includes: a first inverter, a second inverter, a pulse output transistor and a request output circuit;

[0022] The first inverter and the second inverter are connected in series, the first signal is received through the input end of the first inverter, and the output end of the second inverter is connected to the request output circuit, the pulse latch unit and the drain end of the pulse output transistor;

[0023] The request output circuit outputs the read request signal according to the control of the second inverter and the pulse latch circuit;

[0024] The gate terminal of the pulse output transistor receives the enable signal, and the source terminal serves as a pulse output terminal to output the third signal obtained based on the first signal.

[0025] Optionally, the pulse trigger unit further includes: a pull-down transistor;

[0026] The source terminal of the pull-down transistor is grounded, and is connected in parallel with the first inverter through the drain terminal and the gate terminal, the drain terminal receives the first signal, and the gate terminal is connected to the connection point of the first inverter and the second inverter; in response to the first inverter outputting a high level, the pull-down transistor is turned on to ground the first output terminal.

[0027] Optionally, the request output circuit comprises: an enable transistor and a request transistor;

[0028] The drain terminal of the enabling transistor is connected to the power signal, the source terminal is connected to the source terminal of the request transistor, and the gate terminal is connected to the pulse latch unit. In response to the fourth signal latched by the pulse latch unit being at a high level, the enabling transistor is turned on;

[0029] The source terminal of the request transistor is connected to the source terminal of the enable transistor, the gate terminal is connected to the output terminal of the second inverter, and the drain terminal serves as a fourth output terminal; in response to the first signal being at a low level and the enable transistor being turned on, a read request signal is output through the fourth output terminal.

[0030] Optionally, the pulse latch unit comprises: a trigger reset transistor, a trigger termination transistor and a latch circuit;

[0031] The source terminal of the trigger reset transistor is connected to the power supply signal, the drain terminal is connected to the source terminal of the trigger termination transistor and the pulse trigger unit as a latch point, and the gate terminal receives the reset signal;

[0032] The latch circuit is connected to the pulse trigger unit and the latch point, and is used to control the latch point to latch or write the fourth signal according to the reset signal and the enable signal;

[0033] The source terminal of the trigger termination transistor is connected to the latch point, the drain terminal is connected to the pulse trigger unit, and the gate terminal receives the enable signal. In response to the trigger termination transistor receiving a enable signal within a photosensitive cycle, the trigger termination transistor is turned on, so that the fourth signal is pulled down to a low level, thereby disconnecting the path for the pulse trigger unit to send the read request signal.

[0034] Optionally, the latch circuit comprises: a first latch transistor and a second latch transistor;

[0035] The gate terminal of the first latch transistor receives the reset signal, the source terminal is connected to the source terminal of the second latch transistor, and the drain terminal is connected to the latch point;

[0036] The source terminal of the second latch transistor is connected to the source terminal of the first latch transistor, the gate terminal receives the enable signal, and the drain terminal is connected to the latch point;

[0037] In response to the reset signal controlling the first latch transistor to be disconnected, the latch point is in a writable state, and the fourth signal is reset to a high level; in response to the reset signal controlling the first latch transistor to be turned on, and the enable signal controlling the second latch transistor to be turned on, the high-level fourth signal is latched in the latch point.

[0038] Optionally, the latch circuit further includes: a third inverter and a fourth inverter;

[0039] The third inverter and the fourth inverter are connected in series to connect the latch point and the drain end of the first latch transistor. The connection point between the third inverter and the fourth inverter is also connected to the gate end of the enable transistor in the pulse trigger unit. In response to the fourth signal being at a high level, the enable transistor is controlled to be turned on.

[0040] Another aspect of the embodiments of the present disclosure provides a signal processing circuit, comprising: a pixel array consisting of n rows and m columns of sensor pixel units as described in any one of the above embodiments, a row drive control module, a row arbitration module and a column readout module; n and m are integers greater than or equal to 1 respectively;

[0041] The row drive control module is used to provide reset signals, transfer signals and readout signals to the sensor pixel units in the pixel array row by row;

[0042] The pixel array is used to perform a reset according to the reset signal, send a read request signal to the row arbitration module in response to the first signal reaching a preset threshold value during a photosensitive period, and send a third signal to the column readout module under the control of the enable signal fed back by the row arbitration module; when the photosensitive period is reached, send a second signal to the column readout module under the control of the transfer signal and the readout signal; the third signal is determined based on the first signal;

[0043] The row arbitration module is used to receive the read request signal sent by at least one row of the sensor pixel units in the pixel array, and feed back the permission signal to at least one row of the sensor pixel units according to the time sequence of receiving the read request signal;

[0044] The column readout module is used to receive the third signal and the second signal sent by at least one column of the sensor pixel units.

[0045] Optionally, it also includes: a row address encoder and a clock module;

[0046] When the row arbitration module feeds back an enabling signal to a row of the sensor pixel units, the row address encoder encodes row information of the sensor pixel units receiving the enabling signal into a row address;

[0047] The clock module is used to record the time information when the row address encoder generates the row address, and associate the time information with the row address.

[0048] Optionally, the column readout module comprises: m analog-to-digital converters, m column buffers and a column address encoder; each of the analog-to-digital converters corresponds to a column of the sensor pixel units, each of the column buffers corresponds to a column of the sensor pixel units; each of the analog-to-digital converters corresponds to one of the column buffers;

[0049] The column buffer is used to store the third signal output by the sensor pixel unit of the corresponding column and transmit the third signal to the column address encoder;

[0050] The column address encoder is used to receive the third signal output by the column buffer, encode the column information corresponding to the third signal into a column address, and associate the column address with the row address based on the time information to determine the sensor pixel unit corresponding to the third signal;

[0051] The analog-to-digital converter is used to receive the second signal output by the sensor pixel unit of the corresponding column, perform a differential operation on two consecutively received second signals, and perform analog-to-digital conversion on the differential operation result to obtain a fifth signal.

[0052] Optionally, it also includes: a conversion interface circuit;

[0053] The conversion interface circuit is used to receive the signal output by the column readout module.

[0054] Another aspect of the embodiments of the present disclosure provides an electronic device, comprising: a processor, and a memory communicatively connected to the processor, and further comprising the sensor pixel unit described in any of the above embodiments or the signal processing circuit described in any of the above embodiments;

[0055] The memory stores computer-executable instructions;

[0056] The processor executes the computer-executable instructions stored in the memory to control the sensor pixel unit or the signal processing circuit.

[0057] Optionally, the electronic device is included in any one of the following: image data acquisition equipment, audio / video player, navigation equipment, entertainment equipment, communication equipment, roadside traffic facilities, equipment in motor vehicles, industrial inspection equipment, flight equipment, medical equipment, security equipment.

[0058] The sensor pixel unit, signal processing circuit and electronic device provided based on the above embodiments of the present disclosure include: a photosensitive unit, a pulse trigger unit and a pulse latch unit; the photosensitive unit is used to receive a light signal within an exposure time to generate a first signal, and in response to the first signal reaching a preset threshold, the first signal is sent to the pulse trigger unit through a first output terminal; and when the photosensitive period is reached, a second signal is output through a second output terminal; the pulse trigger unit is used to send a read request signal to the outside according to the first signal, and output a third signal according to a feedback permission signal; the pulse latch unit is used to latch a fourth signal as a high level according to the control of a reset signal, and turn on the path for the pulse trigger unit to send the read request signal when the fourth signal is at a high level; in response to receiving the permission signal within a photosensitive period, the pulse trigger unit is controlled to stop outputting the third signal. In the disclosed embodiment, when the first signal reaches a preset threshold value within the photosensitive period, a third signal is requested to be issued to realize asynchronous reading of the pixel unit; and when the photosensitive period is reached, a second signal is output to realize synchronous reading of the pixel unit; a working mode combining synchronous reading and asynchronous reading of the pixel unit is realized, and while a light signal with a stronger light intensity is expressed by the asynchronously read signal, synchronous reading ensures that a light signal with a weaker light intensity is output within the photosensitive period, thereby having the beneficial effects of both synchronous reading and asynchronous reading.

[0059] The technical solution of the present disclosure is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] The accompanying drawings, which constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0061] The present disclosure may be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0062] Figure 1 is a schematic diagram of a circuit structure of a sensor pixel unit provided by an exemplary embodiment of the present disclosure;

[0063] Figure 2 is a schematic diagram of a circuit structure of a photosensitive unit in a sensor pixel unit provided by another exemplary embodiment of the present disclosure;

[0064] Figure 3 is a schematic diagram of a circuit structure of a photosensitive unit in a sensor pixel unit provided by another exemplary embodiment of the present disclosure;

[0065] Figure 4 is a schematic diagram of a circuit structure of a pulse trigger unit in a sensor pixel unit provided by another exemplary embodiment of the present disclosure;

[0066] Figure 5 is a schematic diagram of a circuit structure of a pulse trigger unit in a sensor pixel unit provided by another exemplary embodiment of the present disclosure;

[0067] Figure 6a is a schematic diagram of a circuit structure of a pulse latch unit in a sensor pixel unit provided by yet another exemplary embodiment of the present disclosure;

[0068] Figure 6b is a circuit structure diagram of a pulse latch unit in a sensor pixel unit provided by yet another exemplary embodiment of the present disclosure;

[0069] Figure 7 is a schematic diagram of a circuit structure of a sensor pixel unit provided by an optional exemplary embodiment of the present disclosure;

[0070] Figure 8 is a circuit structure diagram of a signal processing circuit provided by an exemplary embodiment of the present disclosure;

[0071] Fig. 9 is a circuit structure diagram of a signal processing circuit provided by another exemplary embodiment of the present disclosure;

[0072] Fig.10 The figure is a schematic diagram of the structure of an application embodiment of the electronic device disclosed in the present invention. DETAILED DESCRIPTION

[0073] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless otherwise specifically stated.

[0074] Those skilled in the art can understand that the terms "first" and "second" in the embodiments of the present disclosure are only used to distinguish different steps, devices or modules, etc., and neither represent any specific technical meaning nor indicate the necessary logical order between them.

[0075] It should also be understood that in the embodiments of the present disclosure, “plurality” may refer to two or more than two, and “at least one” may refer to one, two, or more than two.

[0076] It should also be understood that any component, data or structure mentioned in the embodiments of the present disclosure can generally be understood as one or more, unless explicitly limited or otherwise indicated in the context.

[0077] In addition, the term "and / or" in the present disclosure is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in the present disclosure generally indicates that the associated objects before and after are in an "or" relationship.

[0078] It should also be understood that the description of the various embodiments in the present disclosure focuses on the differences between the various embodiments, and the same or similar aspects thereof can be referenced to each other, and for the sake of brevity, they will not be described one by one.

[0079] At the same time, it should be understood that for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0080] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present disclosure, its application, or uses.

[0081] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0082] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0083] The embodiments of the present disclosure can be applied to electronic devices such as terminal devices, computer systems, servers, etc., which can operate with many other general or special computing system environments or configurations. Examples of well-known terminal devices, computing systems, environments and / or configurations suitable for use with electronic devices such as terminal devices, computer systems, servers, etc. include, but are not limited to: personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, network personal computers, small computer systems, large computer systems, and distributed cloud computing technology environments including any of the above systems, etc.

[0084] Electronic devices such as terminal devices, computer systems, servers, etc. can be described in the general context of computer system executable instructions (such as program modules) executed by computer systems. Generally, program modules can include routines, programs, object programs, components, logic, data structures, etc., which perform specific tasks or implement specific abstract data types. Computer systems / servers can be implemented in a distributed cloud computing environment, where tasks are performed by remote processing devices linked through a communication network. In a distributed cloud computing environment, program modules can be located on local or remote computing system storage media including storage devices.

[0085] In the process of implementing the present disclosure, the inventors found that the synchronous reading of pixel units has the disadvantages of low time efficiency and inability to reflect the light intensity corresponding to each pixel unit; while the asynchronous reading of pixel units can make the pixel output a signal when it reaches the threshold, and reset after the output, and directly enter the next exposure. The asynchronous reading method avoids the situation where the pixel is still waiting after reaching the threshold, but for weaker light intensities, the triggering output time is longer. In a pixel array, the pixel unit that receives strong light has output signals many times, while the pixel unit that receives weak light may not have output once. This makes the information of the strong light part in the image signal very rich or even too redundant, while the information of the weak light part may be missing. Therefore, the reading method of simple synchronous output or asynchronous output is not perfect.

[0086] In view of the technical problems existing in the existing synchronous readout and asynchronous readout, the present disclosure proposes the following sensor pixel unit.

[0087] Figure 1 FIG. 1 is a schematic diagram of a circuit structure of a sensor pixel unit provided by an exemplary embodiment of the present disclosure. Figure 1 As shown, the sensor pixel unit (hereinafter referred to as pixel unit) provided in this embodiment includes: a photosensitive unit 11, a pulse trigger unit 12 and a pulse latch unit 13;

[0088] The photosensitive unit 11 is used to receive a light signal within the exposure time to generate a first signal Vpd. In response to the first signal Vpd reaching a preset threshold, the first signal Vpd is sent to the pulse trigger unit 12 through the first output terminal; and when the photosensitive period is reached, the second signal Vout is output through the second output terminal.

[0089] The second signal Vout is determined based on the first signal Vpd, and the value of the second signal Vout is correlated with the value of the first signal Vpd.

[0090] The photosensitive unit 11 in this embodiment can be a photosensitive unit of a 4T structure (including 4 transistors), through which the photosensitive unit outputs a first signal Vpd when the first signal generated based on the light signal reaches a preset threshold, thereby realizing asynchronous reading of the pixel unit, realizing that the light intensity of the pixel unit can be reflected by the duration of the accumulation of photogenerated charges when the light intensity is strong, thereby avoiding the situation where the pixel unit is still waiting after reaching the preset threshold. At the same time, for the case of weak light intensity, the photosensitive unit provided in this embodiment realizes synchronous reading of the pixel unit by outputting a second signal Vout when the light intensity period is reached, thereby ensuring that the signal with weak light intensity is output within one light intensity period.

[0091] The pulse trigger unit 12 is used to send a read request signal to the outside according to the first signal Vpd, and output a third signal Vspi according to the feedback permission signal.

[0092] The third signal Vspi is determined based on the first signal Vpd.

[0093] Optionally, the third signal Vspi is a pulse signal, and the reading of the third signal is controlled by an enabling signal, so that the asynchronous reading of the third signal is controllable.

[0094] The pulse latch unit 13 is used to latch the fourth signal according to the control of the reset signal, and in response to the fourth signal being at a high level, turn on the path for the pulse trigger unit 12 to send a read request signal; and in response to receiving an over-enabling signal within a photosensitive cycle, disconnect the path for the pulse trigger unit 12 to send a read request signal.

[0095] In this embodiment, the pulse latch unit is controlled to asynchronously output only one third signal within one photosensitive cycle. Once the permission signal is received within one photosensitive cycle, the pulse trigger unit 12 is controlled to disconnect the path for sending a read request signal, that is, the pulse trigger unit 12 is controlled to stop outputting the third signal, thereby reducing the frequency difference between the synchronous output and the asynchronous output in the pixel unit, and avoiding the problem of redundant information in the strong light part due to too many asynchronous read output signals in the case of strong light intensity.

[0096] The sensor pixel unit, signal processing circuit and electronic device provided by the above-mentioned embodiments of the present disclosure include: a photosensitive unit, a pulse trigger unit and a pulse latch unit; the photosensitive unit is used to receive a light signal within an exposure time to generate a first signal, and in response to the first signal reaching a preset threshold, the first signal is sent to the pulse trigger unit through a first output terminal; and when the photosensitive period is reached, a second signal is output through a second output terminal; the pulse trigger unit is used to send a read request signal to the outside according to the first signal, and output a third signal according to a feedback enable signal; the pulse latch unit is used to latch a fourth signal as a high level according to the control of a reset signal, and turn on the path for the pulse trigger unit to send the read request signal when the fourth signal is at a high level; and trigger the termination transistor to be turned on according to the enable signal, and control the pulse trigger unit to stop outputting the third signal through the conduction of the termination transistor. In the disclosed embodiment, when the first signal reaches a preset threshold value within the photosensitive period, a third signal is requested to be issued to realize asynchronous reading of the pixel unit; and when the photosensitive period is reached, a second signal is output to realize synchronous reading of the pixel unit; a working mode combining synchronous reading and asynchronous reading of the pixel unit is realized, and while a light signal with a stronger light intensity is expressed by the asynchronously read signal, synchronous reading ensures that a light signal with a weaker light intensity is output within the photosensitive period, thereby having the beneficial effects of both synchronous reading and asynchronous reading.

[0097] Figure 2 FIG. 1 is a schematic diagram of a circuit structure of a photosensitive unit in a sensor pixel unit provided by another exemplary embodiment of the present disclosure. Figure 2 As shown, the photosensitive unit 11 in the sensor pixel unit provided in this embodiment includes a first photodiode 111, a second photodiode 112, a reset transistor 113, a transfer transistor 114 and an auxiliary circuit 115;

[0098] The first photodiode 111 is used to receive a light signal within an exposure time to generate a voltage signal, and in response to reaching a light-sensitive period, transmit the voltage signal to the second photodiode through a transfer transistor.

[0099] A photodiode is a photodetector that can convert light into current or voltage signals depending on how it is used. The die often uses a PN junction with photosensitive characteristics, which is very sensitive to changes in light, has unidirectional conductivity, and changes electrical properties when the light intensity is different. Therefore, the light intensity can be used to change the voltage or current in the circuit.

[0100] The second photodiode 112 is used to receive a light signal within the exposure time to generate a voltage signal. During the photosensitive period, in response to the voltage signal reaching a preset threshold, a first signal Vpd is output at the first output terminal based on the voltage signal. In response to reaching the photosensitive period, the voltage signal transmitted by the first photodiode 111 is received, and the voltage signal is output to the auxiliary circuit 115.

[0101] In this embodiment, two photodiodes (the first photodiode 111 and the second photodiode 112) simultaneously convert the light signal corresponding to the position of the pixel unit, and asynchronous reading is realized through the second photodiode 112, so that when the converted voltage signal of the second photodiode 112 reaches the preset threshold, the first signal Vpd is output. In addition, since the transfer transistor 114 is in the off state at this time, the voltage signal in the first photodiode 111 has no effect on the first signal, and asynchronous signal reading is realized by relying on only one photodiode. By determining the time of reading the first signal, the light intensity corresponding to the position of the pixel unit can be determined.

[0102] The reset transistor 113 is used to control the second photodiode 112 to perform a reset according to a reset signal.

[0103] In this embodiment, whether the second photodiode 112 is reset is controlled by turning on or off the reset transistor. Optionally, the source of the reset transistor 113 is connected to the power supply signal Vdd, and the drain is connected to one end of the second photodiode 112. The reset signal received by the gate is turned on or off. When the reset transistor 113 is turned on, the second photodiode 112 is connected to the power supply signal Vdd, thereby resetting the second photodiode 112.

[0104] Optionally, the reset transistor is an N-type transistor, and the reset transistor is turned on in response to the reset signal being at a high level; optionally, the reset transistor is a P-type transistor, and the reset transistor is turned on in response to the reset signal being at a low level.

[0105] When the transfer transistor 114 is turned on, the first photodiode 112 transfers all converted voltage signals to the second photodiode 112 to achieve reset.

[0106] The transfer transistor 114 is used to provide a connection path between the first photodiode 111 and the second photodiode 112 .

[0107] The auxiliary circuit 115 is used to control the second output terminal to output the second signal Vout according to the received voltage signal when the light-sensing period is reached.

[0108] In this embodiment, whether the first photodiode 111 and the second photodiode 112 are conductive or not is controlled by turning on or off the transfer transistor 114. Optionally, the conductive or disconnected state is controlled by a transfer signal. For example, in response to reaching a photosensitive period, the transfer signal is at a high level, and the transfer transistor 114 is controlled to be conductive, and the first photodiode 111 and the second photodiode 112 are conductive. The voltage signal in the first photodiode 111 is transferred to the second photodiode 112 through the connecting path. At this time, the voltage signal at the first output end is the voltage signal collected and converted in the first photodiode 111. Since the first photodiode 111 has not output any signal before the transfer transistor 114 is turned on, when the photosensitive period is reached, the output is a voltage signal generated by all photogenerated charges accumulated in the first photodiode 111 within a photosensitive period, thereby realizing synchronous reading of the signal.

[0109] Figure 3 FIG. 1 is a schematic diagram of a circuit structure of a photosensitive unit in a sensor pixel unit provided by another exemplary embodiment of the present disclosure. Figure 3 As shown, the auxiliary circuit 115 includes a source follower transistor 1151 and a readout transistor 1152 .

[0110] One end of the first photodiode 111 is connected to the ground GND, and the other end is connected to the drain terminal of the transfer transistor 114 .

[0111] One end of the second photodiode 112 is grounded, and the other end is connected to the source end of the transfer transistor 114 , the drain end of the reset transistor 113 , and the gate end of the source follower transistor 1151 , and the connection point serves as the first output end.

[0112] The reset transistor 113 has a source terminal connected to the power signal Vdd, a drain terminal connected to the other end of the second photodiode 112 , and a gate terminal receiving a reset signal RST.

[0113] The transfer transistor 114 connects the first photodiode 111 and the second photodiode 112 via a source terminal and a drain terminal, receives a transfer signal TX at a gate terminal, and conducts a connection path between the first photodiode 111 and the second photodiode 112 according to the control of the transfer signal TX.

[0114] Optionally, the transfer transistor 114 may be an N-type transistor, which is turned on in response to the transfer signal TX being at a high level; the transfer transistor 114 may also be a P-type transistor, which is turned on in response to the transfer signal TX being at a low level.

[0115] The source follower transistor 1151 has a source terminal connected to the power supply signal Vdd, a gate terminal connected to the first output terminal, and a drain terminal connected to the drain terminal of the readout transistor 1152 .

[0116] In response to the first signal at the first output terminal being at a high level, the source follower transistor 1151 is turned on, so that the drain terminal of the readout transistor 1152 is connected to the power supply signal Vdd.

[0117] The drain terminal of the readout transistor 1152 is connected to the drain terminal of the source follower transistor 1151 , the gate terminal receives the readout signal Read, and the source terminal serves as a second output terminal.

[0118] Optionally, the source follower transistor 1151 and the readout transistor 1152 are generally N-type transistors, and are in a turned-on state according to receiving a high level at the gate.

[0119] The 4T photosensitive unit provided in this embodiment includes two photodiodes, and synchronous reading and asynchronous reading are respectively realized through the two photodiodes, and two different output terminals are provided for synchronous reading and asynchronous reading, so that the signals output by synchronous reading and asynchronous reading are independent of each other and do not interfere with each other, so that the pixel unit can combine the advantages of synchronous reading and asynchronous reading, and overcome the disadvantages of both.

[0120] Figure 4 FIG. 1 is a schematic diagram of a circuit structure of a pulse trigger unit in a sensor pixel unit provided by another exemplary embodiment of the present disclosure. Figure 4 As shown, the pulse trigger unit 12 provided in this embodiment includes: a first inverter 121 , a second inverter 122 , a pulse output transistor 123 and a request output circuit 124 .

[0121] The first inverter 121 and the second inverter 122 are connected in series, and the first signal Vpd is received through the input end of the first inverter 121 . The output end of the second inverter 122 is connected to the request output circuit 124 , the pulse latch unit 13 and the drain end of the pulse output transistor 123 .

[0122] The request output circuit 124 outputs a read request signal Req according to the control of the second inverter and the pulse latch circuit 13 .

[0123] The gate terminal of the pulse output transistor 123 receives the enable signal Ack, and the source terminal serves as a pulse output terminal to output the third signal Vspi obtained based on the first signal Vpd.

[0124] Optionally, the third signal Vspi may be a pulse signal.

[0125] In this embodiment, the voltage of the first signal is sorted by two inverters connected in series to obtain a sorted third signal, and the level of the third signal is consistent with that of the first signal. For example, when the first signal is at a high level (not 1), a pulse signal with an output of 1 can be obtained as the third signal through the sorting of the two inverters. When the first signal is at a low level (not 0), a pulse signal with an output of 0 can be obtained as the third signal through the sorting of the two inverters. In addition, in this embodiment, whether to output the third signal is determined by the conduction of the pulse output transistor 123. Only when a high-level permission signal is received, the pulse output transistor 123 is controlled to be turned on, so that the pulse output terminal is connected to the output terminal of the second inverter, and the third signal is output through the pulse output terminal. Before receiving the permission signal, the pulse output transistor 123 is in a normally disconnected state and cannot output the third signal.

[0126] Figure 5 FIG. 1 is a schematic diagram of a circuit structure of a pulse trigger unit in a sensor pixel unit provided by another exemplary embodiment of the present disclosure. Figure 5 As shown, the pulse trigger unit 12 further includes: a pull-down transistor 125;

[0127] The source terminal of the pull-down transistor 125 is grounded, and is connected in parallel with the first inverter 121 through the drain terminal and the gate terminal. The drain terminal receives the first signal, and the gate terminal is connected to the connection point between the first inverter 121 and the second inverter 122. In response to the first inverter outputting a high level, the pull-down transistor is turned on to ground the first output terminal.

[0128] The pull-down transistor 125 is an N-type transistor.

[0129] In this embodiment, when the first signal is at a low level, the signal input to the gate of the pull-down transistor 125 is at a high level, and the pull-down transistor 125 is turned on. In response to the first signal dropping to a preset threshold, the pull-down transistor 125 is turned on, the first output terminal is grounded, and the first signal is quickly dropped from the preset threshold to a 0 level. Compared with the prior art in which the first signal drops slowly, this embodiment uses the pull-down transistor to accurately locate the time when the first signal drops to the preset threshold, thereby improving the accuracy of the signal.

[0130] like Figure 5 As shown, the request output circuit 124 includes: an enable transistor 1241 and a request transistor 1242;

[0131] The drain terminal of the enable transistor 1241 is connected to the power signal Vdd, the source terminal is connected to the source terminal of the request transistor 1241, and the gate terminal is connected to the pulse latch unit 13. In response to the fourth signal latched by the pulse latch unit 13 being at a high level, the enable transistor 1241 is turned on.

[0132] The source terminal of the request transistor 1242 is connected to the source terminal of the enable transistor 1241, the gate terminal is connected to the output terminal of the second inverter 122, and the drain terminal serves as the fourth output terminal; in response to the first signal being at a low level and the enable transistor being turned on, the read request signal Req is output through the fourth output terminal.

[0133] In this embodiment, the connection path from the power supply signal Vdd to the fourth output terminal is formed by the enable transistor 1241 and the request transistor 1242. Only when the enable transistor 1241 and the request transistor 1242 are turned on at the same time, the high-level read request signal Req is output from the fourth output terminal; wherein, whether the enable transistor 1241 is turned on is determined by the fourth signal latched by the pulse latch unit 13, and whether the request transistor 1242 is turned on is determined by the third signal obtained by flipping the first signal twice. Optionally, both the enable transistor 1241 and the request transistor 1242 are P-type transistors, that is, they are turned on when the signal input to the gate terminal is at a low level. The external circuit feeds back a high-level permission signal according to the high-level read request signal Req, and turns on the pulse output transistor 123 through the permission signal. At this time, the third signal is output through the third output terminal.

[0134] Figure 6a FIG. 1 is a schematic diagram of a circuit structure of a pulse latch unit in a sensor pixel unit provided by yet another exemplary embodiment of the present disclosure. Figure 6a As shown, the pulse latch unit 13 provided in this embodiment includes: a trigger reset transistor 131 , a trigger termination transistor 132 and a latch circuit 133 .

[0135] The source terminal of the trigger reset transistor 131 is connected to the power supply signal, the drain terminal is connected to the source terminal of the trigger termination transistor 132 and the pulse trigger unit 12 as a latch point, and the gate terminal receives the reset signal RST;

[0136] The latch circuit 133 is adjacent to the pulse trigger unit 12 and the latch point, and is used to control the latch point to latch or write the fourth signal according to the reset signal RST and the enable signal Ack.

[0137] The source terminal of the trigger termination transistor 132 is connected to the latch point, the drain terminal is connected to the pulse trigger unit, and the gate terminal receives the enable signal Ack. In response to the trigger termination transistor receiving an enable signal Ack within a photosensitive cycle, the trigger termination transistor 132 is turned on, so that the fourth signal is pulled down to a low level, disconnecting the path for the pulse trigger unit 12 to send a read request signal, and the pulse trigger unit 12 cannot send a read request signal.

[0138] Optionally, the drain terminal of the trigger termination transistor 132 is connected to the output terminal of the second inverter 122 of the pulse trigger unit and the drain terminal of the pulse output transistor 123 .

[0139] In this embodiment, the pulse latch unit is used to record whether the pixel unit has triggered an asynchronous pulse output within a photosensitive cycle. When a first signal reaching a preset threshold is generated in the photosensitive unit, and the fourth signal latched by the latch point after being controlled by the reset signal is high, the read request signal sending link in the pulse trigger unit 12 is turned on. At this time, the latch circuit releases the latch of the fourth signal according to the control of the enable signal; that is, if asynchronous output has occurred within a photosensitive cycle, the latch circuit is released from the latch of the fourth signal according to the received enable signal (in the case of asynchronous output, the enable signal is high) combined with the reset signal control, so that the pulse trigger unit cannot continue to send the read request signal, thereby ensuring that the pixel unit triggers the pulse asynchronous output at most once within a photosensitive cycle. In addition, this embodiment allows the signal Ack to turn on to trigger the termination transistor 132. When the termination transistor 132 is turned on, the latch point and the pulse trigger unit 12, the fourth signal of the latch point will be pulled to a low level. When the fourth signal is at a low level, the link for the pulse trigger unit to send a read request signal is interrupted, and the read request signal cannot be sent, that is, it is ensured that the read request signal cannot be sent before receiving the next reset signal, that is, it is achieved that only one asynchronous reading can be performed within one photosensitive cycle.

[0140] Figure 6b FIG. 1 is a schematic diagram of a circuit structure of a pulse latch unit in a sensor pixel unit provided by another exemplary embodiment of the present disclosure. Figure 6b As shown, the latch circuit 133 includes: a first latch transistor 1331 and a second latch transistor 1332;

[0141] The gate terminal of the first latch transistor 1331 receives the reset signal RST, the source terminal is connected to the source terminal of the second latch transistor 1332, and the drain terminal is connected to the latch point.

[0142] The source terminal of the second latch transistor 1332 is connected to the source terminal of the first latch transistor 1331 , the gate terminal receives the enable signal Ack, and the drain terminal is connected to the latch point.

[0143] In response to the reset signal RST, the first latch transistor 1331 is controlled to be disconnected, the latch point is in a writable state, and the fourth signal is reset to a high level; in response to the reset signal RST, the first latch transistor is controlled to be turned on, and when the enable signal controls the second latch transistor to be turned on, the high-level fourth signal is latched in the latch point.

[0144] In this embodiment, a ring circuit formed by two transistors (a first latch transistor 1331 and a second latch transistor 1332) is used to short-circuit the latch point when both transistors are turned on, thereby latching the fourth signal at the latch point. The first latch transistor 1331 and the second latch transistor 1332 form a ring circuit, so that the fourth signal is latched only when the first latch transistor and the second latch transistor are turned on at the same time. As long as one of them is disconnected, the latch circuit 133 is in a writable state, that is, the latch of the fourth signal is released.

[0145] In this embodiment, in order to realize turning on the enabling transistor in the pulse trigger unit based on the fourth signal, the enabling transistor is an N-type transistor, and when the fourth signal is at a high level, the enabling transistor is turned on.

[0146] like Figure 6b As shown, the latch circuit 133 further includes: a third inverter 1333 and a fourth inverter 1334;

[0147] The third inverter 1333 and the fourth inverter 1334 are connected in series to connect the latch point and the drain end of the first latch transistor 1331. The connection point between the third inverter 1333 and the fourth inverter 1334 is also connected to the gate end of the enable transistor 1241 in the pulse trigger unit 12. In response to the fourth signal being at a high level, the enable transistor 1241 is controlled to be turned on.

[0148] In this embodiment, the enabling transistor is a P-type transistor, and the fourth signal of the input gate is processed by the third inverter, that is, when the fourth signal is at a high level, the gate of the enabling transistor receives a low level, and the enabling transistor is turned on. At this time, if the first signal is at a low level, the request transistor is turned on, that is, the path for sending the read request signal in the pulse trigger unit is turned on. Correspondingly, if the fourth signal is pulled down to a low level by the first signal due to the trigger termination transistor being turned on, the gate of the enabling transistor receives a high level, and the enabling transistor is turned off. At this time, regardless of whether the request transistor is turned on or not, the path for the pulse trigger unit to send the read request signal is disconnected, and the request read signal cannot be sent, so that only one asynchronous reading can be achieved within one exposure cycle. The signal processed by the third inverter needs to be latched once, and therefore, this embodiment also includes a fourth inverter, and after two reverse processes, the fourth signal can be latched in the latch circuit.

[0149] Figure 7 1 is a schematic diagram of a circuit structure of a sensor pixel unit provided by an optional exemplary embodiment of the present disclosure. The figure shows the specific structures of a photosensitive unit 11, a pulse trigger unit 12 and a pulse latch unit 13 included in the pixel unit.

[0150] The photosensitive unit 11 includes: a first photodiode 111 , a second photodiode 112 , a reset transistor 113 , a transfer transistor 114 , and an auxiliary circuit 115 . The auxiliary circuit 115 includes a source follower transistor 1151 and a readout transistor 1152 .

[0151] The pulse trigger unit 12 includes: a first inverter 121 , a second inverter 122 , a pulse output transistor 123 , a request output circuit 124 , and a pull-down transistor 125 . The request output circuit 124 includes: an enable transistor 1241 and a request transistor 1242 .

[0152] The pulse latch unit 13 includes: a trigger reset transistor 131 , a trigger termination transistor 132 and a latch circuit 133 . The latch circuit 133 includes: a first latch transistor 1331 , a second latch transistor 1332 , a third inverter 1333 and a fourth inverter 1334 .

[0153] The connection relationship of the various components in this embodiment can refer to the description and drawings of the above embodiments.

[0154] Optionally, during the reset phase of each frame of the light-sensing cycle, the pulse latch unit triggers the reset transistor 131 to turn on by the reset signal RCT (low level), the first latch transistor 1331 to turn off, the latch circuit 133 is in a writable state, and the fourth signal Req_EN is reset to a high level. After the reset is completed, the reset transistor 131 is triggered to turn off, the first latch transistor 1331 is turned on (the second latch transistor 1332 is in a normally turned-on state because it does not receive a high-level permission signal), and the fourth signal Req_EN is locked to a high level, so that the enable transistor 1241 is in a turned-on state (the fourth signal is low level after being processed by the first inverter, and the enable transistor 1241 is turned on by the low level). When the photosensitive element in the pixel unit outputs a low level signal through the first output terminal, the read request signal Req is sent through the pulse trigger unit and the permission signal Ack is received, the permission signal Ack is high level, triggering the termination transistor 132 to turn on, the second latch transistor 1332 to turn off, and the latch circuit 133 is in a writable state. When the enable signal Ack is at a high level, the trigger termination transistor 132 is turned on. Since the third signal output by the pixel unit is at a low level, the fourth signal Req_EN will be set to a low level at this time. At this time, the enable transistor 1241 is disconnected, and the pulse trigger unit cannot send a read request signal. The pixel unit will no longer be able to output a read request signal before performing a reset in the next photosensitive cycle.

[0155] Figure 8 FIG. 1 is a circuit structure diagram of a signal processing circuit provided by an exemplary embodiment of the present disclosure. Figure 8As shown, the signal processing circuit provided in this embodiment includes: a pixel array 81 composed of n rows and m columns of sensor pixel units 811 (hereinafter referred to as pixel units) provided in any one of the above embodiments, a row drive control module 82, a row arbitration module 83 and a column readout module 84; n and m are integers greater than or equal to 1 respectively.

[0156] The row drive control module 82 is used to provide reset signals, transfer signals and readout signals to the sensor pixel units 811 in the pixel array 81 row by row.

[0157] In this embodiment, the row drive control module 82 provides a reset signal RST, a transfer signal TX and a readout signal Read of a corresponding period for each row of sensor pixel units 811 in the pixel array row by row according to the photosensitive period. Usually, a low level is given to the reset signal RST at the beginning of the photosensitive period (high level at other times), a low level is given to the reset signal RST at the end of the photosensitive period, and a high level is given to the transfer signal TX and the readout signal Read (low level at other times).

[0158] The pixel array 81 is used to perform a reset according to a reset signal. During the photosensitive period, in response to the first signal reaching a preset threshold, a read request signal is sent to the row arbitration module 83, and a third signal is sent to the column readout module 84 under the control of the enable signal fed back by the row arbitration module 83; when the photosensitive period is reached, a second signal is sent to the column readout module through the control of the transfer signal and the readout signal.

[0159] The third signal is determined based on the first signal. Optionally, the first signal is reversely processed twice to obtain the sorted third signal.

[0160] Optionally, the sensor pixel units 811 in the pixel array output the third signal and the second signal row by row according to the control of the row drive control module 82 .

[0161] The row arbitration module 83 is used to receive a read request signal Req sent by at least one row of sensor pixel units 811 in the pixel array 81, and feed back an enable signal Ack to at least one row of sensor pixel units according to the time sequence of receiving the read request signal.

[0162] In this embodiment, the row arbitration module 83 receives a read request signal issued by a row of sensor pixel units 811 each time. When the number of read request signals received exceeds one, the multiple read request signals Req can be sorted according to the receiving time, and the multiple read request signals can be processed in sequence, with the read request signal received first being processed first.

[0163] The column readout module 84 is configured to receive the third signal and the second signal sent by at least one column of sensor pixel units 811 .

[0164] Optionally, the column readout module receives, by column, the third signal and the second signal sent by the sensor pixel unit 811. The column readout module in this embodiment implements synchronous reading and asynchronous reading of the sensor pixel unit, and achieves the beneficial effects of synchronous reading and asynchronous reading.

[0165] The circuit structures of the row drive control module 82, the row arbitration module 83 and the column readout module 84 involved in this embodiment can all adopt the commonly used circuit structures in the prior art. The present disclosure does not limit the specific circuit structures of the row drive control module 82, the row arbitration module 83 and the column readout module 84.

[0166] Fig. 9 FIG. 1 is a circuit structure diagram of a signal processing circuit provided by another exemplary embodiment of the present disclosure. Fig. 9 As shown, the signal processing circuit provided in this embodiment further includes: a row address encoder 85 and a clock module 86;

[0167] When the row arbitration module 83 feeds back an enabling signal to a row of sensor pixel units 811 , the row address encoder 85 encodes the row information of the sensor pixel units 811 receiving the enabling signal into a row address Row addr.

[0168] In this embodiment, the circuit structure of the row address encoder may be any circuit structure that can implement address encoding in the prior art, the encoding method may be any encoding method in the prior art, and the encoded row address indicates the row where the pixel unit outputting the third signal is located.

[0169] The clock module 86 is used to record the time information Timestamp when the row address encoder 85 generates the row address, and associate the time information with the row address.

[0170] In this embodiment, the clock module may be any module in the prior art that can provide time information, and the time information is associated with the row address, that is, each row address corresponds to unique time information, so as to distinguish different row addresses.

[0171] like Fig. 9 As shown, the column readout module 84 includes: m analog-to-digital converters 841 , m column buffers 842 and a column address encoder 843 .

[0172] Each analog-to-digital converter 841 corresponds to a column of sensor pixel units 811 , each column buffer 842 corresponds to a column of sensor pixel units 811 ; and each analog-to-digital converter 841 corresponds to a column buffer 842 .

[0173] The column buffer 842 is used to store the third signal Vspi outputted by the sensor pixel unit 811 of the corresponding column, and transmit the third signal to the column address encoder 843 .

[0174] Since the third signal output by the sensor pixel unit 811 in this embodiment is read asynchronously, the output time is not when the photosensitive period is reached, and different sensor pixel units output the third signal at different times. Therefore, after receiving the third signal, the third signal is stored by the column buffer 842.

[0175] The column address encoder 843 is used to receive the third signal output by the column buffer 842, encode the column information corresponding to the third signal into a column address, and associate the column address with the row address based on the time information to determine the sensor pixel unit corresponding to the third signal.

[0176] After receiving and storing the third signal, since the column readout module reads out a corresponding column of pixel units each time, when the third signal is obtained, only the column address corresponding to the third signal can be determined. At this time, in order to determine the specific position of the pixel unit corresponding to the third signal, and then determine the light intensity of the pixel unit at the specific position, this embodiment associates the time information of obtaining the third signal with the row address and its corresponding time information based on time, and makes the row address and column address of the same time information (moment) correspond to obtain the specific position of the pixel unit corresponding to the third signal corresponding to the time information (the row address and the column address determine the unique position). Based on the position and time corresponding to the third signal, the light intensity corresponding to each pixel unit in the pixel array can be determined. Optionally, the shorter the time information of outputting the third signal relative to the reset time interval, the greater the light intensity corresponding to the position.

[0177] The analog-to-digital converter 841 is used to receive the second signal Vout output by the sensor pixel unit of the corresponding column, perform a differential operation on two consecutively received second signals Vout, and perform analog-to-digital conversion on the differential operation result to obtain a fifth signal.

[0178] The second signal in this embodiment is a voltage signal associated with the first signal output by the photodiode, and is correlated with the first signal reflecting the amount of photogenerated charge accumulated by the photodiode. It can be understood that there is a fixed difference between the second signal and the first signal. Performing a differential operation on the two second signals is equivalent to performing a differential operation on the two first signals. The voltage difference between before and after the first photodiode receives light to generate photogenerated charges during the photosensitivity period can be determined, that is, the amount of photogenerated charge generated by the first photodiode according to the received light is determined. Therefore, this embodiment performs a differential operation on the two second signals in the analog-to-digital converter to determine the fifth signal that is output synchronously.

[0179] like Fig. 9 As shown, the signal processing circuit provided in this embodiment further includes: a conversion interface circuit 87.

[0180] The conversion interface circuit 87 is used to receive the signal output by the column readout module 84 .

[0181] In this embodiment, after the signal processing circuit obtains the third signal and the fifth signal, in order to facilitate other devices or circuits to process and / or use the third signal and the fifth signal, this embodiment receives the signal output by the column readout module through a conversion interface circuit and provides an interface to connect with an external circuit or device.

[0182] The signal processing circuit provided by the embodiment of the present disclosure first enters the reset stage during operation, and a low-level reset signal RST is given by the row drive control module to control the clearing of the photogenerated charge on the first photodiode and the second photodiode in the pixel unit, and the fourth signal Req_EN in the pulse latch unit in the pixel unit is reset to a high level. After the reset is completed, the exposure stage is entered, and the first photodiode and the second photodiode start to be exposed at the same time, and the photogenerated charge begins to be accumulated at the same time. During the photosensitive period, the light intensity received by different pixel units is different. The pixel unit that receives stronger light reaches the preset threshold during the photosensitive period. The first signal is low, which triggers the asynchronous output. The pixel unit that triggers the asynchronous output first enters the trigger request stage, and the first signal is input to the pulse trigger unit. After the first inverter and the second inverter are sorted, a low-level voltage signal is obtained to turn on the request transistor. At this time, since the fourth signal is high, the enable transistor is also turned on. Therefore, at this time, the drain end (fourth output end) of the request transistor pulls the read request signal Req of the row to a high level, and sends a read request signal Req to the row arbitration circuit. The row arbitration module determines the priority of the row where the pixel unit currently sending the request is located, and sends an enable signal Ack to the row pixel unit with the highest priority. The priority is determined by the arrival time of the read request signal Req, and the signal that arrives first is fed back with the enable signal first. The third signal Vspi of a row of pixel units that are allowed to output is input to the column buffer. The row address encoder, the column address encoder and the clock module record and read out the current moment, the currently allowed row address, and the column address of all pixel units in the row that reach the preset threshold, and determine the specific address of the asynchronously read pixel unit. After the exposure time (photosensitive cycle) ends, the pixel unit enters the synchronous readout stage. First, the second photodiode is reset, and the second signal Vout at this time is read out to the analog-to-digital converter, and then the transfer transistor is turned on (the transfer signal TX is set to a high level), the photogenerated charge accumulated on the first photodiode is transferred to the second photodiode, and then Vout at this time is read out, and the second signal read out twice is differentially operated in the analog-to-digital converter, and the differential result is analog-to-digital converted and read out. After all signals are read out, a frame cycle is completed. This cycle can be repeated for continuous imaging.

[0183] The signal processing circuit provided in the embodiment of the present disclosure can be integrated in one or more chips. In an optional example, the signal processing circuit is integrated in one chip. The chip mainly includes a pixel array 81, a row drive control module 82, a row arbitration module 83, a row address encoder 85, a column readout module 84, a clock module 86 and a conversion interface circuit 87. The row drive control module 82, the row arbitration module 83, the row address encoder 85, the column readout module 84, the clock module 86 and the conversion interface circuit 87 are all prior art, so the detailed implementation method thereof is not described in detail in this embodiment, and only the logical functions thereof in the present disclosure are described. Among them, the pixel array is composed of the pixel units provided in the above embodiment of n rows and m columns. The row drive control module is used to output the signal timing of the reset signal RST, the transfer signal TX and the readout signal Read of all row pixel units. The row arbitration module is used to receive the request signal Req output by all row pixel units, and output the enable signal Ack to the row pixel unit with the highest current output priority. All row enable signals Ack are simultaneously output to the row address encoder, which encodes the specific position of the currently enabled row pixel unit into a row address (Row addr) and outputs it, and at the same time controls the clock module to output the current time (Timestamp). The column readout module mainly includes m column-level analog-to-digital converters (ADCs), m-bit column buffers, and column address encoders. When the Read signal of a row of pixel units is high (outputting the second signal), the row of pixel units outputs the second signal Vout to the analog-to-digital converter of the corresponding column for analog-to-digital conversion. When a row of pixel units receives an enable signal (high level), the third signal Vspi (pulse signal) of the row of pixel units will be input to the corresponding column buffer. The column address encoder performs address encoding on the position of the third signal in the column buffer and outputs it to the conversion interface circuit. The analog-to-digital converter outputs the result to the conversion interface circuit after completing the analog-to-digital conversion each time. For weak light signals, the digital signal converted from the accumulated photogenerated charge signal within an exposure cycle can reflect the specific light intensity; for strong light signals, the moment when the photogenerated charge signal accumulates to the threshold can reflect the specific light intensity.

[0184] In addition, an embodiment of the present disclosure further provides an electronic device, including:

[0185] Memory for storing computer programs;

[0186] The processor is used to execute the computer program stored in the memory, and when the computer program is executed, the sensor pixel unit or the signal processing circuit described in any of the above embodiments of the present disclosure is implemented.

[0187] The electronic device provided by the present disclosure can be included in any of the following: image data acquisition equipment, audio / video player, navigation equipment, entertainment equipment, communication equipment, roadside traffic facilities, equipment in motor vehicles, industrial inspection equipment, flight equipment, medical equipment, security equipment, etc.

[0188] The electronic device provided by the present disclosure can be applied to any of the following: image data acquisition equipment, audio / video players, navigation equipment, entertainment equipment, communication equipment, roadside traffic facilities, equipment in motor vehicles, industrial inspection equipment, flight equipment, medical equipment, security equipment, etc.

[0189] Fig.10 This is a schematic diagram of the structure of an application embodiment of the electronic device disclosed in the present invention. Fig.10 The electronic device according to the embodiment of the present disclosure is described. The electronic device may be any one or both of the first device and the second device, or a stand-alone device independent of them, and the stand-alone device may communicate with the first device and the second device to receive the collected input signals from them.

[0190] like Fig.10 As shown, the electronic device includes one or more processors and memory.

[0191] The processor may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device to perform desired functions.

[0192] The memory may store one or more computer program products, and the memory may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, a random access memory (RAM) and / or a cache memory (cache), etc. The non-volatile memory may include, for example, a read-only memory (ROM), a hard disk, a flash memory, etc. One or more computer program products may be stored on the computer-readable storage medium, and the processor may run the computer program product to implement the sensor pixel unit or signal processing circuit of each embodiment of the present disclosure described above and / or other desired functions.

[0193] In one example, the electronic device may further include: an input device and an output device, and these components are interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0194] In addition, the input device may also include, for example, a keyboard, a mouse, and the like.

[0195] The output device can output various information to the outside, including determined distance information, direction information, etc. The output device can include, for example, a display, a speaker, a printer, a communication network and a remote output device connected thereto, and the like.

[0196] Of course, to simplify, Fig.10 Only some of the components related to the present disclosure in the electronic device are shown, and components such as a bus, an input / output interface, etc. are omitted. In addition, according to specific application situations, the electronic device may further include any other appropriate components.

[0197] In addition to the above-mentioned methods and devices, an embodiment of the present disclosure may also be a computer program product, which includes computer program instructions, which, when executed by a processor, enable the processor to execute the sensor pixel unit or signal processing circuit according to various embodiments of the present disclosure described in the above part of this specification.

[0198] The computer program product may be written in any combination of one or more programming languages ​​to write program code for performing the operations of the disclosed embodiments, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0199] In addition, an embodiment of the present disclosure may also be a computer-readable storage medium having computer program instructions stored thereon, which, when executed by a processor, enables the processor to execute the sensor pixel unit or signal processing circuit according to various embodiments of the present disclosure described in the above part of this specification.

[0200] The computer readable storage medium can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium can include, for example, but is not limited to, a system, device or device of electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0201] The basic principles of the present disclosure are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present disclosure are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present disclosure. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, and are not limitations. The above details do not limit the present disclosure to the necessity of adopting the above specific details to be implemented.

[0202] Each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the system embodiment, since it basically corresponds to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0203] The block diagrams of the devices, apparatuses, equipment, and systems involved in this disclosure are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including," "comprising," "having," and the like are open words, referring to "including but not limited to," and can be used interchangeably therewith. The words "or" and "and" used herein refer to the words "and / or," and can be used interchangeably therewith, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to," and can be used interchangeably therewith.

[0204] The method and apparatus of the present disclosure may be implemented in many ways. For example, the method and apparatus of the present disclosure may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above order of steps for the method is for illustration only, and the steps of the method of the present disclosure are not limited to the order specifically described above, unless otherwise specifically stated. In addition, in some embodiments, the present disclosure may also be implemented as a program recorded in a recording medium, which includes machine-readable instructions for implementing the method according to the present disclosure. Therefore, the present disclosure also covers a recording medium storing a program for executing the method according to the present disclosure.

[0205] It should also be noted that in the apparatus, device and method of the present disclosure, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as equivalent solutions of the present disclosure.

[0206] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the aspects shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0207] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present disclosure to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. A sensor pixel unit, characterized in that: include: Photosensitive unit, pulse trigger unit, pulse latch unit; The photosensitive unit is used to receive the light signal within the exposure time to generate a first signal, and in response to the first signal reaching a preset threshold, send the first signal to the pulse trigger unit through the first output terminal; And when the photosensitive period is reached, a second signal is output through the second output terminal; The pulse trigger unit is used to send a read request signal to the outside according to the first signal, and output a third signal according to the feedback permission signal; The pulse latch unit is used to latch the fourth signal according to the control of the reset signal, and to conduct the path for the pulse trigger unit to send the read request signal in response to the fourth signal being at a high level; In response to receiving the enabling signal within a photosensitive period, the path for the pulse trigger unit to send the read request signal is disconnected.

2. The pixel unit according to claim 1, characterized in that: The photosensitive unit includes a first photodiode, a second photodiode, a reset transistor, a transfer transistor and an auxiliary circuit; The first photodiode is used to receive a light signal within an exposure time to generate a voltage signal, and in response to reaching the light-sensitive period, transmit the voltage signal to the second photodiode through the transfer transistor; The second photodiode is used to receive a light signal within an exposure time to generate a voltage signal, and in response to the voltage signal reaching a preset threshold value during the photosensitive period, output the first signal at the first output terminal based on the voltage signal, and in response to reaching the photosensitive period, receive the voltage signal transmitted by the first photodiode, and output the voltage signal to the auxiliary circuit; The reset transistor is used to control the second photodiode to perform reset according to a reset signal; The transfer transistor is used to provide a connection path between the first photodiode and the second photodiode; The auxiliary circuit is used to control the second output terminal to output the second signal according to the received voltage signal when the light-sensitive period is reached.

3. The pixel unit according to claim 2, characterized in that: The auxiliary circuit includes a source follower transistor and a readout transistor; One end of the first photodiode is grounded, and the other end is connected to the drain end of the transfer transistor; One end of the second photodiode is grounded, and the other end is connected to the source end of the transfer transistor, the drain end of the reset transistor, and the gate end of the source follower transistor, and the connection point is used as the first output end; The source terminal of the reset transistor is connected to the power supply signal, the drain terminal is connected to the other end of the second photodiode, and the gate terminal receives a reset signal; The transfer transistor is connected to the first photodiode and the second photodiode through a source terminal and a drain terminal, and a gate terminal receives a transfer signal, and a connection path between the first photodiode and the second photodiode is turned on according to the control of the transfer signal; The source follower transistor has a source terminal connected to a power signal, a gate terminal connected to the first output terminal, and a drain terminal connected to a drain terminal of the readout transistor; The drain terminal of the readout transistor is connected to the drain terminal of the source follower transistor, the gate terminal receives a readout signal, and the source terminal serves as a second output terminal.

4. The pixel unit according to any one of claims 1 to 3, characterized in that: The pulse trigger unit includes: a first inverter, a second inverter, a pulse output transistor and a request output circuit; The first inverter and the second inverter are connected in series, the first signal is received through the input end of the first inverter, and the output end of the second inverter is connected to the request output circuit, the pulse latch unit and the drain end of the pulse output transistor; The request output circuit outputs the read request signal according to the control of the second inverter and the pulse latch circuit; The gate terminal of the pulse output transistor receives the enable signal, and the source terminal serves as a pulse output terminal to output the third signal obtained based on the first signal.

5. The pixel unit according to claim 4, characterized in that: The pulse trigger unit further includes: a pull-down transistor; The source terminal of the pull-down transistor is grounded, and is connected in parallel with the first inverter through the drain terminal and the gate terminal, the drain terminal receives the first signal, and the gate terminal is connected to the connection point of the first inverter and the second inverter; in response to the first inverter outputting a high level, the pull-down transistor is turned on to ground the first output terminal.

6. The pixel unit according to claim 4 or 5, characterized in that: The request output circuit includes: an enable transistor and a request transistor; The drain terminal of the enabling transistor is connected to the power signal, the source terminal is connected to the source terminal of the request transistor, and the gate terminal is connected to the pulse latch unit. In response to the fourth signal latched by the pulse latch unit being at a high level, the enabling transistor is turned on; The source terminal of the request transistor is connected to the source terminal of the enable transistor, the gate terminal is connected to the output terminal of the second inverter, and the drain terminal serves as a fourth output terminal; in response to the first signal being at a low level and the enable transistor being turned on, a read request signal is output through the fourth output terminal.

7. The pixel unit according to any one of claims 1 to 6, characterized in that: The pulse latch unit comprises: a trigger reset transistor, a trigger termination transistor and a latch circuit; The source terminal of the trigger reset transistor is connected to the power supply signal, the drain terminal is connected to the source terminal of the trigger termination transistor and the pulse trigger unit as a latch point, and the gate terminal receives the reset signal; The latch circuit is connected to the pulse trigger unit and the latch point, and is used to control the latch point to latch or write the fourth signal according to the reset signal and the enable signal; The source terminal of the trigger termination transistor is connected to the latch point, the drain terminal is connected to the pulse trigger unit, and the gate terminal receives the enable signal. In response to the trigger termination transistor receiving a enable signal within a photosensitive cycle, the trigger termination transistor is turned on, so that the fourth signal is pulled down to a low level, thereby disconnecting the path for the pulse trigger unit to send the read request signal.

8. The pixel unit according to claim 7, characterized in that: The latch circuit comprises: a first latch transistor and a second latch transistor; The gate terminal of the first latch transistor receives the reset signal, the source terminal is connected to the source terminal of the second latch transistor, and the drain terminal is connected to the latch point; The source terminal of the second latch transistor is connected to the source terminal of the first latch transistor, the gate terminal receives the enable signal, and the drain terminal is connected to the latch point; In response to the reset signal controlling the first latch transistor to be disconnected, the latch point is in a writable state, and the fourth signal is reset to a high level; in response to the reset signal controlling the first latch transistor to be turned on, and the enable signal controlling the second latch transistor to be turned on, the high-level fourth signal is latched in the latch point.

9. The pixel unit according to claim 8, characterized in that: The latch circuit further includes: a third inverter and a fourth inverter; The third inverter and the fourth inverter are connected in series to connect the latch point and the drain end of the first latch transistor. The connection point between the third inverter and the fourth inverter is also connected to the gate end of the enable transistor in the pulse trigger unit. In response to the fourth signal being at a high level, the enable transistor is controlled to be turned on.

10. A signal processing circuit, characterized in that: include: A pixel array consisting of n rows and m columns of sensor pixel units according to any one of claims 1 to 9, a row drive control module, a row arbitration module and a column readout module; n and m are integers greater than or equal to 1 respectively; The row drive control module is used to provide reset signals, transfer signals and readout signals to the sensor pixel units in the pixel array row by row; The pixel array is used to perform a reset according to the reset signal, send a read request signal to the row arbitration module in response to the first signal reaching a preset threshold value during a photosensitive period, and send a third signal to the column readout module under the control of the enable signal fed back by the row arbitration module; when the photosensitive period is reached, send a second signal to the column readout module under the control of the transfer signal and the readout signal; the third signal is determined based on the first signal; The row arbitration module is used to receive the read request signal sent by at least one row of the sensor pixel units in the pixel array, and feed back the permission signal to at least one row of the sensor pixel units according to the time sequence of receiving the read request signal; The column readout module is used to receive the third signal and the second signal sent by at least one column of the sensor pixel units.

11. The signal processing circuit according to claim 10, characterized in that: Also includes: Row address encoder and clock module; When the row arbitration module feeds back an enabling signal to a row of the sensor pixel units, the row address encoder encodes row information of the sensor pixel units receiving the enabling signal into a row address; The clock module is used to record the time information when the row address encoder generates the row address, and associate the time information with the row address.

12. The signal processing circuit according to claim 11, characterized in that: The column readout module comprises: m analog-to-digital converters, m column buffers and a column address encoder; each of the analog-to-digital converters corresponds to a column of the sensor pixel units, each of the column buffers corresponds to a column of the sensor pixel units; each of the analog-to-digital converters corresponds to one of the column buffers; The column buffer is used to store the third signal output by the sensor pixel unit of the corresponding column and transmit the third signal to the column address encoder; The column address encoder is used to receive the third signal output by the column buffer, encode the column information corresponding to the third signal into a column address, and associate the column address with the row address based on the time information to determine the sensor pixel unit corresponding to the third signal; The analog-to-digital converter is used to receive the second signal output by the sensor pixel unit of the corresponding column, perform a differential operation on two consecutively received second signals, and perform analog-to-digital conversion on the differential operation result to obtain a fifth signal.

13. The signal processing circuit according to any one of claims 10 to 12, characterized in that: Also includes: Conversion interface circuit; The conversion interface circuit is used to receive the signal output by the column readout module.

14. An electronic device, characterized in that: include: A processor, and a memory communicatively connected to the processor, further comprising the sensor pixel unit of claims 1-9 or the signal processing circuit of any one of claims 10-13; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory to control the sensor pixel unit or the signal processing circuit.

15. The device according to claim 14, characterized in that The electronic device is included in any of the following: image data acquisition equipment, audio / video player, navigation equipment, entertainment equipment, communication equipment, roadside traffic facilities, equipment in motor vehicles, industrial testing equipment, flight equipment, medical equipment, and security equipment.

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