Semiconductor structure, method of forming a semiconductor structure, and memory

Abstract

The embodiments of the present disclosure disclose a semiconductor structure, a forming method of the semiconductor structure and a memory. The semiconductor structure comprises a plurality of discrete active regions and a buried word line. The plurality of discrete active regions extend along a first direction and are arranged at intervals. The buried word line extends along a second direction and penetrates through a corresponding active region. An absolute value of an included angle between the first direction and the second direction is greater than 0° and less than 90°. The buried word line comprises a metal conductive layer, a semiconductor conductive layer and a work function adjustment layer. A work function of the work function adjustment layer is greater than a work function of the semiconductor conductive layer and less than a work function of the metal conductive layer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, a semiconductor structure, a forming method of the semiconductor structure and a memory. BACKGROUND

[0002] A dynamic random access memory (DRAM) is a semiconductor device commonly used in electronic devices such as computers, which includes an array of memory cells for storing data, and a peripheral circuit located in the periphery of the array of memory cells.

[0003] Each memory cell in the DRAM generally includes a transistor, a word line, a bit line and a capacitor. A word line voltage on the word line can control the opening and closing of the transistor, so that data information stored in the capacitor can be read through the bit line, or data information can be written into the capacitor. SUMMARY

[0004] Therefore, the present disclosure provides a semiconductor structure, a forming method of the semiconductor structure and a memory, which can improve the electrical performance of the semiconductor structure as a whole.

[0005] The technical solutions of the present disclosure are implemented as follows:

[0006] The present disclosure provides a semiconductor structure, which includes: a plurality of discrete active regions, extending along a first direction and arranged at intervals; a buried word line, extending along a second direction and penetrating through a corresponding active region; an absolute value of an included angle between the first direction and the second direction is greater than 0° and less than 90°; wherein the buried word line includes: a metal conductive layer, a semiconductor conductive layer and a work function adjustment layer; a work function of the work function adjustment layer is greater than a work function of the semiconductor conductive layer and less than a work function of the metal conductive layer.

[0007] In the above scheme, the buried word line is a plurality of lines and is arranged at intervals along a third direction, the third direction and the second direction are perpendicular to each other; a single active region is penetrated by two corresponding buried word lines, forming three source / drain regions and two first grooves; each first groove is located between two adjacent source / drain regions; each buried word line is arranged in a corresponding first groove.

[0008] In the above scheme, the metal conductive layer, the semiconductor conductive layer and the work function adjustment layer are stacked in a vertical direction in sequence.

[0009] In the above scheme, the thickness of the metal conductive layer is 70-80 nm; the thickness of the semiconductor conductive layer is 40-50 nm; and the thickness of the work function adjustment layer is 5-10 nm.

[0010] In the above solution, the width of the work function adjustment layer or the width of the semiconductor conductive layer is 2-4 nm larger than the width of the metal conductive layer.

[0011] In the above solution, the material of the metal conductive layer includes titanium nitride or tungsten; the material of the semiconductor conductive layer includes polysilicon; the material of the work function adjustment layer includes metal nitride, metal carbonitride, metal aluminum nitride, metal aluminum oxide and / or metal aluminum carbide; and the metal includes tungsten, titanium, cobalt or platinum.

[0012] In the above solution, the material of the work function adjustment layer includes tungsten nitride; the content of tungsten element is 40-60%, the content of silicon element is 25-35%, and the content of nitrogen element is 15-25%.

[0013] In the above solution, the semiconductor structure further includes a shallow trench isolation structure; the shallow trench isolation structure is arranged between adjacent active regions to separate the active regions; and the buried word line penetrates the shallow trench isolation structure.

[0014] The embodiments of the present disclosure further provide a forming method of a semiconductor structure, which includes: providing a substrate; the substrate includes: a plurality of discrete active regions; the plurality of active regions extend along a first direction and are arranged at intervals; forming a buried word line in the substrate; the buried word line extends along a second direction and penetrates the corresponding active region; the absolute value of the included angle between the first direction and the second direction is greater than 0° and less than 90°; wherein the buried word line includes: a metal conductive layer, a semiconductor conductive layer and a work function adjustment layer; the work function of the work function adjustment layer is greater than the work function of the semiconductor conductive layer and less than the work function of the metal conductive layer.

[0015] In the above solution, the substrate further includes a shallow trench isolation structure arranged between adjacent active regions; and the buried word line penetrates the corresponding shallow trench isolation structure.

[0016] In the above solution, forming the buried word line in the substrate includes: forming a patterned hard mask on the substrate; the pattern of the hard mask extends along a second direction and is arranged at intervals along a third direction; etching the substrate according to the hard mask to form a first groove in the active region and a second groove in the shallow trench isolation structure; the depth of the second groove is greater than the depth of the first groove; and the stacked metal conductive layer, semiconductor conductive layer and work function adjustment layer are sequentially formed in the first groove and the second groove, thereby forming a plurality of buried word lines.

[0017] In the above solution, before the metal conductive layer, the semiconductor conductive layer and the work function adjustment layer are sequentially formed in the first groove and the second groove, the method further comprises: forming a gate oxide layer on the inner wall of the first groove by an atomic layer deposition process or an in-situ vapor generation process.

[0018] In the above solution, the metal conductive layer, the semiconductor conductive layer and the work function adjustment layer are sequentially formed in the first groove and the second groove, comprising: depositing a good conductive material to fill the first groove and the second groove by a chemical vapor deposition process; etching back the good conductive material to form the metal conductive layer; depositing a polycrystalline material on the metal conductive layer by a diffusion process; etching back the polycrystalline material to form the semiconductor conductive layer; depositing a work function adjustment material on the semiconductor conductive layer by a chemical vapor deposition process; etching back the work function adjustment material to form the work function adjustment layer.

[0019] In the above solution, after the buried word line is formed in the substrate, the method further comprises: depositing a protection layer to cover the buried word line.

[0020] The present disclosure further provides a memory comprising the semiconductor structure as described in the above solution.

[0021] Therefore, the present disclosure provides a semiconductor structure, a forming method of the semiconductor structure and a memory. The semiconductor structure comprises: a plurality of discrete active regions and a buried word line. The plurality of discrete active regions extend along a first direction and are arranged at intervals. The buried word line extends along a second direction and penetrates through a corresponding active region. The absolute value of the included angle between the first direction and the second direction is greater than 0° and less than 90°. The buried word line comprises: a metal conductive layer, a semiconductor conductive layer and a work function adjustment layer. The work function of the work function adjustment layer is greater than the work function of the semiconductor conductive layer and less than the work function of the metal conductive layer. Since the work function of the work function adjustment layer is greater than the work function of the semiconductor conductive layer 302 and less than the work function of the metal conductive layer, the work function adjustment layer is used, so that the thickness of the semiconductor conductive layer does not need to be increased too much, and the saturation current IDR is improved. That is, while avoiding the risk of short circuit, the saturation current IDR is improved to meet the demand. At the same time, the buried word line comprises several parts with different work functions, and the difference in work function can reduce the leakage of the device. In summary, the electrical performance of the semiconductor structure as a whole is improved. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 Structure diagram of the semiconductor structure provided by the present disclosure Figure 1 ;

[0023] Figure 2 Structure diagram of a semiconductor structure provided by an embodiment of the present disclosure Figure 2 ;

[0024] Figure 3 Structure diagram of a semiconductor structure provided by an embodiment of the present disclosure Figure 3 ;

[0025] Figure 4 Structure diagram of a buried word line provided by an embodiment of the present disclosure

[0026] Figure 5 Structure diagram of a semiconductor structure provided by an embodiment of the present disclosure Figure 4 ;

[0027] Figure 6 Structure diagram of a semiconductor structure provided by an embodiment of the present disclosure Figure 5 ;

[0028] Figure 7 Flow diagram of a forming method of a semiconductor structure provided by an embodiment of the present disclosure Figure 1 ;

[0029] Figure 8 Flow diagram of a forming method of a semiconductor structure provided by an embodiment of the present disclosure Figure 2 ;

[0030] Figure 9 Flow diagram of a forming method of a semiconductor structure provided by an embodiment of the present disclosure Figure 3 ;

[0031] Figure 10 Structure diagram of a forming method of a semiconductor structure provided by an embodiment of the present disclosure Figure 1 ;

[0032] Figure 11 Structure diagram of a forming method of a semiconductor structure provided by an embodiment of the present disclosure Figure 2 ;

[0033] Figure 12 Structure diagram of a forming method of a semiconductor structure provided by an embodiment of the present disclosure Figure 3 ;

[0034] Figure 13 Structure diagram of a forming method of a semiconductor structure provided by an embodiment of the present disclosure Figure 4 ;

[0035] Figure 14 Structure diagram of a forming method of a semiconductor structure provided by an embodiment of the present disclosure Figure 5 ;

[0036] Figure 16Structure diagram of a semiconductor structure forming method provided by an embodiment of the present disclosure Figure 7 ;

[0037] Figure 17 Structure diagram of a semiconductor structure forming method provided by an embodiment of the present disclosure Figure 8 ;

[0038] Figure 18 Structure diagram of a semiconductor structure forming method provided by an embodiment of the present disclosure Figure 9 ;

[0039] Figure 19 Structure diagram of a semiconductor structure forming method provided by an embodiment of the present disclosure Figure 10 ;

[0040] Figure 20 Structure diagram of a semiconductor structure forming method provided by an embodiment of the present disclosure Figure 10 ;

[0041] Figure 21 Structure diagram of a semiconductor structure forming method provided by an embodiment of the present disclosure Figure 1 ;

[0042] Figure 2 Schematic diagram of a memory provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] In order to make the purposes, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further described in detail below in combination with the drawings and embodiments, and the described embodiments should not be regarded as limiting the present disclosure, and all other embodiments obtained by those skilled in the art without making creative efforts belong to the protection scope of the present disclosure.

[0044] In the following description, “some embodiments” are related to a subset of all possible embodiments, but it can be understood that “some embodiments” can be the same subset or different subset of all possible embodiments, and can be combined with each other without conflict.

[0045] If similar descriptions of “first / second” appear in the application file, the following description is added, in the following description, the terms “first / second / third” related only distinguish similar objects, and do not represent a specific order of the objects, and it can be understood that “first / second / third” can be interchanged with a specific order or sequence as allowed, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0046] In this document, when a layer / element is referred to as being "on" another layer / element, it can be directly on the other layer / element or intervening layers / elements can also be present. In addition, in one orientation a layer / element can be "on" another layer / element when it is oriented directly away from the other layer / element, even though there can be other layers / elements in between.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description herein is for describing the embodiments of the disclosure only and is not intended to be limiting of the disclosure.

[0048] With the continuous development of semiconductor process technology, the integration is continuously improved, and the size of the transistor is also getting smaller and smaller. Therefore, the channel electric field strength in the transistor is also continuously enhanced. In particular, when the process node reaches 10 nm and below, the energy density per unit area of the transistor is greatly increased, and the leakage problem will be more prominent, so that the power consumption will increase; at the same time, with the miniaturization of the size, the saturation current IDR also needs to be increased to improve the performance of the transistor.

[0049] Figure 1 And Figure 2 is an optional structure diagram of a semiconductor structure provided by the embodiments of the disclosure, wherein, Figure 1 is a top view, Figure 1 is a cross-sectional view along the cross-sectional line P1 in Figure 2 .

[0050] As shown in Figure 2 , the semiconductor structure includes a plurality of discrete active regions 20 and a buried word line 30. The plurality of discrete active regions 20 extend along a first direction A and are arranged at intervals. The buried word line 30 extends along a second direction B and penetrates through the corresponding active region 20. Wherein, the absolute value of the included angle between the first direction A and the second direction B is greater than 0° and less than 90°.

[0051] As shown in Figure 2 , the buried word line 30 includes a metal conductive layer 301, a semiconductor conductive layer 302, and a work function adjustment layer 303. Wherein, the work function of the work function adjustment layer 303 is greater than the work function of the semiconductor conductive layer 302 and less than the work function of the metal conductive layer 301.

[0052] In the embodiments of the disclosure, referring to Figure 2 , the substrate 10 includes a plurality of discrete active regions 20, and the material of the substrate 10 is a semiconductor, such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. In the embodiments of the disclosure, the substrate 10 and the active region 20 are described by using silicon (Si), which will not be described below.

[0053] In the embodiments of the present disclosure, referring to Figure 2 , the buried word line 30 penetrates the active region 20. In this way, the part of the active region 20 surrounding the buried word line 30 can form a channel of a transistor, and the part of the buried word line 30 surrounded can form a gate of the transistor. Compared with the conventional transistor structure, the transistor provided by the embodiments of the present disclosure has a longer channel, so that the negative effects caused by the short channel effect can be avoided. That is, the embodiments of the present disclosure can reduce the leakage current, improve the electron mobility, and control the thermal effect of the transistor, thereby improving the performance of the transistor.

[0054] In the embodiments of the present disclosure, referring to Figure 1 , the buried word line 30 includes a metal conductive layer 301, a semiconductor conductive layer 302, and a work function adjusting layer 303. Among them, the work function of the semiconductor conductive layer 302 is the smallest, the work function of the metal conductive layer 301 is the largest, and the work function of the work function adjusting layer 303 is between the above two.

[0055] It should be noted that the work function (work function) is also called work function, escape work, which refers to the minimum energy (usually in eV) that must be provided to make an electron immediately escape from the surface of the solid. Here, the word "immediately" means that the final electron position is far away from the surface on the atomic scale, but still close to the solid on the macroscopic scale. The work function is not an intrinsic property of the bulk phase of the material, but more accurately, it is a property of the surface of the material (such as the surface exposed crystal face condition and the degree of contamination). The work function is an important attribute of the metal. The size of the work function is usually about half of the ionization energy of the free atom of the metal. Generally, the lower the work function, the easier it is for electrons in the system to escape and participate in surface chemical reactions. Substances with low work function can easily emit photoelectrons under minimum excitation energy, so they can conduct electricity better.

[0056] In the embodiments of the present disclosure, continuing to refer to Figure 3 , on the basis of the metal conductive layer 301, the semiconductor conductive layer 302 is used, and the thickness of the semiconductor conductive layer 302 is appropriately increased, which can improve the saturation current IDR. However, as the thickness of the semiconductor conductive layer 302 increases, the overall thickness of the buried word line 30 increases, and the top of the buried word line 30 is closer to other conductive areas (for example, the bit line contact structure BLC located at the top of the active region 20), so that short risk is caused.

[0057] In the embodiments of the present disclosure, the work function adjustment layer 303 is used to adjust the overall work function of the embedded word line 30. Since the work function of the work function adjustment layer 303 is greater than the work function of the semiconductor conductive layer 302 and less than the work function of the metal conductive layer 301, the thickness of the semiconductor conductive layer 302 does not need to be increased too much, and the saturation current IDR can be improved, that is, the saturation current IDR is improved to meet the demand while avoiding the risk of short circuit. At the same time, the embedded word line 30 includes several parts with different work functions, and the difference in work function can reduce the leakage of the device. In summary, the embodiments of the present disclosure improve the overall electrical performance of the semiconductor structure.

[0058] In some embodiments of the present disclosure, referring to Figure 3 , the embedded word line 30 is a plurality of lines and is arranged at intervals along a third direction C, and the third direction C is perpendicular to the second direction B.

[0059] Referring to Figure 2 , the single active region 20 is penetrated by the corresponding two embedded word lines 30, forming three source / drain regions 201, 202 and 203, and two first grooves 21. Each first groove 21 is located between adjacent two source / drain regions, that is, there is a first groove 21 between the adjacent two source / drain regions 201 and 202, and there is a first groove 21 between the adjacent two source / drain regions 202 and 203. Each embedded word line 30 is arranged in the corresponding first groove 21.

[0060] In the embodiments of the present disclosure, continuing to refer to Figure 4 , the single active region 20 is penetrated by the corresponding two embedded word lines 30, which can form two transistor structures. Among them, the source / drain regions 201 and 202 can be used as the source and drain of the first transistor, the part of the word line 30 between the source / drain regions 201 and 202 can be used as the gate of the first transistor, and the active region 20 surrounding the part of the word line 30 can be used as the channel region of the first transistor, and further, the gate oxide layer 31 is formed between the channel region and the gate of the first transistor.

[0061] Correspondingly, the source / drain regions 202 and 203 can be used as the source and drain of the second transistor, the part of the word line 30 between the source / drain regions 202 and 203 can be used as the gate of the second transistor, and the active region 20 surrounding the part of the word line 30 can be used as the channel region of the second transistor, and further, the gate oxide layer 31 is formed between the channel region and the gate of the second transistor. In the first transistor and the second transistor, the thickness of the gate oxide layer 31 can be 5-6 nm.

[0062] It can be understood that the single active region 20 is penetrated by the corresponding two buried word lines 30, thereby forming two transistor structures. In this way, on the one hand, more than one transistor structure is formed in the single active region 20, thereby reducing the device size and improving the integration; on the other hand, the active region surrounding the buried word line serves as the channel region of the transistor, and the channel region of each transistor structure is longer, thereby avoiding the negative effects of the short channel effect and improving the performance of the transistor.

[0063] In some embodiments of the present disclosure, referring to Figure 4 The metal conductive layer 301, the semiconductor conductive layer 302, and the work function adjustment layer 303 can be stacked in the vertical direction Z in sequence.

[0064] In some embodiments of the present disclosure, referring to Figure 2 The thickness t1 of the metal conductive layer 301 can be 70-80 nm; the thickness t2 of the semiconductor conductive layer 302 can be 40-50 nm; and the thickness t3 of the work function adjustment layer 303 can be 5-10 nm.

[0065] In some embodiments of the present disclosure, referring to Figure 2 The width of the work function adjustment layer 303 or the width w2 of the semiconductor conductive layer 302 can be 2-4 nm larger than the width w1 of the metal conductive layer 301.

[0066] It can be understood that the metal conductive layer 301, the semiconductor conductive layer 302, and the work function adjustment layer 303 are stacked in the vertical direction Z in sequence, while the width and the thickness thereof are controlled; in this way, while ensuring a large saturation current IDR, the size of the buried word line 30 can be controlled within a certain range, thereby avoiding the risk of short circuit.

[0067] On the other hand, the work function of the semiconductor conductive layer 302 is the lowest, and it is stacked on the metal conductive layer 301 with the highest work function, thereby reducing the leakage current from the gate to the drain of the formed transistor and reducing the device power consumption.

[0068] In some embodiments of the present disclosure, referring to Figure 5 The material of the metal conductive layer 301 can include titanium nitride (TiN) or tungsten (W). The material of the semiconductor conductive layer 302 can include polysilicon (Poly-Si). The material of the work function adjustment layer 303 can include metal nitride, metal carbonitride, metal aluminum nitride, metal aluminum oxide, and / or metal aluminum carbide; wherein the metal includes tungsten (W), titanium (Ti), cobalt (Co), or platinum (Pt).

[0069] In some embodiments of the present disclosure, referring to Figure 6The material of the work function adjustment layer 303 includes tungsten silicon nitride (WSiN), wherein the content of tungsten (W) is 40-60%, the content of silicon (Si) is 25-35%, and the content of nitrogen (N) is 15-25%.

[0070] Figure 5 and Figure 6 is an optional structural schematic diagram of the semiconductor structure provided by the embodiments of the present disclosure, wherein Figure 5 is a top view, Figure 5 is a sectional view along the section line P2 in Figure 6 .

[0071] In combination with Figures 10 to 20 and Figure 7 , the semiconductor structure further includes a shallow trench isolation structure (STI) 40. The shallow trench isolation structure 40 is arranged between adjacent active regions 20 to separate the active regions 20. The buried word line 30 also penetrates the shallow trench isolation structure 40.

[0072] In the embodiments of the present disclosure, the shallow trench isolation structure 40 separates different active regions 20 to avoid short circuit between different active regions 20. In the process of arranging the buried word line 30, the shallow trench isolation structure 40 needs to be penetrated; however, the remaining shallow trench isolation structure 40 is still located between the buried word line 30 and the active region 20 to separate them, so as to avoid short circuit between the buried word line 30 and the active region 20.

[0073] It should be noted that, Figure 7 shows an intermediate structure in the forming method of the semiconductor structure provided by the embodiments of the present disclosure, which is used to describe and clearly show the steps of the forming method of the semiconductor structure.

[0074] Figure 10 is an optional flowchart of the forming method of the semiconductor structure provided by the embodiments of the present disclosure. As Figure 11 shown, the forming method of the semiconductor structure includes S101-S102, which will be described in combination with each step.

[0075] S101, providing a substrate; the substrate includes a plurality of discrete active regions; the plurality of active regions extend along a first direction and are arranged at intervals.

[0076] In the embodiments of the present disclosure, reference is made to Figure 10 and Figure 11 , wherein Figure 10 is a top view, Figure 1 is a sectional view along the section line P2 in Figure 19A cross-sectional view along the section line P3. The substrate 10 includes a plurality of discrete active regions 20, which are spaced apart and extend along a first direction A. The substrate 10 is made of a semiconductor material, such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. In the embodiments of the present disclosure, the substrate 10 and the active regions 20 are made of silicon (Si), which will not be described in detail hereinafter.

[0077] In S102, a buried word line is formed in the substrate. The buried word line extends along a second direction and penetrates through a corresponding active region. The absolute value of the included angle between the first direction and the second direction is greater than 0° and less than 90°. The buried word line includes a metal conductive layer, a semiconductor conductive layer, and a work function adjustment layer. The work function of the work function adjustment layer is greater than the work function of the semiconductor conductive layer and less than the work function of the metal conductive layer.

[0078] In the embodiments of the present disclosure, referring to Figure 19 , the buried word line 30 extends along the second direction B and penetrates through the corresponding active region 20. The absolute value of the included angle between the first direction A and the second direction B is greater than 0° and less than 90°.

[0079] In the embodiments of the present disclosure, referring to Figure 19 , the buried word line 30 includes a metal conductive layer 301, a semiconductor conductive layer 302, and a work function adjustment layer 303. The work function of the semiconductor conductive layer 302 is the smallest, the work function of the metal conductive layer 301 is the largest, and the work function of the work function adjustment layer 303 is between the two.

[0080] In the embodiments of the present disclosure, referring to Figure 1 , the buried word line 30 penetrates through the active region 20. In this way, the part of the active region 20 around the buried word line 30 can form a channel of a transistor, and the part of the buried word line 30 around the active region 20 can form a gate of the transistor. Compared with the conventional transistor structure, the transistor provided by the embodiments of the present disclosure has a longer channel, which can avoid the negative effects of the short channel effect. That is, the embodiments of the present disclosure can reduce the leakage current, improve the electron mobility, control the heat effect of the transistor, and thus improve the performance of the transistor.

[0081] Continuing to refer to Figure 19, the work function adjustment layer 303 is used to adjust the overall work function of the embedded word line 30, so that the thickness of the semiconductor conductive layer 302 does not need to be increased too much, and the saturation current IDR can be improved, that is, the saturation current IDR is improved to meet the demand while avoiding the risk of short circuit. At the same time, the embedded word line 30 includes several parts with different work functions, and the difference in work function can reduce the leakage of the device. In summary, the electrical performance of the overall semiconductor structure is improved.

[0082] In the embodiments of the present disclosure, in combination with Figure 19 and Figure 19 , the embedded word line 30 is in multiple and is arranged at intervals along the third direction C, and the third direction C is perpendicular to the second direction B. The single active area 20 is penetrated by the corresponding two embedded word lines 30, forming three source / drain areas 201, 202 and 203, and two first grooves 21. Each first groove 21 is located between adjacent two source / drain areas, that is, there is a first groove 21 between the adjacent two source / drain areas 201 and 202, and there is a first groove 21 between the adjacent two source / drain areas 202 and 203. Each embedded word line 30 is arranged in the corresponding first groove 21.

[0083] Continuing to refer to Figure 8 , in the embedded word line 30, the metal conductive layer 301, the semiconductor conductive layer 302 and the work function adjustment layer 303 can be stacked in the vertical direction Z in sequence.

[0084] It can be understood that the single active area 20 is penetrated by the corresponding two embedded word lines 30, and two transistor structures are further formed. In this way, on the one hand, more than one transistor structure is formed in the single active area 20, the device size is reduced, and the integration degree is improved; on the other hand, the active area surrounding the embedded word line is used as the channel region of the transistor, and the channel region of each transistor structure is longer, which can avoid the negative effects of the short channel effect and improve the performance of the transistor.

[0085] In the embodiments of the present disclosure, referring to Figure 12 , the substrate 10 further includes a shallow trench isolation structure 40 arranged between adjacent active areas 20. The embedded word line 30 penetrates the corresponding shallow trench isolation structure 40.

[0086] It can be understood that the embedded word line 30 needs to penetrate the shallow trench isolation structure 40 during arrangement; however, the remaining shallow trench isolation structure 40 after being penetrated is still located between the embedded word line 30 and the active area 20 to isolate the two, so that the short circuit between the embedded word line 30 and the active area 20 is avoided.

[0087] In some embodiments of the present disclosure, the saturation current IDR can be improved by Figure 1The steps S201 to S203 shown are used to form embedded letter lines, and will be explained in conjunction with each step.

[0088] S201, A patterned hard mask is formed on a substrate; the pattern of the hard mask extends along a second direction and is spaced apart along a third direction.

[0089] In this embodiment of the disclosure, reference is made to Figure 1 A patterned hard mask 50 can be formed on the substrate 10 (i.e., on top of the active region 20). The pattern of the hard mask 50 determines the shape of the subsequently formed embedded word lines; therefore, the pattern of the hard mask 50 can be referenced. Figure 12 The pattern of the embedded letter line 30 is understood, that is, the pattern of the hard mask 50 is along... Figure 12 The second direction B extends and is arranged at intervals along the third direction C.

[0090] S202. Based on the hard mask, the substrate is etched to form a first groove in the active region and a second groove in the shallow trench isolation structure; wherein the depth of the second groove is greater than the depth of the first groove.

[0091] In this embodiment of the disclosure, reference continues to be made to Figure 19 The substrate 10 can be etched using the hard mask 50 to form a first groove 21 in the active region 20 and a second groove 22 in the shallow trench isolation structure 40; the depth of the second groove 22 is greater than the depth of the first groove 21. A portion of the shallow trench isolation structure 40 is retained in the second groove 22. The remaining shallow trench isolation structure 40 can isolate the active region 20 and prevent short circuits.

[0092] S203. Stacked metal conductive layer, semiconductor conductive layer and work function adjustment layer are sequentially formed in the first groove and the second groove, thereby forming multiple embedded word lines.

[0093] In this embodiment of the disclosure, after forming Figure 8 Following the first groove 21 and the second groove 22 shown, a stacked metal conductive layer 301, a semiconductor conductive layer 302, and a work function adjustment layer 303 can be sequentially formed in the first groove 21 and the second groove 22, thereby forming Figure 13 The multiple embedded character lines 30 are shown.

[0094] In some embodiments of this disclosure, Figure 9 S2021 is also included between S202 and S203 shown, which will be explained in conjunction with each step.

[0095] S2021. A gate oxide layer is formed on the inner wall of the first groove by means of atomic layer deposition or in-situ vapor generation process.

[0096] In this embodiment of the disclosure, reference is made toFigure 8 After the first recess 21 and the second recess 22 are formed, a gate oxide layer 31 can be formed on the inner wall of the first recess 21 by an atomic layer deposition (ALD) process or an in-situ steam generation (ISSG) process. The thickness of the gate oxide layer 31 can be 5-6 nm.

[0097] In some embodiments of the present disclosure, the first recess and the second recess can be filled with a good-conductive material by Figure 13 The S301-S306 shown can be implemented by Figure 14 The S203 shown will be described in combination with each step.

[0098] S301, a good-conductive material is deposited to fill the first recess and the second recess by a chemical vapor deposition (CVD) process.

[0099] In the embodiments of the present disclosure, in combination with Figure 14 and Figure 15 The good-conductive material 304 can be deposited to fill the first recess 21 and the second recess 22 by a chemical vapor deposition (CVD) process. The good-conductive material 304 can include titanium nitride (TiN) or tungsten (W).

[0100] S302, the good-conductive material is etched back to form a metal-conductive layer.

[0101] In the embodiments of the present disclosure, in combination with Figure 16 and Figure 16 The good-conductive material 304 can be selectively etched back, and the etching back can be performed until a depth of 80-85 nm (i.e., the distance between the etching back position and the top of the active region 20 is 80-85 nm), so as to form a metal-conductive layer 301. The thickness of the metal-conductive layer 301 can be 70-80 nm.

[0102] S303, a polycrystalline material is deposited on the metal-conductive layer by a diffusion process.

[0103] In the embodiments of the present disclosure, in combination with Figure 17 After the metal-conductive layer 301 is formed, a polycrystalline material 305 can be deposited on the metal-conductive layer 301 by a diffusion (DIFF) process. The polycrystalline material 305 can be polysilicon (Poly-Si).

[0104] S304, the polycrystalline material is etched back to form a semiconductor-conductive layer.

[0105] In the embodiments of the present disclosure, in combination with Figure 18 and Figure 18The polycrystalline material 305 can be selectively etched back, and the etching back can be performed to a depth of 50-60 nm (i.e., the etching back end position is 50-60 nm away from the top of the active region 20), so as to form the semiconductor conductive layer 302. The thickness of the semiconductor conductive layer 302 can be 40-50 nm.

[0106] In S305, a work function adjustment material is deposited on the semiconductor conductive layer by a chemical vapor deposition process.

[0107] In the embodiments of the present disclosure, the work function adjustment material 306 can be a metal nitride, a metal carbonitride, a metal aluminide, a metal alumina, and / or a metal carbide. Figure 19 After the semiconductor conductive layer 302 is formed, the work function adjustment material 306 can be deposited on the semiconductor conductive layer 302 by a chemical vapor deposition (CVD) process. The work function adjustment material 306 can be a metal nitride, a metal carbonitride, a metal aluminide, a metal alumina, and / or a metal carbide, where the metal includes tungsten (W), titanium (Ti), cobalt (Co), or platinum (Pt).

[0108] In some embodiments of the present disclosure, the work function adjustment material 306 includes tungsten silicon nitride (WSiN), where the content of tungsten (W) is 40-60%, the content of silicon (Si) is 25-35%, and the content of nitrogen (N) is 15-25%.

[0109] In S306, the work function adjustment material is etched back to form a work function adjustment layer.

[0110] In the embodiments of the present disclosure, the work function adjustment material 306 can be a metal nitride, a metal carbonitride, a metal aluminide, a metal alumina, and / or a metal carbide. Figure 7 and Figure 20 The work function adjustment material 306 can be selectively etched back, and the etching back can be performed to a depth of 45-50 nm (i.e., the etching back end position is 45-50 nm away from the top of the active region 20), so as to form the work function adjustment layer 303, thereby forming the buried word line 30. The thickness of the work function adjustment layer 303 can be 5-10 nm.

[0111] It can be understood that the metal conductive layer 301, the semiconductor conductive layer 302, and the work function adjustment layer 303 are stacked in the vertical direction Z in sequence, while the width and thickness thereof are controlled. In this way, while the saturation current IDR is ensured to be large, the size of the buried word line 30 can be controlled within a certain range, thereby avoiding the risk of short circuit.

[0112] On the other hand, the work function of the semiconductor conductive layer 302 is the lowest, and the semiconductor conductive layer 302 is stacked on the metal conductive layer 301 with the highest work function. This can reduce the leakage current from the gate to the drain of the formed transistor, and reduce the power consumption of the device.

[0113] In some embodiments of the present disclosure, Figure 21The S102 shown further comprises S103, which will be described in combination with each step.

[0114] S103, covering the buried word line, and depositing to form a protective layer.

[0115] In the embodiments of the present disclosure, with reference to Figure 21 After the buried word line 30 is formed, the buried word line 30 can be covered, and a protective layer 60 is deposited to form. The protective layer 60 also covers the top of the active region 20. The material of the protective layer 60 can be silicon nitride (SiN).

[0116] It can be understood that the protective layer 60 can isolate the buried word line 30 and the active region 20 from the subsequent process and avoid short circuit.

[0117] The embodiments of the present disclosure also provide a memory, such as ​ As shown, the memory 80 comprises a semiconductor structure 70. The semiconductor structure 70 comprises the technical features of the foregoing embodiments.

[0118] In some embodiments of the present disclosure, with reference to ​ The memory 90 is a DRAM.

[0119] It should be noted that in this document, the terms "comprising", "containing" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or apparatus that includes a series of elements not only includes those elements, but also includes other elements not explicitly listed, or inherent to such a process, method, article or apparatus. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article or apparatus that includes the element.

[0120] The above-mentioned sequence numbers of the embodiments of the present disclosure are only for description, and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided by the present disclosure can be combined arbitrarily without conflict, to obtain new method embodiments. The features disclosed in the several product embodiments provided by the present disclosure can be combined arbitrarily without conflict, to obtain new product embodiments. The features disclosed in the several method or device embodiments provided by the present disclosure can be combined arbitrarily without conflict, to obtain new method or device embodiments.

[0121] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a plurality of discrete active regions extending along a first direction and arranged at intervals; a buried word line extending along a second direction and penetrating through a corresponding active region; an absolute value of an included angle between the first direction and the second direction is greater than 0° and less than 90°; wherein the buried word line comprises a metal conductive layer, a semiconductor conductive layer and a work function adjustment layer; a work function of the work function adjustment layer is greater than a work function of the semiconductor conductive layer and less than a work function of the metal conductive layer; the metal conductive layer, the semiconductor conductive layer and the work function adjustment layer are sequentially stacked along a vertical direction; a thickness of the metal conductive layer is 70-80 nm; a thickness of the semiconductor conductive layer is 40-50 nm; a thickness of the work function adjustment layer is 5-10 nm; a width of the work function adjustment layer or a width of the semiconductor conductive layer is greater than a width of the metal conductive layer by 2-4 nm.

2. The semiconductor structure of claim 1, wherein, The buried word line is a plurality of and arranged at intervals along a third direction; the third direction is perpendicular to the second direction; a single active region is penetrated through by two corresponding buried word lines, forming three source / drain regions and two first grooves; each first groove is located between two adjacent source / drain regions; each buried word line is arranged in a corresponding first groove.

3. The semiconductor structure of claim 1 or 2, wherein: a material of the metal conductive layer comprises titanium nitride or tungsten; a material of the semiconductor conductive layer comprises polysilicon; a material of the work function adjustment layer comprises metal nitride, metal carbonitride, metal aluminide, metal alumina and / or metal carbide; the metal comprises tungsten, titanium, cobalt or platinum.

4. The semiconductor structure of claim 1 or 2, wherein, The material of the work function adjustment layer comprises tungsten nitride; wherein a content of tungsten element is 40-60%, a content of silicon element is 25-35% and a content of nitrogen element is 15-25%.

5. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises a shallow trench isolation structure; the shallow trench isolation structure is arranged between adjacent active regions to separate the active regions; the buried word line further penetrates through the shallow trench isolation structure.

6. A method of forming a semiconductor structure, comprising: The method comprises: providing a substrate; the substrate comprises a plurality of discrete active regions; a plurality of active regions extend along a first direction and are arranged at intervals; Forming a buried word line in the substrate; the buried word line extends along a second direction and penetrates through a corresponding active region; an absolute value of an included angle between the first direction and the second direction is greater than 0° and less than 90°; wherein the buried word line comprises a metal conductive layer, a semiconductor conductive layer and a work function adjustment layer; a work function of the work function adjustment layer is greater than a work function of the semiconductor conductive layer and less than a work function of the metal conductive layer; the metal conductive layer, the semiconductor conductive layer and the work function adjustment layer are sequentially stacked along a vertical direction; a thickness of the metal conductive layer is 70-80 nm; a thickness of the semiconductor conductive layer is 40-50 nm; a thickness of the work function adjustment layer is 5-10 nm; a width of the work function adjustment layer or a width of the semiconductor conductive layer is 2-4 nm greater than a width of the metal conductive layer.

7. The method of forming a semiconductor structure of claim 6, wherein, The substrate further comprises a shallow trench isolation structure arranged between adjacent active regions; the buried word line penetrates through a corresponding shallow trench isolation structure.

8. The method of forming a semiconductor structure of claim 7, wherein, Forming the buried word line in the substrate comprises: forming a patterned hard mask on the substrate; a pattern of the hard mask extends along a second direction and is arranged at intervals along a third direction; performing etching on the substrate according to the hard mask to form a first recess in the active region and a second recess in the shallow trench isolation structure; wherein a depth of the second recess is greater than a depth of the first recess; forming the metal conductive layer, the semiconductor conductive layer and the work function adjustment layer in the first recess and the second recess in sequence to form a plurality of the buried word lines.

9. The method of forming a semiconductor structure of claim 8, wherein, Before forming the metal conductive layer, the semiconductor conductive layer and the work function adjustment layer in the first recess and the second recess in sequence, the method further comprises: forming a gate oxide layer on an inner wall of the first recess by an atomic layer deposition process or an in-situ vapor generation process.

10. The method of forming a semiconductor structure according to claim 8 or 9, wherein, Forming the metal conductive layer, the semiconductor conductive layer and the work function adjustment layer in the first recess and the second recess in sequence comprises: filling the first recess and the second recess with a good conductive material by a chemical vapor deposition process; etching back the good conductive material to form the metal conductive layer; depositing a polycrystalline material on the metal conductive layer by a diffusion process; etching back the polycrystalline material to form the semiconductor conductive layer; depositing a work function adjustment material on the semiconductor conductive layer by a chemical vapor deposition process; etching back the work function adjustment material to form the work function adjustment layer.

11. The method of forming a semiconductor structure of claim 6, wherein, After forming the buried word line in the substrate, the method further comprises: depositing a protection layer to cover the buried word line.

12. A memory, comprising: The memory comprises the semiconductor structure according to any one of claims 1-5.

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