Field effect transistor and preparation method thereof, memory and electronic equipment

Abstract

The invention provides a field effect transistor and a preparation method thereof, a memory and electronic equipment, and the field effect transistor comprises a grid electrode, an insulating layer, a conductive channel layer, a source electrode and a drain electrode, wherein the grid electrode, the insulating layer and the conductive channel layer are sequentially stacked, and the source electrode and the drain electrode are arranged on the surface of one side, deviating from the insulating layer, of the conductive channel layer at intervals. The conductive channel layer comprises a two-dimensional material and hydrazine hydrate dispersed in the two-dimensional material. According to the field effect transistor, the conductive channel layer comprises the two-dimensional material, and hydrazine hydrate enters the two-dimensional material, so that the number of charge capture centers is increased, electron movement is promoted, the electrical hysteresis characteristic is enhanced, an electrical hysteresis window is expanded, the storage performance of the field effect transistor is improved, and the preparation cost of the field effect transistor is reduced; and the data reliability and the anti-interference capability of the memory can be enhanced.

Description

Technical Field

[0001] The present application relates to the field of field effect transistors, and in particular to field effect transistors and methods for preparing the same, memory devices, and electronic devices. Background Art

[0002] With the increasing demand for miniaturization and high performance of electronic devices, the requirements for memory are getting higher and higher, and the performance of field effect transistors determines the storage performance of memory. At present, two-dimensional materials are expected to become the next generation of field effect transistor materials due to their unique bipolar characteristics. In the prior art, two-dimensional material field effect transistors have problems such as complex preparation process, high cost, small hysteresis window, poor storage performance, etc., which make it difficult to carry out large-scale production and application. Therefore, there is a need for a field effect transistor with good electrical hysteresis characteristics, excellent storage performance, simple preparation process and low cost. Summary of the invention

[0003] In view of this, the present application provides a field effect transistor and a preparation method thereof, a memory, and an electronic device. The structure of the field effect transistor includes a two-dimensional material modified with hydrazine hydrate, which reduces interface defects, increases the number of charge capture centers, strengthens electron flow, enhances electrical hysteresis characteristics, expands the electrical hysteresis window, and improves the storage performance of the field effect transistor, which is beneficial to improving the data reliability and anti-interference ability of the memory. At the same time, the preparation method of the field effect transistor is simple and the preparation cost is low, which is beneficial to the industrial production of field effect transistors.

[0004] In a first aspect, the present application provides a field effect transistor, comprising a gate, an insulating layer, and a conductive channel layer stacked in sequence, and a source and a drain arranged at intervals on a surface of the conductive channel layer facing away from the insulating layer, wherein the conductive channel layer comprises a two-dimensional material and hydrazine hydrate dispersed in the two-dimensional material.

[0005] Optionally, the hydrazine hydrate is uniformly dispersed in the conductive channel layer.

[0006] Optionally, part of the hydrazine hydrate exists in the internal structure of the two-dimensional material.

[0007] Optionally, the thickness of the conductive channel layer is 5nm-10nm.

[0008] Optionally, the field effect transistor further includes a hydrazine hydrate layer disposed on the conductive channel layer between the source and the drain.

[0009] Optionally, the two-dimensional material includes a transition metal chalcogenide.

[0010] Optionally, the chemical formula of the transition metal chalcogenide compound is MX2, wherein M represents a transition metal element, M includes one or more of Ti, V, Ta, Mo, W, Re, and X represents a chalcogen atom, X is S, Se or Te.

[0011] Optionally, the material of the gate includes one or more of elemental silicon, molybdenum silicide, tungsten silicide, aluminum, copper, chromium, nickel, molybdenum, tungsten, titanium, indium and tin, and the material of the insulating layer includes one or more of silicon dioxide, silicon nitride and aluminum oxide.

[0012] Optionally, the material of the source electrode includes one or more of iridium, rhodium, ruthenium, platinum, gold, silver, palladium, nickel and cobalt, and the material of the drain electrode includes one or more of iridium, rhodium, ruthenium, platinum, gold, silver, palladium, nickel and cobalt.

[0013] Optionally, the electrochemical hysteresis window of the field effect transistor is greater than or equal to 65V.

[0014] The conductive channel layer of the field effect transistor provided in the present application includes a two-dimensional material and hydrazine hydrate dispersed in the two-dimensional material, which increases the number of charge capture centers and the electron concentration, enhances the electrical hysteresis characteristics of the two-dimensional material, increases the electrical hysteresis window, and is beneficial to improving the storage performance of the field effect transistor.

[0015] In a second aspect, the present application provides a method for preparing a field effect transistor, comprising:

[0016] A gate is formed on one surface of the insulating layer, and a two-dimensional material layer, a source electrode and a drain electrode are formed on a surface of the insulating layer away from the gate electrode to obtain a field effect transistor to be modified;

[0017] The field effect transistor to be modified is placed in a hydrazine hydrate atmosphere for a first time to obtain the field effect transistor.

[0018] Optionally, the first time is 30s-15min.

[0019] The preparation method of the field effect transistor provided in the present application is novel, has low preparation cost and simple preparation process, and the prepared field effect transistor has excellent electrical hysteresis characteristics, a large electrical hysteresis window and good storage performance.

[0020] In a third aspect, the present application provides a memory, which includes the field effect transistor described in the first aspect or the field effect transistor manufactured by the preparation method described in the second aspect.

[0021] The memory provided by the present application has excellent comprehensive performance, excellent storage performance, and high stability and reliability.

[0022] In a fourth aspect, the present application provides an electronic device, comprising the memory described in the third aspect.

[0023] The electronic device provided by the present application has low production cost, fast operation speed and high stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for the embodiments or the prior art description. The specific embodiments described here are only used to explain the present invention and are not used to limit the present invention.

[0025] Figure 1 A schematic diagram of a cross-sectional structure of a field effect transistor provided in one embodiment of the present application;

[0026] Figure 2 A schematic diagram of a cross-sectional structure of a field effect transistor provided in another embodiment of the present application;

[0027] Figure 3 A schematic diagram of a preparation process of a field effect transistor provided in one embodiment of the present application;

[0028] Figure 4 An electron energy loss spectrum (EELS) diagram of the field effect transistor provided in Example 1 of the present application;

[0029] Figure 5 A Raman spectrum of a cross section of a conductive channel layer in a field effect transistor provided in Example 1 of the present application;

[0030] Figure 6 A cycle characteristic curve diagram of the field effect transistor provided in Example 1 of the present application;

[0031] Figure 7 1 is the transfer characteristic curve of the field effect transistor of Examples 1-4 and Comparative Example 1 of the present application.

[0032] Description of Figure Numbers

[0033] 100 - field effect transistor; 10 - gate; 20 - insulating layer; 30 - conductive channel layer; 41 - source; 42 - drain; 50 - hydrazine hydrate layer. DETAILED DESCRIPTION

[0034] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0035] As the demand for miniaturization and high performance of electronic devices continues to increase, the performance requirements for field effect transistors are getting higher and higher. Field effect transistors are a semiconductor device that uses the electric field effect of the control input loop to control the output loop current. Because two-dimensional materials have bipolarity, they can simultaneously realize the transmission of electrons and holes, and are expected to become the next generation of field effect transistor materials. However, in the prior art, two-dimensional materials cannot be used to obtain pure p-type or n-type field effect transistors through simple operations such as ion implantation and doping to achieve storage functions. Usually, two-dimensional materials need to be combined with floating gate storage structures or ferroelectric storage structures to obtain field effect transistors with excellent storage performance. Among them, floating gate memory constructs a floating gate structure on two-dimensional materials and uses the tunneling effect to realize the storage and release of charges, but it requires a precise multi-layer structure, including a floating gate, a charge tunnel layer, and a control gate, and the resulting memory structure is complex, the preparation process steps are numerous, and the process cost and time cost are greatly increased. Ferroelectric memory relies on the spontaneous polarization characteristics of special ferroelectric materials to store and erase data under the action of an external electric field. When combined with two-dimensional materials, it can also obtain a memory with a large electrical hysteresis loop. However, ferroelectric memory may degrade after high temperature or long-term use, and the preparation and integration process of the memory is strict, which further increases the manufacturing difficulty and cost. Therefore, a field effect transistor with low preparation cost, simple process, large electrical hysteresis window and excellent storage performance is needed.

[0036] See also Figure 1 , Figure 1A schematic diagram of the cross-sectional structure of a field effect transistor provided in one embodiment of the present application, wherein the field effect transistor 100 includes a gate 10, an insulating layer 20, and a conductive channel layer 30 stacked in sequence, and a source 41 and a drain 42 spaced apart on a surface of the conductive channel layer 30 facing away from the insulating layer 20, wherein the conductive channel layer 30 includes a two-dimensional material and hydrazine hydrate dispersed in the two-dimensional material. In the present application, by applying voltage on the gate, source and drain, the transmission of carriers in the conductive channel layer is realized, and the electrons are prompted to move in a directional manner to realize data storage and erasure; in addition, hydrazine hydrate is dispersed in the two-dimensional material layer, and hydrazine hydrate molecules are introduced into the structure of the two-dimensional material, which reduces interface defects, so that a large number of charge capture centers are formed in the two-dimensional material, which can increase the number and efficiency of the captured and released charges, enhance the electrical hysteresis characteristics of the field effect transistor, and achieve a larger electrical hysteresis window, achieve excellent data access and reading performance, and enhance the memory anti-interference ability and data reliability; at the same time, hydrazine hydrate is a strong polar compound, and under the premise of not reacting with the two-dimensional material, the bipolarity of the two-dimensional material can be converted into electronic (n-type) doping induction, and the electron concentration of the conductive channel layer is increased, so that the current is increased, the device switching ratio is increased, and the control ability of the gate voltage to the channel is improved, which is conducive to improving the storage performance of the field effect transistor. In addition, the structure of the field effect transistor in the present application is simple, no special materials are required, the preparation cost of the memory is reduced, and it is conducive to the wide application of the memory. The field effect transistor provided in the present application has a large electrical hysteresis window and high data storage and erasure efficiency, which is beneficial to improving the storage performance and data stability of the memory.

[0037] In one embodiment of the present application, the conductive channel layer 30 includes a two-dimensional material and hydrazine hydrate dispersed in the two-dimensional material. The hydrazine hydrate fully enters the two-dimensional material, causing the crystal structure of the two-dimensional material to change, resulting in a longer bond length, thereby introducing a large number of charge capture centers, increasing the number of charges captured and released in the conductive channel layer, and promoting the movement of electrons in the conductive channel layer, which is beneficial to improving the storage performance of the storage device; the strong polarity of hydrazine hydrate causes the bipolar transport characteristics of the two-dimensional material, which are mainly p-type, to gradually transform into n-type, thereby increasing the electron concentration in the conductive channel layer, which is beneficial to improving the electrical hysteresis window of the field effect transistor. Specifically, the two-dimensional material may include, but is not limited to, a transition metal chalcogenide. Exemplarily, the chemical formula of the transition metal chalcogenide is MX2, wherein M represents a transition metal element, M may include, but is not limited to, one or more of Ti, V, Ta, Mo, W, and Re, and X represents a chalcogen atom, which may be, but is not limited to, S, Se, or Te, etc. In one embodiment of the present application, the conductive channel layer includes MoTe2, and the bond length of the Mo-Te bond of MoTe2 after hydrazine hydrate enters the two-dimensional material is Increase to The bond length of Te-Te is given by Increase to

[0038] In one embodiment of the present application, the thickness of the conductive channel layer 30 is 5nm-10nm. The appropriate thickness of the conductive channel layer 30 can increase the electrical hysteresis window of the field effect transistor and improve the storage and reading efficiency of data. Specifically, the thickness of the conductive channel layer 30 can be, but is not limited to, 5nm, 6nm, 7nm, 8nm, 9nm or 10nm. In one embodiment of the present application, the thickness of the conductive channel layer 30 can be 5nm-8nm. In another embodiment of the present application, the thickness of the conductive channel layer 30 can be 7nm-10nm.

[0039] See also Figure 2 The conductive channel layer 30 between the source 41 and the drain 42 also includes a hydrazine hydrate layer 50. The hydrazine hydrate layer 50 can increase the number of charge capture centers in the conductive channel layer, achieve stable charge capture and release, and help improve the electrical hysteresis window of the field effect transistor.

[0040] In one embodiment of the present application, the field effect transistor includes a source 41 and a drain 42 disposed on the surface of the conductive channel layer 30 on the side away from the insulating layer 20, the source 41 controls the inflow of carriers, and the carriers are discharged from the drain 42 to realize the storage function of the field effect transistor. Specifically, the material of the source 41 may include, but is not limited to, one or more of iridium, rhodium, ruthenium, platinum, gold, silver, palladium, nickel and cobalt, the material of the drain 42 may include, but is not limited to, one or more of iridium, rhodium, ruthenium, platinum, gold, silver, palladium, nickel and cobalt, the thickness of the source 41 may be, but is not limited to, 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm or 50nm, etc., the thickness of the drain 42 may be, but is not limited to, 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm or 50nm, etc. In one embodiment of the present application, a palladium metal with a thickness of 10 nm can be used as the source 41. In another embodiment of the present application, a metal with a thickness of 50 nm can be used as the drain 42. In some embodiments, a voltage (drain voltage V d , source voltage V s ), the source voltage is grounded and the drain is used as an external voltage.

[0041] In one embodiment of the present application, the source 41 and / or the drain 42 may be composed of a metal conductive layer and a metal compound layer, wherein the metal conductive layer is connected to an external voltage, and the metal compound layer is located between the conductive channel layer and the metal conductive layer, which is beneficial to increase the electron flow rate in the conductive channel layer and reduce the preparation cost of the field effect transistor. Specifically, the material of the metal conductive layer may include but is not limited to one or more of iridium, rhodium, ruthenium, platinum, gold, silver, palladium, nickel and cobalt; the material of the metal compound layer may include but is not limited to one or more of metal oxides, metal nitrides, and alloys.

[0042] In one embodiment of the present application, the source 41 and / or the drain 42 may be composed of a metal conductive layer and other conductive material layers, wherein the metal conductive layer is connected to an external voltage, and the other conductive material layers are located between the conductive channel layer and the metal conductive layer, which is beneficial to increase the electron flow rate in the conductive channel layer and reduce the preparation cost of the field effect transistor. Specifically, the material of the metal conductive layer may include but is not limited to one or more of iridium, rhodium, ruthenium, platinum, gold, silver, palladium, nickel and cobalt; the other conductive material layer includes at least one dopant doped with at least one organic material, wherein the organic material may include but is not limited to one or more of polythiophene, polypyrrole, polyaniline, polyacetylene, polyphenylene, polyfuran and polyazulene, and the dopant may include but is not limited to one or more of iodine, perchloric acid, hydrochloric acid, sulfuric acid, nitric acid, phosphoric acid, tetrafluoroboric acid and hexafluorophosphoric acid.

[0043] In one embodiment of the present application, the gate 10 can be subjected to an external voltage so that carriers can enter the conductive channel layer 30 to achieve data reading, writing and erasing. The insulating layer 20 can prevent the interface reaction and mutual diffusion between the gate 10 and the conductive channel layer 30, which is beneficial to improving the structural stability of the field effect transistor. Specifically, the material of the gate 10 may include but is not limited to one or more of elemental silicon, molybdenum silicide, tungsten silicide, aluminum, copper, chromium, nickel, molybdenum, tungsten, titanium, indium and tin, and the material of the insulating layer 20 may include but is not limited to one or more of silicon dioxide, silicon nitride and aluminum oxide. In one embodiment of the present application, the insulating layer 20 may be silicon dioxide, the gate 10 may be silicon, and the insulating layer and the gate constitute the substrate of the field effect transistor. In some embodiments, a voltage is applied to the gate 10 (gate voltage V g ).

[0044] In one embodiment of the present application, the thickness of the insulating layer 20 is 10nm-350nm. The appropriate thickness of the insulating layer 20 can improve the structural stability of the field effect transistor. Specifically, the thickness of the insulating layer 20 can be, but is not limited to, 10nm, 50nm, 100nm, 150nm, 200nm, 250nm, 300nm or 350nm. In one embodiment of the present application, the thickness of the insulating layer 20 can be 10nm-250nm. In another embodiment of the present application, the thickness of the insulating layer 20 can be 200nm-350nm.

[0045] In one embodiment of the present application, the electrical hysteresis window of the field effect transistor is greater than or equal to 65V. The electrical hysteresis window refers to the voltage difference between the field effect transistor in the programming and erasing operations. The larger the electrical hysteresis window, the better it is for improving the storage and reading capabilities of the field effect transistor, improving the access and reading efficiency, and enhancing the anti-interference ability and data reliability of the field effect transistor. Specifically, the electrical hysteresis window of the field effect transistor may be, but is not limited to, greater than or equal to 65V, greater than or equal to 66V, greater than or equal to 68V, greater than or equal to 70V, greater than or equal to 72V, or greater than or equal to 75V, etc. In one embodiment of the present application, the electrical hysteresis window of the field effect transistor may be greater than or equal to 68V. In some embodiments, the field effect transistor may be tested for a transfer characteristic curve, and the read, write, and erase voltages may be selected according to the transfer curve, and the erase, write, read, and write may be tested as a cycle to obtain the cycle characteristics, thereby obtaining the electrical hysteresis window range of the field effect transistor.

[0046] The present application provides a method for preparing a field effect transistor, comprising:

[0047] S101: forming a gate on one surface of the insulating layer, and forming a two-dimensional material layer, a source electrode and a drain electrode on the surface of the insulating layer away from the gate electrode, to obtain a field effect transistor to be modified;

[0048] S102: Place the field effect transistor to be modified in a hydrazine hydrate atmosphere, and keep obtaining the field effect transistor for the first time. The preparation method of the field effect transistor provided in the present application is novel, the preparation process is simple, the preparation cost is low, the prepared field effect transistor has good electrical hysteresis characteristics, a large programming and erasure window, and improves the data storage and reading efficiency of the field effect transistor. In the present application, hydrazine hydrate molecules are introduced into the two-dimensional material, so that a large number of charge capture centers are formed in the two-dimensional material, which can increase the number of charges captured and released, enhance the electrical hysteresis characteristics of the field effect transistor, achieve a larger electrical hysteresis window, achieve excellent data access and reading performance, and enhance the memory's anti-interference ability and data reliability. The cost of hydrazine hydrate is low and relatively cheap, which reduces the preparation cost of field effect transistors and improves the economy and feasibility of memory.

[0049] See also Figure 3 , Figure 3 A schematic diagram of the preparation process of a field effect transistor provided in one embodiment of the present application, wherein a two-dimensional material is disposed on the surface of an insulating layer to form a two-dimensional material layer, which is conducive to realizing charge storage and improving the structural stability of the field effect transistor. In one embodiment of the present application, an optical microscope and a transfer table are used to transfer a mechanically exfoliated two-dimensional material (MoTe2) nanosheet to the surface of a cleaned silicon insulating layer to form a two-dimensional material layer.

[0050] In one embodiment of the present application, after the two-dimensional material is disposed on the surface of the insulating layer, a source electrode and a drain electrode are disposed on the surface of the two-dimensional material layer. In one embodiment of the present application, a photoresist is disposed on the surface of the two-dimensional material layer, and after electron beam lithography and cleaning, a bare area and a photoresist-covered area are formed on the surface of the two-dimensional material layer, and after electron beam evaporation, a source electrode and a drain electrode are disposed on the surface of the bare area, and the photoresist covering the remaining area is removed to obtain a field effect transistor to be modified.

[0051] In the present application, a field effect transistor to be modified is placed in hydrazine hydrate vapor for a first time, during which the hydrazine hydrate vapor modifies the field effect transistor to be modified to form a conductive channel layer, hydrazine hydrate is dispersed in the two-dimensional material, and a hydrazine hydrate layer is formed on the surface of the two-dimensional material layer between the source and the drain, thereby obtaining a field effect transistor.

[0052] In one embodiment of the present application, the first time is 30s-15min, which is conducive to inserting hydrazine hydrate into the two-dimensional material, modifying the conductive channel layer, and improving the storage performance of the field effect transistor. Specifically, the first time of the modification treatment can be but is not limited to 30s, 1min, 2min, 5min, 8min, 10min, 12min, 14min or 15min, etc. In one embodiment of the present application, 0.5ml of hydrazine hydrate is placed in a flask, heated to 70°C, the field effect transistor to be modified is hung in the flask through a bracket, and modified with hydrazine hydrate vapor for 10min to obtain a field effect transistor.

[0053] The present application also provides a memory, the memory comprising the field effect transistor described in any of the above embodiments or the field effect transistor prepared by the preparation method described in any of the above embodiments. In the present application, after the field effect transistor is modified with hydrazine hydrate, a hydrazine hydrate modification layer is formed on the surface of the conductive channel layer, and hydrazine hydrate is introduced into the two-dimensional material, thereby improving the storage performance of the field effect transistor, thereby improving the programming and erasing window of the memory, which is beneficial to improving the data storage and reading efficiency of the memory device, and is beneficial to improving the computing speed of the electronic device.

[0054] In one embodiment of the present application, applying voltage to the metal electrode and the insulating layer in the field effect transistor can cause the electrons in the conductive channel layer to move in a directional manner, thereby having data storage and erasing functions, and obtaining a memory with excellent storage performance. In one embodiment of the present application, a field effect transistor can be a storage device.

[0055] In one embodiment of the present application, the memory can be divided into a random access memory and a read-only memory according to the working mode. A random access memory is a memory that reads and writes data at high speed and randomly at the same speed for any address (the write speed and the read speed may be different); the content in the read-only memory can only be read randomly but not written. Once the information is written into the memory, it is fixed and unchanged, and the content will not be lost even if the power is turned off. The field effect transistor provided in the present application can be used in the preparation of the above-mentioned memory, and the storage capacity of the above-mentioned memory can be increased.

[0056] The present application also provides an electronic device, including the memory described in any of the above embodiments. The electronic device may be, for example, a mobile phone, a tablet computer, a laptop computer, a wearable device (watch, bracelet), a digital camera, etc. The memory provided in the present application has low preparation cost and good storage performance, which is conducive to improving the operating speed of the electronic device and is conducive to the wide application of the electronic device, for example: the electronic device can be used in data centers, network communications, consumer electronics, automotive electronics, industrial electronics and other fields. In one embodiment of the present application, the electronic device may be a computer, and the computer includes three core hardware: a central processing unit, a memory and a hard disk, wherein the central processing unit is responsible for calculation, the hard disk is responsible for storage, and the memory is a bridge between the central processing unit and the hard disk, which is used to temporarily store the calculation data in the central processing unit. The memory and the hard disk include the memory shown in any of the above embodiments, which can realize fast reading and writing of data and long-term preservation, and improve the operation speed of the computer.

[0057] The effect of the technical solution of the present application is further illustrated below through specific examples.

[0058] Example 1

[0059] The bulk two-dimensional material (5nm MoTe2 nanosheet) was transferred to a clean insulating layer (300nm SiO2) by mechanical stripping using blue tape, the gate (Si) was set on the side away from the two-dimensional material layer, photoresist was coated on the surface of the two-dimensional material layer, electron beam lithography and electron beam evaporation were performed to obtain the source (palladium (Pd, 10nm)) and drain (gold (Au, 50nm)), the photoresist was removed, and the field effect transistor to be modified was obtained;

[0060] Add 0.5 mL of hydrazine hydrate into a 250 mL flask, heat the flask to 70°C to obtain hydrazine hydrate vapor, vertically place the field effect transistor to be modified at the mouth of the flask, and keep it under hydrazine hydrate gas for the first time (10 minutes) by the steam method to obtain a field effect transistor.

[0061] Figure 4 This is an electron energy loss spectrum (EELS) diagram of the field effect transistor provided in Example 1 of the present application. Figure 4 It can be seen that the N element in the hydrazine hydrate molecule is distributed in the two-dimensional material of the conductive channel layer, that is, the hydrazine hydrate molecule can enter the two-dimensional material. Figure 5 This is the Raman spectrum of the field effect transistor provided in Example 1 of the present application. Figure 5 It can be seen that the two-dimensional material MoTe2 does not change before and after hydrazine hydrate modification, and there is no obvious difference in the Raman spectrum peak position of the two-dimensional material before and after modification, which proves that the two-dimensional material MoTe2 has not undergone substantial changes and hydrazine hydrate does not react with the two-dimensional material. Figure 6 The cyclic characteristic curves of the field effect transistor provided in Example 1 of the present application are as follows: (a) is a linear graph of the transfer characteristic curve of the field effect transistor; (b) is a logarithmic graph of the transfer characteristic curve of the field effect transistor; (c) is a cyclic current change graph of a single field effect transistor; (d) is a cyclic current change graph of multiple field effect transistors; (e) is a schematic diagram of the data retention capability of the field effect transistor when erased; (f) is a schematic diagram of the data retention capability of the field effect transistor when written, wherein (a) (b) shows that the hysteresis window of the field effect transistor is 65V; (c) (d) describe the erase and write tests under a single cycle and 256 cycles, and the data show that the device resistance switching ratio is 10 3 , the data remains stable within 256 cycles. (e)(f) describes the data retention capability of the field effect transistor, the data retention time can reach 60 minutes.

[0062] Example 2

[0063] The difference from Example 1 is that the first time is 5 minutes.

[0064] Example 3

[0065] The difference from Example 1 is that the first time is 2 minutes.

[0066] Example 4

[0067] The difference from Example 1 is that the first time is 0.5 min.

[0068] Comparative Example 1

[0069] The difference from Example 1 is that no hydrazine hydrate modification is performed.

[0070] Performance Testing

[0071] The field effect transistors prepared in the above-mentioned embodiments 1-4 and comparative example 1 were subjected to an electrical hysteresis characteristic curve test. The test process was as follows: the read (Vg=0V), write (Vg=60V), and erase (Vg=-60V) voltages were selected according to the transfer curve, and the erase, write, read, and write were used as a cycle test to obtain the cycle characteristics. The results are shown in FIG. Figure 7 shown. Figure 7 1 is the transfer characteristic curve of the field effect transistor of Examples 1-4 and Comparative Example 1 of the present application.

[0072] The field effect transistors prepared in the above-mentioned Example 1 and Comparative Example 1 were subjected to synchrotron radiation X-ray absorption fine structure (XAFS), and the results are shown in Table 1.

[0073] Table 1 Performance test results

[0074]

[0075] According to Examples 1-4 and Comparative Example 1, it can be seen that in the field effect transistor modified with hydrazine hydrate, hydrazine hydrate enters the two-dimensional material, changes the bond length of the two-dimensional material, increases the number of charge capture centers, significantly increases the hysteresis window, and increases the N-terminal current (Vg = 60V) by 6x10 -6 A increases to 1.5x10 -5 A, resulting in an increase in the electron concentration in the transistor, and a larger hysteresis window is beneficial to improving the storage and reading capabilities of the device. According to Examples 1-4, it can be seen that as the hydrazine hydrate modification time increases, the field effect transistor gradually changes from a p-type bipolar transport characteristic to an n-type, and the N-terminal current gradually increases, indicating that the hydrazine molecule can induce n-type doping in the transistor to a certain extent, resulting in an increasing trend in the hysteresis window of the field effect transistor, which is beneficial to improving the storage performance of the field effect transistor.

[0076] The above is a preferred embodiment of the present application, but it should not be understood as limiting the scope of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application, and these improvements and modifications are also considered to be within the scope of protection of the present application.

Claims

1. A field effect transistor, characterized in that: The field effect transistor comprises a gate, an insulating layer, a conductive channel layer which are stacked in sequence, and a source electrode and a drain electrode which are spaced apart on a surface of the conductive channel layer which is away from the insulating layer. The conductive channel layer comprises a two-dimensional material and hydrazine hydrate dispersed in the two-dimensional material.

2. The field effect transistor according to claim 1, characterized in that The hydrazine hydrate is uniformly dispersed in the conductive channel layer; part of the hydrazine hydrate exists in the internal structure of the two-dimensional material.

3. The field effect transistor according to claim 1, characterized in that The thickness of the conductive channel layer is 5nm-10nm.

4. The field effect transistor according to claim 1, characterized in that The field effect transistor further includes a hydrazine hydrate layer disposed on the conductive channel layer between the source electrode and the drain electrode.

5. The field effect transistor according to claim 1, wherein: The two-dimensional material includes a transition metal chalcogenide; The chemical formula of the transition metal chalcogenide is MX2, wherein M represents a transition metal element, M includes one or more of Ti, V, Ta, Mo, W, and Re, and X represents a chalcogen atom, X is S, Se, or Te; The material of the gate includes one or more of elemental silicon, molybdenum silicide, tungsten silicide, aluminum, copper, chromium, nickel, molybdenum, tungsten, titanium, indium and tin, and the material of the insulating layer includes one or more of silicon dioxide, silicon nitride and aluminum oxide; The material of the source electrode includes one or more of iridium, rhodium, ruthenium, platinum, gold, silver, palladium, nickel and cobalt, and the material of the drain electrode includes one or more of iridium, rhodium, ruthenium, platinum, gold, silver, palladium, nickel and cobalt.

6. The field effect transistor according to claim 1, wherein: The electrical hysteresis window of the field effect transistor is greater than or equal to 65V.

7. A method for preparing a field effect transistor according to any one of claims 1 to 6, characterized in that: include: A gate is formed on one surface of the insulating layer, and a two-dimensional material layer, a source electrode and a drain electrode are formed on a surface of the insulating layer away from the gate electrode to obtain a field effect transistor to be modified; The field effect transistor to be modified is placed in a hydrazine hydrate atmosphere for a first time to obtain the field effect transistor.

8. The preparation method according to claim 7, characterized in that: The first time is 30s-15min.

9. A memory, characterized in that: The memory comprises the field effect transistor according to any one of claims 1 to 6 or the field effect transistor manufactured by the manufacturing method according to any one of claims 7 to 8.

10. An electronic device, characterized in that: The electronic device comprises the memory according to claim 9.

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