Method of fabricating a semiconductor structure, semiconductor structure, device and apparatus

Abstract

The application provides a preparation method of a semiconductor structure, a semiconductor structure, a device and equipment, the semiconductor structure comprising a first semiconductor structure and a second semiconductor structure stacked in a first direction, the first semiconductor structure being a complementary metal-oxide-semiconductor (CMOS), and the second semiconductor structure being a CMOS image sensor; the method comprising: forming an active structure on a substrate; the active structure comprising a first active structure and a second active structure; forming the first semiconductor structure based on the first active structure; the first semiconductor structure comprising a first transistor of a first polarity and a second transistor of a second polarity; developing and thinning the substrate until the second active structure is exposed; forming the second semiconductor structure based on the second active structure; the second semiconductor structure comprising a third transistor of the first polarity and an image sensor unit; the third transistor and the image sensor unit being arranged side by side in a second direction.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor, and in particular to a preparation method of a semiconductor structure, the semiconductor structure, a device and equipment. BACKGROUND

[0002] CMOS image sensors, which are a kind of optical sensors, have the function of converting optical signals into electrical signals and converting them into digital signals through readout circuits, and are widely used in the field of vision and are the core components of camera modules. CMOS image sensors are often used in high-end mobile phone cameras, digital cameras and digital single-lens reflex cameras and other electronic devices.

[0003] At present, the integration of CMOS image sensors and logic circuits has the problem of poor process compatibility. SUMMARY

[0004] The present application provides a preparation method of a semiconductor structure, the semiconductor structure, a device and equipment to solve the process compatibility problem of complementary metal oxide semiconductor (CMOS) logic units and CMOS image sensors.

[0005] In a first aspect, the embodiments of the present application provide a preparation method of a semiconductor structure, the semiconductor structure including a first semiconductor structure and a second semiconductor structure stacked in a first direction, the first semiconductor structure being a CMOS, and the second semiconductor structure being a CMOS image sensor; the method includes: forming an active structure on a substrate; the active structure includes a first active structure and a second active structure; based on the first active structure, forming the first semiconductor structure; the first semiconductor structure includes a first transistor of a first polarity and a second transistor of a second polarity; the first transistor and the second transistor are arranged side by side in a second direction; the second direction is perpendicular to the first direction; the substrate is developed and thinned until the second active structure is exposed; based on the second active structure, forming the second semiconductor structure; the second semiconductor structure includes a third transistor of the first polarity and an image sensor unit; the third transistor and the image sensor unit are arranged side by side in the second direction.

[0006] In some possible implementations, the second active structure is divided into a first part and a second part in the second direction; based on the second active structure, forming the second semiconductor structure includes: based on the first part of the second active structure, forming a third source-drain structure and a third gate structure in the third transistor; based on the second part of the second active structure, forming a photodiode in the image sensor unit; forming a second metal interconnection layer in the second semiconductor structure on the third gate structure and the photodiode; disposing an optical element in the second metal interconnection layer; the optical element is connected with the photodiode.

[0007] In some possible implementation manners, forming the photodiode in the image sensor unit based on the second part of the second active structure comprises: forming a first mask plate on the second part of the second active structure; and performing ion implantation on the second part of the second active structure under the mask effect of the first mask plate to form the photodiode.

[0008] In some possible implementation manners, the optical element comprises a filter and a microlens; and the optical element is arranged in the second metal interconnection layer, comprising: forming a second mask plate on the second metal interconnection layer; etching the second metal interconnection layer under the mask effect of the second mask plate until the photodiode is exposed to form a first recess; and sequentially stacking and arranging the filter and the microlens in the first recess.

[0009] In some possible implementation manners, the first active structure is divided into a third part and a fourth part in the second direction; and the first semiconductor structure is formed based on the first active structure, comprising: forming a first transistor of a first polarity based on the third part of the first active structure; and forming a second transistor of a second polarity based on the fourth part of the first active structure.

[0010] In some possible implementation manners, the first transistor of the first polarity is formed based on the third part of the first active structure, comprising: performing source-drain epitaxial growth on a source-drain region of the first transistor to form a first source-drain structure in the first transistor; depositing a metal material on a gate region of the first transistor to form a first gate structure in the first transistor; and performing a back-end process on the first gate structure to obtain a metal interconnection layer in the first transistor.

[0011] In some possible implementation manners, the second transistor of the second polarity is formed based on the fourth part of the first active structure, comprising: performing source-drain epitaxial growth on a source-drain region of the second transistor to form a second source-drain structure in the second transistor; depositing a metal material on a gate region of the second transistor to form a second gate structure in the second transistor; and performing a back-end process on the second gate structure to obtain a metal interconnection layer in the second transistor.

[0012] In a second aspect, an embodiment of the present application provides a semiconductor structure, which is prepared by the method in the first aspect, and the semiconductor structure comprises: a first semiconductor structure; and a second semiconductor structure; the first semiconductor structure and the second semiconductor structure are arranged in a stack in a first direction; wherein the first semiconductor structure comprises a first transistor of a first polarity and a second transistor of a second polarity, and the second semiconductor structure comprises a third transistor of the first polarity and an image sensor unit; the first transistor and the second transistor are arranged side by side in a second direction; the second direction is perpendicular to the first direction; and the third transistor and the image sensor unit are arranged side by side in the second direction.

[0013] In a third aspect, an embodiment of the present application provides a semiconductor device, comprising: the semiconductor structure according to the second aspect.

[0014] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising: a circuit board and the semiconductor device according to the third aspect, the semiconductor device is arranged on the circuit board.

[0015] In the present application, the first semiconductor structure and the second semiconductor structure are arranged in a stack, and the first semiconductor structure is a CMOS logic unit, and the second semiconductor structure is a CMOS image sensor. Through the film processing, the first semiconductor structure and the second semiconductor structure are arranged in a "back-to-back" stack, and the process compatibility problem of the CMOS logic unit and the CMOS image sensor is solved.

[0016] Further, while realizing the homogeneous integration of the CMOS logic unit and the CMOS image sensor, no additional area is occupied, and the integration density of the semiconductor structure is improved; due to the interconnection between the first semiconductor structure and the second semiconductor structure, the bandwidth of the semiconductor structure is higher, the interconnection delay is low, and the performance of the overall system (i.e. the semiconductor structure) is more friendly.

[0017] Further, the preparation of the first semiconductor structure and the preparation of the second semiconductor structure are independent of each other, and there is no need to consider the complex and tedious process compatibility problem of the CMOS logic circuit and the CMOS image sensor, which has great advantages for improving the yield and performance of the overall system.

[0018] Further, because the distance between the preparation of the first semiconductor structure and the second semiconductor structure is very close, the system performance decline caused by interconnection delay can be greatly reduced, which is very friendly to the future (artificial intelligence, AI), sensing and computing integration environment.

[0019] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0020] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present application and, together with the specification, serve to explain the principles of the present application.

[0021] Figure 1 The first example of the integration mode of the CMOS image sensor and the logic circuit;

[0022] Figure 2 The second example of the integration mode of the CMOS image sensor and the logic circuit;

[0023] Figure 3 An implementation flow diagram of a method for preparing a semiconductor structure in an embodiment of the present application;

[0024] Figure 4 A first structure diagram of a semiconductor structure in an embodiment of the present application;

[0025] Figures 5A to 5D A diagram of a preparation process of a semiconductor structure in an embodiment of the present application;

[0026] Figure 6 A second structure diagram of a semiconductor structure in an embodiment of the present application;

[0027] The above figures:

[0028] 10, semiconductor structure; 11, first semiconductor structure; 111, first transistor; 1111, first interlayer dielectric layer; 1112, first gate dielectric layer; 1113, first gate structure; 1114, first source-drain structure; 112, second transistor; 1121, second interlayer dielectric layer; 1122, second gate dielectric layer; 1123, second gate structure; 1124, second source-drain structure; 113, first metal interconnection layer; 12, second semiconductor structure; 121, third transistor; 1211, third interlayer dielectric layer; 1212, third gate dielectric layer; 1213, third gate structure; 1214, third source-drain structure; 122, image sensor unit; 1221, fourth interlayer dielectric layer; 1222, photodiode; 1224, optical filter; 1225, microlens; 123, second metal interconnection layer; 13, insulating layer; 14, carrier wafer; 21, substrate; 22, fin structure; 221, first fin structure; 222, second fin structure; 23, shallow trench isolation structure; 31, first nanosheet structure; 32, second nanosheet structure. DETAILED DESCRIPTION

[0029] The exemplary embodiments will be described in detail herein below with reference to the drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0030] A CMOS image sensor is an optical sensor that converts optical signals into electrical signals and converts the electrical signals into digital signals through a readout circuit, and is widely used in the field of vision and is a core component of a camera module. CMOS image sensors are often used in high-end mobile phone cameras, digital cameras, and digital single-lens reflex cameras, and the like.

[0031] Currently, the integration methods for CMOS image sensors and logic circuits include the following: 1. Integrating the CMOS image sensor chip and the logic computing chip (i.e., logic circuits) within the same package substrate using traditional packaging methods; 2. Figure 1 For a first example of how CMOS image sensors and logic circuits are integrated, see [link to relevant documentation]. Figure 1 As shown, through silicon via (TSV) technology is used to interconnect the pixel array and logic circuits in the peripheral area of ​​the chip; 3. Figure 2 For a second example of how CMOS image sensors and logic circuits are integrated, see [link to relevant documentation]. Figure 2 As shown, a CMOS image sensor chip and a logic computing chip are integrated together to form a three-dimensional stack through copper-copper hybrid bonding.

[0032] However, Method 1 uses traditional packaging methods, and the logic unit is far from the image sensor unit, resulting in poor performance. Method 2 uses TSV technology to interconnect the pixel array and logic circuit in the peripheral area of ​​the chip, resulting in low bandwidth. Method 3 integrates the logic circuit and CMOS image sensor in a homogeneous manner, and they are close to each other. The circuit design is more flexible, but the process is complex and the wafer bonding process has high alignment requirements.

[0033] To address the aforementioned technical problems, this application provides a method for fabricating a semiconductor structure to resolve the process compatibility issues between CMOS logic cells and CMOS image sensors.

[0034] In the embodiments of this application, the above-described semiconductor structure can be applied to semiconductor devices such as memory and processors.

[0035] In some embodiments, the semiconductor structure includes: a first semiconductor structure; a second semiconductor structure; the first semiconductor structure and the second semiconductor structure are stacked in a first direction; wherein the first semiconductor structure includes a first transistor of a first polarity and a second transistor of a second polarity, and the second semiconductor structure includes a third transistor of a first polarity and an image sensor unit; the first transistor and the second transistor are arranged side by side in a second direction; the second direction is perpendicular to the first direction; the third transistor and the image sensor unit are arranged side by side in the second direction.

[0036] In the embodiments of this application, the first transistor, the second transistor, and the third transistor in the semiconductor structure can be transistors of the same type, such as any of the following: fin field-effect transistor; gate-all-around transistor; planar transistor.

[0037] Figure 4 The semiconductor structure is composed of fin field-effect transistors, which will be discussed below. Figure 4A schematic diagram of the semiconductor structure is shown to illustrate the method for manufacturing the semiconductor structure provided in the embodiments of the present application.

[0038] Figure 3 An implementation flowchart of the method for manufacturing the semiconductor structure in the embodiments of the present application is shown. In some embodiments, the semiconductor structure includes a first semiconductor structure and a second semiconductor structure stacked in a first direction. Referring to Figure 3 As shown, the method for manufacturing the semiconductor structure can include:

[0039] S301, forming an active structure on a substrate. The active structure includes a first active structure and a second active structure.

[0040] It can be understood that the active structure can be formed by etching the substrate. The active structure includes a first active structure and a second active structure stacked; the semiconductor structure includes a first semiconductor structure and a second semiconductor structure stacked; the first semiconductor structure is formed based on the first active structure, and the second semiconductor structure is formed based on the second active structure.

[0041] In some embodiments, in the case where the first transistor, the second transistor and the third transistor are fin-type field effect transistors, the active structure is a fin structure.

[0042] In some embodiments, in the case where the first transistor, the second transistor and the third transistor are all-around gate transistors, the active structure is a columnar structure; and the columnar structure is a stack formed by the first semiconductor material and the second semiconductor material stacked in sequence; for example, the first semiconductor material can be silicon (Si), and the second semiconductor material can be silicon germanium (SiGe). The second semiconductor material serves as a sacrificial material, and in a subsequent manufacturing process of the transistor, the second semiconductor material can be removed to form a nanosheet or nanolayer structure in the all-around gate transistor.

[0043] In some embodiments, in the case where the first transistor, the second transistor and the third transistor are planar transistors, the active structure is a block structure.

[0044] In some embodiments, since the first active structure and the second active structure are formed by the same process, the first semiconductor structure formed based on the first active structure and the second semiconductor structure formed based on the second active structure share the same active region.

[0045] In the embodiments of the present application, the active region is the collective term of the source region, the drain region and the channel region.

[0046] S302, forming a first semiconductor structure based on the first active structure. The first semiconductor structure includes a first transistor of a first polarity and a second transistor of a second polarity. The first transistor and the second transistor are arranged side by side in a second direction. The second direction is perpendicular to the first direction.

[0047] It can be understood that the first transistor and the second transistor have different polarities, and the first transistor and the second transistor are complementary transistors, that is, the first polarity and the second polarity are complementary. Based on the complementary first transistor and the second transistor, the first semiconductor structure is a complementary metal oxide semiconductor (CMOS). The first polarity can be N type, and the second polarity can be P type. Then, the first transistor is an N channel metal-oxide-semiconductor field-effect transistor (MOS) tube, and the second transistor is a P channel MOS tube.

[0048] S303, flipping and thinning the substrate until the second active structure is exposed.

[0049] It can be understood that after the first semiconductor structure is formed, the first semiconductor structure can be subjected to a flipping process so that the substrate is placed upward, and then the substrate is thinned until the surface of the second active structure away from the first active structure is exposed. The first semiconductor structure and the second semiconductor structure formed based on the flipping process are arranged in a "back-to-back" manner.

[0050] In some embodiments, the substrate can be thinned by a chemical-mechanical planarization (CMP) process.

[0051] In some possible implementations, before S303 described above, the method for manufacturing the semiconductor structure described above can further include: depositing an insulating material on the surface of the first semiconductor structure away from the second active structure to form an insulating layer; and bonding the insulating layer with a slide wafer.

[0052] In the embodiments of the present application, the slide wafer after bonding can provide physical support for the first semiconductor structure after being flipped, effectively preventing the first semiconductor structure from being broken by external force during the process of manufacturing the second semiconductor structure.

[0053] It should be noted that the insulating material for forming the insulating layer can be selected according to actual needs, and the embodiments of the present application do not make specific limitations in this regard.

[0054] S304, forming a second semiconductor structure based on the second active structure. The second semiconductor structure includes a third transistor of the first polarity and an image sensor unit, and the third transistor and the image sensor unit are arranged side by side in the second direction.

[0055] It can be understood that after the second active structure is exposed, the third transistor and the image sensor unit can be formed based on a standard process of manufacturing a transistor and an image sensor. The third transistor is a transistor of the first polarity, i.e., the third transistor is an N-channel MOS transistor.

[0056] In some possible implementations, the second active structure is divided into a first part and a second part in the second direction. S304 can include: forming the second semiconductor structure based on the second active structure, including: forming third source / drain structures and a third gate structure in the third transistor based on the first part of the second active structure; forming a photodiode in the image sensor unit based on the second part of the second active structure; forming a second metal interconnection layer in the second semiconductor structure on the third gate structure and the photodiode; disposing an optical element in the second metal interconnection layer; and connecting the optical element with the photodiode.

[0057] It can be understood that the third transistor and the image sensor unit in the second semiconductor structure are arranged side by side, and based on this, the second active structure can be divided into two parts arranged side by side, i.e., the first part and the second part. The third transistor is formed based on the first part of the second active structure, and the image sensor unit is formed based on the second part of the second active structure.

[0058] In some embodiments, after the second active structure is exposed, the third source / drain structures and the third gate structure in the third transistor can be formed based on the first part of the second active structure first; then, the photodiode can be formed based on the second part of the second active structure; a subsequent process is performed on the third gate structure and the photodiode to form a second metal interconnection layer in the second semiconductor structure; an optical element in contact with the photodiode is disposed in the second metal interconnection layer; and thus, the second semiconductor structure is formed.

[0059] In some embodiments, the photodiode can be a PIN diode or a PN junction diode, or other types of photodiodes can be selected according to actual requirements, and the embodiments of the present application do not make specific limitations in this regard.

[0060] In some possible implementation manners, the second part of the second active structure, based on which the photodiode in the image sensor unit is formed, can include: forming a first mask plate on the second part of the second active structure; and performing ion implantation on the second part of the second active structure under the mask effect of the first mask plate to form the photodiode.

[0061] It can be understood that, the mask material is first deposited on the second active structure, and a part of the mask material is etched to obtain the first mask plate with the preset pattern; and the ion implantation process is performed on the second part of the second active structure under the mask effect of the first mask plate, P-type ions are first implanted, and then N-type ions are implanted to form the photodiode.

[0062] In some possible implementation manners, the optical element includes a filter and a microlens; and the optical element is arranged in the second metal interconnection layer, which can include: forming a second mask plate on the second metal interconnection layer; etching the second metal interconnection layer until the photodiode is exposed to form a first recess under the mask effect of the second mask plate; and sequentially stacking and arranging the filter and the microlens in the first recess.

[0063] It can be understood that, after the second metal interconnection layer is formed, the second metal interconnection layer covers the photodiode, the mask material is deposited on the second metal interconnection layer to form the second mask plate; then, the second metal interconnection layer is etched to stop etching at the photodiode under the effect of the second mask plate to form the first recess; and the optical element such as the filter and the microlens is sequentially formed and stacked in the first recess to form the image sensor unit.

[0064] It should be noted that the forming process of the second mask plate is the same as that of the first mask plate, and details are not repeated herein.

[0065] In some possible implementation manners, the first active structure is divided into a third part and a fourth part in the second direction; and S302 can include: forming a first transistor of a first polarity based on the third part of the first active structure; and forming a second transistor of a second polarity based on the fourth part of the first active structure.

[0066] It can be understood that the first transistor and the second transistor in the first semiconductor structure are arranged side by side, based on which the first active structure can be divided into two parts arranged side by side, which are the third part and the fourth part; the first transistor is formed based on the third part of the first active structure, and the second transistor is formed based on the fourth part of the first active structure.

[0067] In some possible implementation manners, the third part of the first active structure, which forms the first transistor of the first polarity, can include: performing source-drain epitaxial growth on a source-drain region of the first transistor to form a first source-drain structure in the first transistor; depositing a metal material on a gate region of the first transistor to form a first gate structure in the first transistor; and performing a post-process on the first gate structure to obtain a metal interconnection layer in the first transistor.

[0068] It can be understood that the first transistor of the first polarity can be prepared according to a standard process for preparing an N-channel MOS transistor.

[0069] In some embodiments, the process of forming the first transistor can include: performing photolithography to open a first gate region of the first transistor, depositing a semiconductor material in the first gate region to form a first dummy gate structure, and forming first spacers on both sides of the first dummy gate structure. The first transistor is formed by etching the third part of the first active structure to provide a source-drain recess of the first transistor. The first spacers are used as a mask to form a strained material such as silicon germanium or silicon carbide in the source-drain recess of the first transistor by selective epitaxial growth to fill the source-drain recess of the first transistor, and then a first source-drain structure is formed on the strained material by a heavy doping process. An insulating material (such as silicon dioxide (SiO2)) is deposited on the third part of the first active structure and the first source-drain structure to form a first interlayer dielectric layer; the first interlayer dielectric layer can cover the third part of the first active structure and the first source-drain structure. The first dummy gate structure is removed by etching to expose the first gate region, and an insulating material is deposited on the first active structure in the first gate region to form a first gate dielectric layer of the first transistor. A metal material is deposited in the first gate region to form a first gate structure of the first transistor. A portion of the first interlayer dielectric layer above the first source-drain structure is etched until the upper surface of the first source-drain structure is exposed to form a first source-drain metal recess. A metal material is deposited in the first source-drain metal recess to form a first source-drain metal structure. Interconnection line dielectric deposition, metal line formation, and lead pad formation are performed on the first gate structure and the first source-drain metal to form a metal interconnection layer of the first transistor.

[0070] It should be noted that, for the sake of brevity, the first source-drain structure mentioned in the embodiments of the present application is a simple term, and specifically refers to a first source structure and / or a first drain structure. In addition, the second source-drain structure, the third source-drain structure, and the source-drain recess are similar to the first source-drain structure, and "source-drain" is a simple term for "source and / or drain".

[0071] In some possible implementation manners, the fourth part of the first active structure, which forms the second transistor of the second polarity, can include: performing source-drain epitaxial growth on a source-drain region of the second transistor to form a second source-drain structure in the second transistor; depositing a metal material on a gate region of the second transistor to form a second gate structure in the second transistor; and performing a post-process on the second gate structure to obtain a metal interconnection layer in the second transistor.

[0072] It can be understood that the second transistor of the second polarity can be prepared according to a standard process for preparing a P-channel MOS transistor.

[0073] In some embodiments, the process of forming the second transistor can include: performing photolithography to open a second gate region of the second transistor, depositing a semiconductor material in the second gate region to form a second dummy gate structure, and forming a second spacer on both sides of the second dummy gate structure. The source-drain recess of the second transistor is formed by etching the fourth part of the second active structure. The silicon germanium or silicon carbide or other strain material is formed by selective epitaxial growth in the source-drain recess of the second transistor to fill the source-drain recess of the second transistor, and then a second source-drain structure is formed on the strain material by a heavy doping process. The second interlayer dielectric layer is formed by depositing an insulating material on the fourth part of the second active structure and the second source-drain structure. The second gate dielectric layer of the second transistor is formed by removing the second dummy gate structure by etching and depositing an insulating material on the first active structure in the second gate region. The second gate structure of the second transistor is formed by depositing a metal material in the second gate region. The second source-drain metal structure is formed by etching a part of the second interlayer dielectric layer above the second source-drain structure until the upper surface of the second source-drain structure is exposed to form a second source-drain metal recess. The second source-drain metal structure is formed by depositing a metal material in the second source-drain metal recess. The metal interconnection layer of the second transistor can be formed by performing interconnection line dielectric deposition, metal line formation, and pad formation on the second gate structure and the second source-drain metal.

[0074] It should be noted that the metal interconnection layer in the first transistor and the metal interconnection layer in the second transistor together form the first metal interconnection layer in the first semiconductor structure.

[0075] In the embodiments of the present application, the metal material of the gate structure (the first gate structure, the second gate structure, and the third gate structure) can include but is not limited to tantalum nitride (TaN), titanium nitride (TiN), aluminum nitride (AlN), titanium aluminum carbide (TiAlC), and titanium aluminum nitride (TiAlN). The materials of the first gate structure, the second gate structure, and the third gate structure can be selected according to actual conditions and are not limited to the metal materials listed above.

[0076] It should be noted that the same structures in the first transistor and the second transistor can be formed in the same process, for example, the source-drain structures (i.e., the first source-drain structure and the second source-drain structure), the spacers (i.e., the first spacer and the second spacer), the interlayer dielectric layers (i.e., the first interlayer dielectric layer and the second interlayer dielectric layer), and the metal interconnection layers (i.e., the first metal interconnection layer and the second metal interconnection layer).

[0077] In some embodiments, the first semiconductor structure is a complementary metal-oxide semiconductor, and the first gate structure and the second gate structure can be formed separately, that is, the first dummy gate structure corresponding to the position of the first gate structure is removed by etching to expose the first gate region, a metal material is deposited in the first gate region to form the first gate structure, and then the second dummy gate structure is removed by etching to expose the second gate region, and a metal material is deposited in the second gate region to form the second gate structure.

[0078] In the embodiments of the present application, the semiconductor material for forming the dummy gate structure (i.e., the first dummy gate structure, the second dummy gate structure, and the third dummy gate structure) can include but is not limited to amorphous carbon, amorphous silicon, and the like, and can also be other semiconductor materials, which are not limited in the embodiments of the present application.

[0079] In some embodiments, the process of forming the third transistor can include: lithographically opening a third gate region of the third transistor, depositing a semiconductor material in the third gate region to form a third dummy gate structure; and forming a third spacer on both sides of the third dummy gate structure. The first portion of the second active structure is etched to provide a source-drain recess of the third transistor. A strained material such as silicon germanium or silicon carbide is formed in the source-drain recess of the third transistor by selective epitaxy growth to fill the source-drain recess of the third transistor, with the third spacer as a mask, and then a third source-drain structure is formed on the strained material by a heavy doping process. An insulating material is deposited on the first portion of the second active structure and the third source-drain structure to form a third interlayer dielectric layer; the third interlayer dielectric layer can cover the first portion of the first active structure and the third source-drain structure. The third dummy gate structure is removed by etching to expose the third gate region, and an insulating material is deposited on the second active structure in the third gate region to form a third gate dielectric layer of the third transistor. A metal material is deposited in the third gate region to form a third gate structure of the third transistor. A portion of the third interlayer dielectric layer above the third source-drain structure is etched until the upper surface of the third source-drain structure is exposed to form a third source-drain metal recess. A metal material is deposited in the third source-drain metal recess to form a third source-drain metal structure. Interconnection line dielectric deposition, metal line formation, and lead pad formation are performed on the third gate structure and the third source-drain metal to form a metal interconnection layer of the third transistor.

[0080] In some embodiments, the process of forming the image sensor unit can include: depositing an insulating material on the second portion of the second active structure to form a fourth interlayer dielectric layer; the fourth interlayer dielectric layer can cover the second portion of the first active structure. An ion implantation process is performed on the second portion of the second active structure to form a photodiode. A dielectric material is deposited on the photodiode and the fourth interlayer dielectric layer to form a metal interconnection layer of the image sensor unit. The metal interconnection layer in the image sensor unit is etched to form a first recess, a filter is formed on the photodiode in the first recess, and a microlens is formed on the filter.

[0081] It should be noted that the metal interconnection layer in the third transistor and the metal interconnection layer in the image sensor unit together constitute a second metal interconnection layer in the second semiconductor structure.

[0082] In some embodiments, in order to realize the isolation of the first semiconductor structure and the second semiconductor structure, a silicon-on-insulator (SOI) substrate can be used to prepare the semiconductor structure. The insulating layer in the SOI substrate is located between the first active structure and the second active structure, which can effectively isolate the first active structure and the second active structure, and further isolate the first semiconductor structure and the second semiconductor structure.

[0083] In some embodiments, to achieve the isolation of the first semiconductor structure and the second semiconductor structure, ion implantation can be performed between the first active structure and the second active structure to achieve electrical isolation between the first active structure and the second active structure, thereby isolating the first semiconductor structure and the second semiconductor structure.

[0084] In some embodiments, the ions implanted between the first active structure and the second active structure can include, but are not limited to, any one of the following: P-type ions, N-type ions, and oxygen ions.

[0085] In the following, the first transistor, the second transistor, and the third transistor are taken as fin-type field effect transistors, and the substrate is taken as an SOI substrate as an example to describe the semiconductor structure provided by the embodiments of the present application. Figure 4 Fig. 1 is a first schematic diagram of the semiconductor structure in the embodiments of the present application. In the figure, Figure 4 (a) is a design layout of the semiconductor structure. It should be noted that, for the purpose of understanding, only the fin structure, the gate structure, and the source-drain structure are shown in the design layout; (b) is a sectional view of the semiconductor structure along the direction of the sectional surface of the gate structure (i.e., the A-A' direction); (c) is a sectional view of the semiconductor structure along the direction of the sectional surface of the fin structure corresponding to the first transistor and the third transistor (i.e., the B-B' direction); and (d) is a sectional view of the semiconductor structure along the direction of the sectional surface of the fin structure corresponding to the third transistor and the image sensor unit (i.e., the C-C' direction).

[0086] Figure 4 The semiconductor structure 10 shown in the figure can be prepared by Figures 5A to 5D the flow shown in the figure, Figures 5A to 5D Fig. 2 is a schematic diagram of the preparation process of the semiconductor structure in the embodiments of the present application.

[0087] In an example, the preparation process of the semiconductor structure 10 can include the following steps:

[0088] Step 1: providing a substrate 21 (see Figure 5A (a) in the figure).

[0089] Step 2: etching the substrate by the side wall method to form a fin structure 22 (see Figure 5B (a) in the figure). In the figure, the number of the first fin structure 221 corresponding to the first semiconductor structure 11 is 4, and the number of the second fin structure 222 corresponding to the second semiconductor structure 12 is 2. The first fin structure 221 and the second fin structure 222 are isolated by the insulating layer in the SOI substrate.

[0090] Third step: depositing insulating material on the first fin structure 221, the second fin structure 222 and the substrate 21 to form the shallow trench isolation structure 23, at this time, the height of the shallow trench isolation structure 23 is greater than the height of the fin structure 22; through the CMP process and the selective etching treatment, the shallow trench isolation structure 23 wrapping the first fin structure 221 is removed to expose the first fin structure 221 (see Figure 5A (c) in the middle).

[0091] Fourth step: based on the first fin structure 221, forming the first interlayer dielectric layer 1111, the second interlayer dielectric layer 1121, the first gate dielectric layer 1112, the second gate dielectric layer 1122, the first gate structure 1113, the second gate structure 1123, the first source-drain structure 1114, the second source-drain structure 1124 and the first metal interconnection layer 113 (see Figure 5B (a) in the middle). At this time, the first transistor 111 and the second transistor 112 are formed.

[0092] Fifth step: depositing insulating material on the first semiconductor structure 11 to form the insulating layer 13; bonding the insulating layer 13 and the carrier wafer 14 together (see Figure 5B (b) in the middle).

[0093] Sixth step: carrying out the film stripping treatment on the first semiconductor structure 11 so that the substrate 21 is placed upwards (see Figure 5B (c) in the middle).

[0094] Seventh step: carrying out the thinning treatment on the substrate 21 so that the surface of the second fin structure 222 far away from the first fin structure 221 is exposed (see Figure 5C (a) in the middle).

[0095] Eighth step: based on the second fin structure 222, forming the third gate dielectric layer 1212, the third gate structure 1213 and the third source-drain structure 1214 in the third transistor 121 (see Figure 5C (b) in the middle).

[0096] Ninth step: carrying out the ion implantation treatment on the second fin structure 222 corresponding to the second transistor 112 to form the photodiode 1222 in the image sensor unit 122 (see Figure 5C (c) in the middle).

[0097] Tenth step: forming the third interlayer dielectric layer 1211 in the third transistor 121 and the fourth interlayer dielectric layer 1221 in the image sensor unit 122; forming the second metal interconnection layer 123 in the second semiconductor structure 12; disposing the optical filter 1224 and the microlens 1225 on the photodiode 1222 in the second metal interconnection layer 123 (see Figure 5D ).

[0098] So far, the semiconductor structure 10 is prepared according to the above preparation method.

[0099] In an embodiment, the first transistor, the second transistor and the third transistor are all gate-all-around transistors, and the substrate is an SOI substrate. The semiconductor structure provided by the embodiment of the present application is described. Figure 6 Fig. 2 is a second structural schematic diagram of the semiconductor structure in the embodiment of the present application. In Fig. 2, Figure 6 (a) in Fig. 2 is a design layout of the semiconductor structure. It should be noted that, for the convenience of understanding, only the nanosheet structure, the gate structure and the source-drain structure are shown in the design layout; (b) is a sectional view of the semiconductor structure along the direction of the sectional surface of the gate structure (i.e. the direction of A-A'); (c) is a sectional view of the semiconductor structure along the direction of the sectional surface of the nanosheet structure corresponding to the first transistor and the third transistor (i.e. the direction of B-B').

[0100] In some embodiments, referring to Fig. 3, Figure 6 It is shown that the first nanosheet structure 31 in the first semiconductor structure 11 and the second nanosheet structure 32 in the second semiconductor structure 12 are formed by removing the sacrificial material (i.e. the second semiconductor material) in the active structure. It should be noted that, in addition to the first nanosheet structure 31 and the second nanosheet structure 32, Figure 6 The semiconductor structure 10 shown in Fig. 4 is prepared by the same method as the semiconductor structure shown in Fig. 1, and the embodiment of the present application does not make specific limitations thereto. Figure 4

[0101] In the embodiment of the present application, the first semiconductor structure and the second semiconductor structure are stacked, the first semiconductor structure is a CMOS logic unit, the second semiconductor structure is a CMOS image sensor, and the first semiconductor structure and the second semiconductor structure are stacked in a "back-to-back" manner through film reversal processing, so as to solve the process compatibility problem of the CMOS logic unit and the CMOS image sensor.

[0102] Further, while realizing the homogeneous integration of the CMOS logic unit and the CMOS image sensor, no additional area is occupied, and the integration density of the semiconductor structure is improved; due to the interconnection between the first semiconductor structure and the second semiconductor structure, the bandwidth of the semiconductor structure is higher, the interconnection delay is low, and the performance of the overall system (i.e. the semiconductor structure) is more friendly.

[0103] Further, the preparation of the first semiconductor structure and the preparation of the second semiconductor structure are independent of each other, and there is no need to consider the complex and cumbersome process compatibility problem of the CMOS logic circuit and the CMOS image sensor, which has great advantages for improving the yield and performance of the overall system.

[0104] ​Further, because the distance between the preparation of the first semiconductor structure and the second semiconductor structure is very close, the system performance decline caused by interconnection delay can be greatly reduced, which is very friendly to future (artificial intelligence, AI), sensor integration, etc.

[0105] Further, the semiconductor structure provided by the embodiments of the present application can be detected by detection analysis instruments, such as a scanning electron microscope (SEM), a transmission electron microscope (TEM), a scanning transmission electron microscope (STEM), etc. Taking the TEM as an example, the semiconductor structure provided by the embodiments of the present application can be detected in the form of TEM sectioning. For example, the first semiconductor structure includes a first transistor and a second transistor, the second semiconductor structure includes a third transistor and an image sensor unit, and the first semiconductor structure and the second semiconductor structure share the same active region.

[0106] The embodiments of the present application provide a semiconductor device, including the semiconductor structure as described above. The specific limitations of the semiconductor structure can be referred to the semiconductor structure as described above Figure 4 and Figure 6 , which will not be repeated here.

[0107] The embodiments of the present application provide an electronic device, including a circuit board and a semiconductor device as described above. The semiconductor device is arranged on the circuit board. The semiconductor device includes the semiconductor structure as described above. The specific limitations of the semiconductor structure can be referred to the semiconductor structure as described above Figure 4 and Figure 6 , which will not be repeated here.

[0108] In the description of the present application, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present application, the illustrative description of the above terms is not necessarily for the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, the skilled in the art can combine the different embodiments or examples described in the present application and the features of the different embodiments or examples without contradiction.

[0109] The above merely provides preferred embodiments of the present application, and is not used to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the principles and technical scope of the present application shall fall into the scope of the present application.

Claims

1. A method of fabricating a semiconductor structure, characterized by, The semiconductor structure includes a first semiconductor structure and a second semiconductor structure stacked in a first direction, the first semiconductor structure being a complementary metal-oxide semiconductor (CMOS), and the second semiconductor structure being a CMOS image sensor; and the method includes: forming an active structure on a substrate; the active structure includes a first active structure and a second active structure; forming the first semiconductor structure based on the first active structure; the first semiconductor structure includes a first transistor of a first polarity and a second transistor of a second polarity; the first transistor and the second transistor are arranged side by side in a second direction; the second direction is perpendicular to the first direction; reversing and thinning the substrate until the second active structure is exposed; forming a second semiconductor structure based on the second active structure; the second semiconductor structure includes a third transistor of the first polarity and an image sensor unit; the third transistor and the image sensor unit are arranged side by side in the second direction.

2. The method of claim 1, wherein, The second active structure is divided into a first part and a second part in the second direction; The forming the second semiconductor structure based on the second active structure includes: forming a third source-drain structure and a third gate structure in the third transistor based on the first part of the second active structure; forming a photodiode in the image sensor unit based on the second part of the second active structure; forming a second metal interconnection layer in the second semiconductor structure on the third gate structure and the photodiode; arranging an optical element in the second metal interconnection layer; the optical element is connected to the photodiode.

3. The method of claim 2, wherein, The forming the photodiode in the image sensor unit based on the second part of the second active structure includes: forming a first mask on the second part of the second active structure; performing ion implantation on the second part of the second active structure under the mask of the first mask to form the photodiode.

4. The method of claim 2, wherein, The optical element includes a filter and a microlens; The arranging the optical element in the second metal interconnection layer includes: forming a second mask on the second metal interconnection layer; etching the second metal interconnection layer under the mask of the second mask until the photodiode is exposed to form a first recess; stacking the filter and the microlens in the first recess in sequence.

5. The method of claim 1, wherein, The first active structure is divided into a third part and a fourth part in the second direction; The forming the first semiconductor structure based on the first active structure includes: forming the first transistor of the first polarity based on the third part of the first active structure; forming the second transistor of the second polarity based on the fourth part of the first active structure.

6. The method of claim 5, wherein, The forming the first transistor of the first polarity based on the third part of the first active structure includes: performing source-drain epitaxial growth on a source-drain region of the first transistor to form a first source-drain structure in the first transistor; depositing a metal material on a gate region of the first transistor to form a first gate structure in the first transistor; Performing post-process on the first gate structure to obtain a metal interconnection layer in the first transistor.

7. The method of claim 5, wherein, The fourth part of the first active structure forms a second transistor of a second polarity, comprising: Performing source-drain epitaxial growth on the source-drain region of the second transistor to form a second source-drain structure in the second transistor; Depositing a metal material on the gate region of the second transistor to form a second gate structure in the second transistor; Performing post-process on the second gate structure to obtain a metal interconnection layer in the second transistor.

8. A semiconductor structure, characterized by The semiconductor structure is prepared by the method of any one of claims 1 to 7, comprising: a first semiconductor structure; a second semiconductor structure; the first semiconductor structure and the second semiconductor structure are arranged in a stack in a first direction; wherein the first semiconductor structure is a complementary metal-oxide semiconductor (CMOS), and the second semiconductor structure is a CMOS image sensor; the first semiconductor structure comprises a first transistor of a first polarity and a second transistor of a second polarity, and the second semiconductor structure comprises a third transistor of the first polarity and an image sensor unit; the first transistor and the second transistor are arranged side by side in a second direction; the second direction is perpendicular to the first direction; the third transistor and the image sensor unit are arranged side by side in the second direction; and the first semiconductor structure and the second semiconductor structure share the same active region.

9. A semiconductor device, characterized by comprising: comprising: the semiconductor structure of claim 8.

10. An electronic device, comprising: comprising: a circuit board and the semiconductor device of claim 9, the semiconductor device being arranged on the circuit board.

Images