Branching filter and communication device

Abstract

In the branching filter, a first filter connects a common terminal and a first terminal and corresponds to a first passband. The second filter connects the common terminal and the second terminal and corresponds to the second passband. A third filter connects the node and the second terminal and corresponds to the first passband. The fourth filter connects the node and the first terminal and corresponds to the second passband. The 180-degree phase shifter is located on a side closer to the first terminal than the first filter and the fourth filter, or on a side closer to the second terminal than the second filter and the third filter. The 180 DEG phase shifter inverts output signals of two paths based on the same input signal, the two paths being a path from the first terminal to the second terminal via the first filter and the second filter, and a path from the first terminal to the second terminal via the fourth filter and the third filter.

Description

Technical Field

[0001] The present disclosure relates to a splitter having two or more filters and a communication device including the splitter. Background Art

[0002] As a splitter, a duplexer having a transmission filter and a reception filter is known (for example, the following patent document 1). The transmission filter connects the transmission terminal and the antenna terminal, filters the transmission signal input from the transmission terminal and outputs it to the antenna terminal. The reception filter connects the antenna terminal and the reception terminal, filters the reception signal input from the antenna terminal and outputs it to the reception terminal. In other viewpoints, the reception filter blocks the transmission signal output from the transmission filter and prohibits the transmission signal from being input to the reception terminal. However, in reality, the signal output from the transmission filter (for example, the transmission signal) is not completely blocked by the reception filter. That is, a leakage signal is generated that passes through the reception filter and toward the reception terminal.

[0003] In Patent Document 1, the leakage signal is reduced and the isolation characteristics are improved. Specifically, in Patent Document 1, a delay line and a resonator connected in parallel with a transmission filter and a reception filter are provided between a transmission terminal and a reception terminal. When a transmission signal is input from the transmission terminal, the delay line and the resonator generate an elimination signal and output it to the reception terminal, wherein the elimination signal has an amplitude equal to that of the leakage signal and has a phase opposite to that of the leakage signal. As a result, the elimination signal and the leakage signal cancel each other, thereby reducing the leakage signal.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2013-118611 Summary of the invention

[0007] A wave splitter of one embodiment of the present invention comprises: a first filter, a second filter, a third filter, a fourth filter and a 180° phase shifter. The first filter connects a common terminal and a first terminal and corresponds to a first passband. The second filter connects the common terminal and the second terminal and corresponds to a second passband that does not overlap with the first passband. The third filter connects a node located at a branch point and the second terminal and corresponds to the first passband. The fourth filter connects the node and the first terminal and corresponds to the second passband. The 180° phase shifter is located on a side closer to the first terminal than the first filter and the fourth filter, or is located on a side closer to the second terminal than the second filter and the third filter. In addition, the 180° phase shifter makes the output signals of two paths based on the same input signal in opposite phases to each other, wherein the two paths are a path from the first terminal via the first filter and the second filter to the second terminal, and a path from the first terminal via the fourth filter and the third filter to the second terminal.

[0008] A communication device according to one aspect of the present disclosure includes: the above-mentioned splitter; an antenna connected to the common terminal; a resistor connected to the node; and an integrated circuit element connected to the first terminal and the second terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 : is a circuit diagram showing the structure of the branching filter according to the embodiment.

[0010] Figure 2 Yes means Figure 1 A schematic stereoscopic diagram of a first structural example of a splitter.

[0011] Figure 3 Yes means Figure 2 A plan view showing an example of the structure of a splitter chip.

[0012] Figure 4 Yes means Figure 1 A schematic stereoscopic diagram of a second construction example of a splitter.

[0013] Figure 5 Yes means Figure 4 A plan view of a structure example of a splitter chip.

[0014] Figure 6 This is a block diagram showing the structure of a communication device according to an embodiment. DETAILED DESCRIPTION

[0015] The following describes the embodiments of the present disclosure with reference to the accompanying drawings. In addition, the drawings used in the following description are schematic. Therefore, for example, the dimensional ratios on the drawings may not be consistent with reality. In addition, the dimensional ratios, etc. are sometimes inconsistent between the drawings. Specific shapes and / or dimensions are sometimes exaggerated, or details are sometimes omitted. However, the above description does not deny that the actual shape and / or dimensions may differ from the attached drawings. Figure 1 or features of shape and / or size may be extracted from the accompanying drawings.

[0016] (Overview of the Demultiplexer of the Embodiment)

[0017] Here, the outline of the duplexer 1 (an example of a splitter) according to the embodiment is described. In the description of the outline of the duplexer 1, for convenience, unless otherwise specified, features that can be variously configured are sometimes described using a specific configuration as an example.

[0018] Figure 1 It is a circuit diagram showing the structure of a duplexer 1 (an example of a branching filter) according to the embodiment.

[0019] The duplexer 1 includes a first transmission filter 5TA and a first reception filter 5RA. The first transmission filter 5TA filters the transmission signal input from the outside to the transmission terminal 3T and outputs it to the antenna terminal 3A. The first reception filter 5RA filters the reception signal input from the antenna to the antenna terminal 3A and outputs it to the reception terminal 3R. The first transmission filter 5TA attenuates the signal outside the transmission band (allows the signal of the transmission band to pass). The first reception filter 5RA attenuates the signal outside the reception band (allows the signal of the reception band to pass). The transmission band and the reception band do not overlap. It can be considered that the first transmission filter 5TA and the first reception filter 5RA constitute the first duplexer 7A.

[0020] The transmission signal from the transmission terminal 3T that has passed through the first transmission filter 5TA is attenuated (blocked) by the first reception filter 5RA, and is therefore basically (ideally) not output to the reception terminal 3R. However, in reality, a leakage signal is generated that passes through the first reception filter 5RA and leaks to the reception terminal 3R. In order to reduce the leakage signal, the duplexer 1 has a parallel path 15 connected in parallel with the first duplexer 7A between the transmission terminal 3T and the reception terminal 3R.

[0021] The parallel path 15 includes, for example, a second duplexer 7B and a phase shifter 9, wherein the second duplexer 7B has a structure substantially the same as that of the first duplexer 7A, and the phase shifter 9 is connected in series with the second duplexer 7B. The second duplexer 7B includes a second transmission filter 5TB and a second reception filter 5RB, wherein the second transmission filter 5TB and the second reception filter 5RB have structures substantially the same as those of the first transmission filter 5TA and the first reception filter 5RA. The connection order of the second transmission filter 5TB and the second reception filter 5RB relative to the transmission terminal 3T and the reception terminal 3R is opposite to the connection order of the first transmission filter 5TA and the first reception filter 5RA relative to the transmission terminal 3T and the reception terminal 3R. The phase shifter 9 shifts the phase of the input signal by 180° and outputs it.

[0022] The transmission signal input from the outside to the transmission terminal 3T is basically blocked by the second reception filter 5RB, and thus does not flow into the parallel path 15. Therefore, the transmission signal flows to the first transmission filter 5TA as in the case where the parallel path 15 is not provided. In other words, ideally, no insertion loss is generated due to the provision of the parallel path 15. Similarly, the reception signal from the antenna terminal 3A through the first reception filter 5RA is basically blocked by the second transmission filter 5TB, and thus does not flow into the parallel path 15. Therefore, ideally, no insertion loss is generated in the reception signal due to the provision of the parallel path 15.

[0023] On the other hand, it can be understood from the situation that a leakage signal is generated from the transmitting terminal 3T through the first transmitting filter 5TA and the first receiving filter 5RA toward the receiving terminal 3R that, in fact, a part of the transmitting signal from the transmitting terminal 3T passes through the second receiving filter 5RB. The signal (hereinafter, sometimes referred to as "elimination signal") passes through the second duplexer 7B having the same structure (same characteristics) as the first duplexer 7A, and therefore has the same intensity as the intensity of the leakage signal (for example, voltage, current or power, the same below). In addition, since the phase of the elimination signal is offset by 180° by the phase shifter 9, the elimination signal has a phase opposite to the phase of the leakage signal. Therefore, the two cancel each other out. As a result, the leakage signal output from the receiving terminal 3R to the outside of the duplexer 1 is reduced.

[0024] The parallel path 15 has a node 17, and the node 17 is connected to the resistor element 11 between the second reception filter 5RB and the second transmission filter 5TB. The resistor element 11 is connected to the node 17 and the reference potential unit 13. The resistor element 11, for example, helps to reproduce the effect of the antenna terminal 3A on the leakage signal passing through the first duplexer 7A in the cancellation signal passing through the second duplexer 7B. As a result, the leakage signal and the cancellation signal are easily offset. The resistor element 11 can be included in the duplexer 1, or it can be an element outside the duplexer 1.

[0025] The above-mentioned duplexer 1 can be realized by various structures.

[0026] For example, in Figure 2 In the first configuration example shown, four chips 23 are mounted on the multilayer substrate 21A. The four chips 23 respectively constitute the first transmission filter 5TA, the first reception filter 5RA, the second transmission filter 5TB, and the second reception filter 5RB. The phase shifter 9 is constituted by the transmission line in the multilayer substrate 21A.

[0027] In addition, for example, in Figure 4 In the second structural example shown, two chips 25 are mounted on the multi-layer substrate 21B. The two chips 25 constitute the first duplexer 7A and the second duplexer 7B, respectively. The phase shifter 9 is constituted by the transmission line in the multi-layer substrate 21B.

[0028] The above is an overview of the duplexer 1 according to the embodiment. Hereinafter, the duplexer 1 will be described roughly in the following order.

[0029] 1. Duplexer overall ( Figure 1 )

[0030] Filter

[0031] 1.2. Phase shifter

[0032] 1.3.Resistor

[0033] 1.4. First duplexer and second duplexer

[0034] 2. Specific example of the structure of a duplexer

[0035] 2.1. First construction example ( Figure 2 as well as Figure 3 )

[0036] 2.1.1. Overall structure of the duplexer

[0037] 2.1.2. Multilayer substrate

[0038] 2.1.3. Chip

[0039] 2.1.4. Connection construction example

[0040] 2.1.5. Example of Phase Shifter Construction

[0041] 2.2. Second construction example ( Figure 4 as well as Figure 5 )

[0042] 2.3. Other construction examples

[0043] 2.4. Node construction example

[0044] 3. Communication equipment including duplexer ( Figure 6 )

[0045] 4. Summary of implementation methods

[0046] (1. Duplexer as a whole)

[0047] In the following description, the antenna terminal 3A, the transmission terminal 3T, and the reception terminal 3R are sometimes referred to as "terminal 3" without distinguishing each other. In addition, the first duplexer 7A and the second duplexer 7B are sometimes referred to as "duplexer 7" without distinguishing each other. The first transmission filter 5TA and the second transmission filter 5TB are sometimes referred to as "transmission filter 5T" without distinguishing each other. The first reception filter 5RA and the second reception filter 5RB are sometimes referred to as "reception filter 5R" without distinguishing each other. The transmission filter 5T and the reception filter 5R are sometimes referred to as "filter 5" without distinguishing each other.

[0048] The path from the transmission terminal 3T to the reception terminal 3R via the first duplexer 7A is called the first path RT1. The path from the transmission terminal 3T to the reception terminal 3R via the second duplexer 7B is called the second path RT2. The branch point where the path starting from the transmission terminal 3T branches to the first transmission filter 5TA and the second reception filter 5RB is called the first branch point 19T. The branch point where the path starting from the reception terminal 3R branches to the first reception filter 5RA and the second transmission filter 5TB is called the second branch point 19R.

[0049] In addition, and Figure 1 The transmitting terminal 3T and the first branch point 19T may be the same. Similarly, the receiving terminal 3R and the second branch point 19R may be the same.

[0050] (1.1. Filter)

[0051] For example, as described above, the filter 5 is a bandpass filter that allows a signal of a specified passband (transmission band or reception band) to pass. The passband (center frequency and bandwidth) is arbitrary. For example, the passband may be within the range of 300MHz to 10GHz. In addition, the passband may be a passband that complies with a specified standard. The passband may correspond to a passband specified by the standard, or may include more than two passbands specified by the standard. Both the transmission band and the reception band may be located on the high frequency side.

[0052] In the example shown in the figure, the filter 5 is input with an unbalanced signal and outputs an unbalanced signal. The unbalanced signal may be, for example, a signal whose signal level changes relative to a reference potential. However, the filter 5 may also be a filter that inputs a balanced signal and / or outputs a balanced signal. The balanced signal may be, for example, two signals with opposite phases. When a balanced signal is used, for example, all filters 5 correspond to the input and output of the balanced signal, two terminals may be provided for each, and an element that converts the unbalanced signal and the balanced signal may be provided at an appropriate position.

[0053] For example, the second transmission filter 5TB has the same characteristics as the first transmission filter 5TA (for example, pass characteristics, delay time and / or impedance characteristics, the same below). As such a second transmission filter 5TB, for example, a filter having the same structure (construction) as the first transmission filter 5TA can be cited. However, in theory, the second transmission filter 5TB having the same characteristics as the first transmission filter 5TA can be realized by a structure different from the structure of the first transmission filter 5TA.

[0054] Even if the characteristics of the second transmission filter 5TB are the same as those of the first transmission filter 5TA, all the various characteristics may be different at various frequencies. For example, the pass characteristics within the specified comparison frequency band may be the same in the first transmission filter 5TA and the second transmission filter 5TB. The comparison frequency band may be, for example, a transmission frequency band and / or a reception frequency band, a frequency band consisting of a transmission frequency band and a reception frequency band and a frequency band therebetween (referred to as a transmission reception frequency band in this paragraph), or a frequency band having a width of 2, 3 or 5 times the width of the above-mentioned frequency band centered on the center frequency of any one of the transmission frequency band, the reception frequency band and the transmission reception frequency band. In addition, the delay time of any frequency within the comparison frequency band (for example, the center frequency of the comparison frequency band) may be the same in the first transmission filter 5TA and the second transmission filter 5TB.

[0055] In addition, it should be noted that the pass characteristic is, for example, an S21 parameter when the input side of the transmission filter 5T is 1 and the output side of the transmission filter 5T is 2. In addition, the delay time is the delay of the output signal relative to the input signal. The delay time can be converted into a phase using the period (frequency) of the signal (input signal and output signal). Unless otherwise specified, in the comparison of the characteristics of the two transmission filters 5T, the characteristics of the same frequency are compared with each other. When the characteristics in the comparison frequency band are the same, the characteristics at the same frequency are the same in the entire comparison frequency band. In other viewpoints, when a graph with a horizontal axis of frequency and a vertical axis of characteristic values ​​is assumed, the lines showing the characteristics of the two transmission filters 5T are consistent. In the description of the embodiment, when the characteristics are mentioned to be the same, etc., unless otherwise specified, in addition, as long as no contradiction is generated, the term of the characteristic can be understood to refer to all or part of various electrical characteristics (such as the above-mentioned pass characteristic and delay time) Any one of them, in addition, it can also be understood to refer to any one of the characteristics in a specific frequency, a specific frequency band, and all frequencies.

[0056] Of course, although the characteristics are the same, they may not be strictly the same. The degree of the allowed difference can be reasonably judged according to the specifications required for the duplexer 1, etc. For example, as mentioned above, when the pass characteristics in the comparison frequency band are the same in the two transmission filters 5T, within the same range, a mode that produces a difference of less than 5dB between the pass characteristics of the two transmission filters 5T in a part or all of the above-mentioned comparison frequency band can be included. In addition, for example, as mentioned above, when the delay time at any one frequency in the comparison frequency band is the same in the two transmission filters 5T, within the same range, a mode that produces a difference of less than 5° in phase conversion between the two can be included.

[0057] Different from the above description, the characteristics of the second transmission filter 5TB may be different from the characteristics of the first transmission filter 5TA. This is because, assuming that the leakage signal and the cancellation signal are ideally in anti-phase, as long as the intensity of the cancellation signal (not 0) is less than twice the intensity of the leakage signal, the difference between the intensities of the two (the intensity of the signal after cancellation) will become somewhat smaller relative to the intensity of the leakage signal.

[0058] In the description of the characteristics of the second transmit filter 5TB in comparison with the characteristics of the above-mentioned first transmit filter 5TA, the term first transmit filter 5TA can be replaced by the term first receive filter 5RA, the term second transmit filter 5TB can be replaced by the term second receive filter 5RB, and so on, and can be referred to in the characteristics of the second receive filter 5RB.

[0059] The characteristics of the transmission filter 5T may be the same or different when a signal is input from a side where an input signal is assumed (referred to as the "imagined input side". Not limited to the actual input signal side) and when a signal is input from a side where an output signal is assumed (referred to as the "imagined output side". Not limited to the actual output signal side). In the latter case, the characteristics of the two transmission filters 5T may be the same when a signal is input from the imaginary input side, for example. In addition, the characteristics of the two transmission filters 5T may also be the same when a signal is input from the imaginary output side, for example. Although the transmission filter 5T is described, the same is true for the reception filter 5R.

[0060] In the two transmission filters 5T, the characteristics when the signal is input to the assumed input side and the characteristics when the signal is input to the assumed output side are different, and in addition, when the characteristics when the signal is input from the assumed input side are the same in the two transmission filters 5T, for example, the assumed input side of the first transmission filter 5TA can be connected to the transmission terminal 3T side, and the assumed input side of the second transmission filter 5TB can also be connected to the transmission terminal 3T side (node ​​17 side). Thus, the signal from the transmission terminal 3T passes through any one of the two transmission filters 5T from the assumed input side.

[0061] Similarly, in the two reception filters 5R, the characteristics when the signal is input to the assumed input side and the characteristics when the signal is input to the assumed output side are different, and in addition, when the characteristics when the signal is input from the assumed input side are the same in the two reception filters 5R, and the characteristics when the signal is input from the assumed output side are the same in the two reception filters 5R, for example, the assumed input side of the first reception filter 5RA can be connected to the antenna terminal 3A (transmission terminal 3T in other viewpoints) side, and the assumed input side of the second reception filter 5RB can be connected to the transmission terminal 3T side. Thus, the signal from the transmission terminal 3T passes through any one of the two reception filters 5R from the assumed input side.

[0062] It should be noted that, in the case where the characteristic when a signal is input to the assumed input side and the characteristic when a signal is input to the assumed output side are the same, any one of the assumed input side and the assumed output side may be connected to the transmission terminal 3T side. In addition, according to the above description (even if the characteristic when a signal is input to the assumed input side and the characteristic when a signal is input to the assumed output side are different, the characteristics of the two transmission filters 5T (and / or the two reception filters 5R) may be different), it can be understood that in the two transmission filters 5T (and / or the two reception filters 5R), the assumed input side may not be connected to the transmission terminal 3T side as described above.

[0063] The specific structure (construction) of the filter 5 may be various structures, for example, it may be a known structure. More specifically, for example, the filter 5 may be a piezoelectric filter including a piezoelectric body, a dielectric filter using electromagnetic waves in a dielectric, an LC filter combining an inductor and a capacitor, or a combination of two or more thereof. The piezoelectric filter may be, for example, an elastic wave filter using elastic waves, or a filter not using elastic waves (for example, a filter using a piezoelectric oscillator).

[0064] As long as elastic waves are used, elastic wave filters may be of various types. For example, an elastic wave filter may be a filter that excites elastic waves by using IDT (interdigital transducer) electrodes located on the surface of a piezoelectric body, or a filter that excites elastic waves by using electrodes that face each other with a piezoelectric film sandwiched therebetween (piezoelectric thin film resonator). In addition, for example, an elastic wave filter may be a ladder filter in which a plurality of elastic wave resonators are connected in a ladder shape, or a multi-mode filter (including a dual-mode filter) in which a plurality of IDT electrodes are arranged in the propagation direction of the elastic wave, or a transverse filter that receives and transmits elastic waves between two IDT electrodes.

[0065] The elastic wave may be, for example, a SAW (Surface Acoustic Wave), a BAW (Bulk Acoustic Wave), a boundary elastic wave, or a plate wave. However, these elastic waves cannot necessarily be clearly distinguished.

[0066] (1.2. Phase shifter)

[0067] The structure of the phase shifter can be various structures, for example, it can be the same as a known structure. For example, the phase shifter can be a distributed parameter type phase shifter or a lumped parameter type phase shifter. A distributed parameter type phase shifter is, for example, a transmission line with a length of λ / 2. λ is the wavelength of the signal. The frequency of the signal when calculating the wavelength λ can be, for example, the same as the frequency for comparing the above-mentioned delay time. In more detail, for example, the frequency of the wavelength λ can be any frequency included in the frequency band between the transmission band and the reception band (for example, the center frequency of the transmission band, the center frequency of the reception band, or the center frequency of the frequency band between the above-mentioned frequency bands). In addition, the wavelength λ is the length of the signal when it propagates in the transmission line (phase shifter), and the dielectric constant and permeability of the transmission line (a broad concept including the surrounding dielectric) will have an impact.

[0068] The phase shifter 9 can be used as long as it can convert the difference between the delay time of the first path RT1 and the delay time of the second path RT2 into 180° by phase conversion. In other words, the phase shifter 9 can be used as long as it can make the output signals of the two paths in anti-phase, wherein the output signals of the two paths are based on signals that are the same input signal relative to the first path RT and the second path RT2. As a result, the leakage signal and the cancellation signal can be made anti-phase to each other so that at least a part of each other is canceled out. In addition, since the first path RT1 and the second path RT2 are common to each other at the side closer to the transmitting terminal 3T than the first branch point 19T and at the side closer to the receiving terminal 3R than the second branch point 19R, the above description can be referred to the delay time of two paths parallel to each other from the first branch point 19T to the second branch point 19R.

[0069] As can be understood from the above, the position of the phase shifter 9 is not limited to the position shown in the figure. For example, in a manner in which the phase shifter 9 shifts the phase by 180°, the phase shifter 9 can be located at any one of the following four positions. Between the first branch point 19T and the first transmit filter 5TA. Between the first branch point 19T and the second receive filter 5RB. Between the second branch point 19R and the first receive filter 5RA. Between the second branch point 19R and the second transmit filter 5TB (illustrated example).

[0070] As shown in the above example, the setting position of part or all of the phase shifter 9 can be summarized as: the side closer to the transmission terminal 3T (the first branch point 19T in other viewpoints) relative to the first transmission filter 5TA and the second reception filter 5RB, and the side closer to the reception terminal 3R (the second branch point 19R in other viewpoints) relative to the first reception filter 5RA and the second transmission filter 5TB. Unlike the description of the embodiment, part or all of the phase shifter 9 can be located between the first transmission filter 5TA and the first reception filter 5RA (in the first duplexer 7A in other viewpoints), or between the second transmission filter 5TB and the second reception filter 5RB (in the second duplexer 7B in other viewpoints). However, as in the embodiment, when the phase shifter 9 is set outside the duplexer 7, the characteristics of the duplexer 1 can be improved.

[0071] Of course, even if the phase shifter 9 performs a 180° phase shift (or phase reversal), the phase difference may not be strictly 180°. The degree of the allowable error can be reasonably determined based on the specifications required by the duplexer 1. For example, a phase difference of 180° (phase reversal) includes a phase difference of 180°±5°. The difference between the delay time of the first path RT1 and the delay time of the second path RT2 is converted into a phase value, which is not only 180°, but also 360°×n+180°. Among them, n is an integer greater than 1 and relatively small. The upper limit of n can be reasonably set based on the specifications required by the duplexer 1, for example, it can be 1 or 2, or it can be 5.

[0072] (1.3.Resistor element)

[0073] The resistor element 11 has a predetermined resistance value, and as described above, the resistor element 11 connects the node 17 and the reference potential section 13. The resistance value of the resistor element 11 can be set to be equal to the absolute value of the characteristic impedance of the antenna terminal 3A, for example. Generally, the absolute value of the characteristic impedance of the antenna terminal 3A is set to be approximately 50Ω in a desired frequency band, and therefore, the resistance value of the resistor element 11 can be set to 50Ω.

[0074] The resistor element 11 may be a chip-type electronic component or a conductor pattern formed on a circuit board. In addition, the circuit board on which the chip-type electronic component is mounted or the circuit board on which the conductor pattern is formed may be, for example, a substrate included in the duplexer 1 or a circuit board (not shown) on which the duplexer 1 is mounted. Examples of the circuit board included in the duplexer 1 include: Figure 2 The multilayer substrate 21A or Figure 4 The first and second configuration examples described below are examples in which the resistor element 11 is provided outside the multilayer substrates 21A and 21B (outside the duplexer 1). The resistor element 11 may be included in Figure 2 Chip 23 or Figure 4 The chip 25. More specifically, for example, the resistor element 11 may be formed of a conductor formed on the upper surface of the piezoelectric substrate 35 described later.

[0075] In addition, as long as it is assumed that a reference potential is given, the reference potential portion 13 connected to the resistor element 11 (or the parallel resonator 33P described later, etc.) can be set as various conductors. In addition, unless otherwise specified or unless there is a contradiction, the term reference potential portion can refer to all of the above-mentioned various conductors or to various conductors.

[0076] (1.4. First duplexer and second duplexer)

[0077] By analogy from the above description of the filter 5, the first duplexer 7A and the second duplexer 7B may have the same characteristics. As an example of this, the first duplexer 7A and the second duplexer 7B may have the same structure. In addition, by analogy from the above description of the filter 5, as long as the intensity of the cancellation signal and the leakage signal after cancellation is less than the intensity of the leakage signal, the characteristics of the first duplexer 7A and the second duplexer 7B may be different.

[0078] The matters that the characteristics of the first duplexer 7A and the second duplexer 7B are the same can be referred to the description of the matters that the characteristics of the two filters 5 are the same. For example, the two duplexers 7 do not need to have all the same characteristics in all frequency bands, and the pass characteristics in the comparison frequency band can be the same, and the delay time in any frequency of the comparison frequency band can be the same. In addition, although the characteristics are the same, they may not be strictly the same. For example, the difference in the pass characteristics of less than 5 dB and the difference in the delay time of less than 5° in phase conversion can be included in the same range.

[0079] When the characteristics of the two duplexers 7 are the same, first, the characteristics related to the signal passing through each filter 5 in each duplexer 7 can be compared. For example, the characteristics when the signal flows from the transmission terminal 3T side through the first transmission filter 5TA to the antenna terminal 3A side, and the characteristics when the signal flows from the reception terminal 3R side through the second transmission filter 5TB to the node 17 side can be compared. Similarly, the characteristics when the signal flows from the antenna terminal 3A side through the first reception filter 5RA to the reception terminal 3R side, and the characteristics when the signal flows from the node 17 side through the second reception filter 5RB to the transmission terminal 3T can be compared. The characteristics when the signal flows through each filter 5 in other directions can also be compared.

[0080] In addition to the above or as a substitute, the characteristics of the combination of the two filters can be compared. For example, the characteristics when the signal flows through the first transmission filter 5TA and the first receiving filter 5RA in sequence, and the characteristics when the signal flows through the second transmission filter 5TB and the second receiving filter 5RB in sequence can be compared. And, the characteristics at this time can be the same in the two duplexers 7. In addition, since the leakage signal and the elimination signal flow from the transmission terminal 3T to the receiving terminal 3R, therefore, the characteristics when the signal flows through the first transmission filter 5TA and the first receiving filter 5RA in sequence, and the characteristics when the signal flows through the second receiving filter 5RB and the second transmission filter 5TB in sequence can be compared. And, the characteristics at this time can be the same in the two duplexers 7.

[0081] The characteristics when the signal flows through the first transmission filter 5TA and the first reception filter 5RA in sequence may be the same as or different from the characteristics when the signal flows through the opposite direction. The same applies to the second transmission filter 5TB and the second reception filter 5RB.

[0082] According to the above description of the filter 5, it can be understood that the connection relationship between the assumed input side and the assumed output side of the first transmitting filter 5TA and the assumed input side and the assumed output side of the first receiving filter 5RA, and the positional relationship between the assumed input side and the assumed output side of the second transmitting filter 5TB and the assumed input side and the assumed output side of the second receiving filter 5RB may be the same or different.

[0083] For example, as illustrated in the above description of the filter 5, when the assumed input sides of the four filters 5 are all set to the transmission terminal 3T side, in the first duplexer 7A, the assumed output side of the first transmission filter 5TA is connected to the assumed input side of the first reception filter 5RA, and on the other hand, in the second duplexer 7B, the assumed input side of the second transmission filter 5TB is connected to the assumed output side of the second reception filter 5RB. That is, the connection relationship between the assumed input side and the assumed output side of the transmission filter 5T and the assumed input side and the assumed output side of the reception filter 5R is different between the first duplexer 7A and the second duplexer 7B. In addition, this connection relationship is also mentioned in the description of the first construction example.

[0084] In addition, for example, as a mode in which the connection relationship between the two is the same, the following mode can be cited, that is, in the first duplexer 7A, the assumed output side of the first transmission filter 5TA is connected to the assumed input side of the first reception filter 5RA, and on the other hand, in the second duplexer 7B, the assumed output side of the second transmission filter 5TB is connected to the assumed input side of the second reception filter 5RB. In addition, this connection relationship is also mentioned in the description of the second construction example.

[0085] (2. Specific example of the structure of a duplexer)

[0086] The duplexer 1 may be configured as a chip-type electronic component having only the function of a duplexer, for example. However, the duplexer 1 may be integrally and inseparably combined with a component having a function different from that of the duplexer, and the electronic component including the duplexer 1 may not be a chip-type component. For example, although not specifically shown in the figure, in a module substrate having a circuit board, an IC (integrated circuit) mounted or built into the circuit board, an antenna mounted or built into the circuit board, and the duplexer 1, a part or all of the duplexer 1 may also be included in the circuit board.

[0087] In the first and second structural examples described below, a chip-type electronic component having only the function of a duplexer is exemplified as the duplexer 1 .

[0088] (2.1. First construction example)

[0089] (2.1.1. Overall structure of the duplexer)

[0090] Figure 2 1 is a schematic perspective view showing a main part of the structure of a duplexer 1A which is an example of the duplexer 1 .

[0091] In this figure, the chip 23 is indicated by a dotted line, and the upper surface of the multilayer substrate 21A is visualized. In addition, the wiring inside the multilayer substrate 21A is schematically shown. The arbitrary direction of the duplexer 1A can be upward or downward, but Figure 2 In the description of the invention, for convenience, an orthogonal coordinate system xyz is defined, the +z side is regarded as the upper side, and sometimes the terms upper surface or lower surface are used (the second structural example described later involves Figure 4 Same here).

[0092] The duplexer 1A is configured as a surface mounted chip-type electronic component, for example. For example, the duplexer 1A has a plurality of terminals 3 (external terminals) located on the lower surface and composed of a layered conductor. The plurality of terminals 3 are bonded to the pads located on the upper surface of a circuit board (not shown) in a state of being opposite to each other, through a conductive bonding material located therebetween. The conductive bonding material is a protrusion in other viewpoints, and its material is, for example, solder (the same below). The general shape and size of the duplexer 1A are arbitrary. For example, the duplexer 1A as a whole is roughly a thin rectangular parallelepiped.

[0093] As described above, the plurality of terminals 3 include the antenna terminal 3A, the transmission terminal 3T, and the reception terminal 3R. In addition, in the illustrated example, the plurality of terminals 3 include a resistance terminal 3B connected to the resistance element 11. The resistance element 11 is provided on a circuit board (not shown) on which the duplexer 1A is mounted. Although not particularly illustrated, the plurality of terminals 3 may include a reference potential terminal to which a reference potential is given from the circuit board. The number, position, shape, size, etc. of the plurality of terminals 3 may be appropriately set.

[0094] In addition, the duplexer 1A as a chip-type electronic component is not limited to a duplexer having layered terminals 3 on the lower surface. For example, the layered terminals 3 located on the upper surface may be connected to a circuit board (not shown) via bonding wires. In addition, for example, the pin-shaped terminals 3 may be bonded to the multilayer substrate 21A.

[0095] As described above, the duplexer 1A, for example, has a multilayer substrate 21A and one or more chips 23 (four in the illustrated example) mounted on the multilayer substrate 21A. In addition, in the illustrated example, one chip 23 has one filter 5, and the duplexer 1A has four chips 23 corresponding to the four filters 5. The positions of the four chips 23 on the upper surface of the multilayer substrate 21A and the relative positions of the four chips 23 are arbitrary. The duplexer 1A may also have components other than those shown in the illustration. As such components, for example, a sealing material or a cover portion that covers the upper surface of the multilayer substrate 21A from above the chip 23 can be cited.

[0096] (2.1.2. Multilayer substrate)

[0097] The basic structure and material of the multilayer substrate 21A (circuit board) (except for the pattern and size of the specific conductors used to form the duplexer 1A) can be the same as the structures and materials of various known printed circuit boards. For example, the multilayer substrate 21A can be an LTCC (Low Temperature Co-fi red Ceramics) substrate, an HTCC (High Temperature Co-fi red Ceramic) substrate, an IPD (Integrated Passive Device) substrate, or an organic substrate.

[0098] Examples of LTCC substrates include substrates that can be fired at low temperatures (e.g., about 900°C) by adding glass-based materials to alumina. In LTCC substrates, for example, Cu or Ag can be used as a conductive material. Examples of HTCC substrates include substrates that use ceramics with alumina or aluminum nitride as a main component. In HTCC substrates, for example, tungsten or molybdenum can be used as a conductive material. Examples of IPD substrates include substrates in which passive components are formed on a Si substrate. Examples of organic substrates include substrates in which a prepreg impregnated with a resin is stacked on a base material made of glass or the like.

[0099] The multilayer substrate 21A has an insulating base 22 and a conductor 27 located inside and / or on the surface of the base 22. As can be understood from the description in the previous paragraph, the materials of the base 22 and the conductor 27 are arbitrary. The base 22 may, for example, have a plurality of insulating layers 22a stacked on each other. The shape and size of the base 22 are arbitrary. In the example shown in the figure, the base 22 is a thin rectangular parallelepiped. The conductor 27 may, for example, have a conductor layer located on the upper surface or lower surface (main surface) of the insulating layer 22a, and a via conductor penetrating the insulating layer 22a. The number, position, shape, and size of the conductor layer and the via conductor can be appropriately set according to the functions required by the multilayer substrate 21A.

[0100] exist Figure 2 In the figure, as an example of the conductor 27 (conductor layer), the above-mentioned multiple (part of) terminals 3 and multiple (part of) pads 29 (29I and 29O) for mounting the chip 23 on the multilayer substrate 21A are illustrated. As described later, the multiple terminals 3 and the multiple pads 29 are connected to each other via the conductor 27 of the multilayer substrate 21A. Thus, the filter 5 included in the chip 23 can filter the signal input from any terminal 3 and output it to other terminals 3.

[0101] For example, a plurality of pads 29 overlap on the upper surface of the base 22. For example, the plurality of pads 29 are bonded to the layered external terminals (not shown) located on the lower surface of the chip 23 via a conductive bonding material (not shown) therebetween in a state of facing each other. Thus, the chip 23 is surface mounted on the multilayer substrate 21A. In addition, unlike the example shown in the figure, the pads 29 may also be electrically connected to the external terminals provided on the upper surface of the chip 23 via bonding wires.

[0102] The number, position, shape, and size of the plurality of pads 29 may be determined based on the number of at least one chip 23 and the terminals ( Figure 2 The number, position, shape, and size of the plurality of pads 29 (not shown) are appropriately set. Usually, at least four pads 29 are provided so as to support at least four corners of each chip 23. In addition, the plurality of pads 29 include, for example, pads for inputting signals to the chip 23 (filter 5), pads for outputting signals from the chip 23, and pads for providing a reference potential to the chip 23.

[0103] (2.1.3. Chip)

[0104] As described above, the specific structure of the filter 5 included in each chip 23 can be variously configured. Here, a ladder filter in which elastic wave resonators using IDT electrodes are connected in a ladder shape is exemplified as the filter 5 .

[0105] Figure 3 1 is a schematic plan view of the chip 23 as viewed from the multi-layer substrate 21A side.

[0106] Chip 23 can be up or down in any direction, but Figure 3In the description of the invention, for convenience, an orthogonal coordinate system consisting of the D1 axis, the D2 axis, and the D3 axis is given in the drawings, and the +D3 side is regarded as the upper side, and sometimes the terms such as the upper surface or the lower surface are used. In addition, the D1 axis is defined as being parallel to the propagation direction of the elastic wave propagating along the upper surface of the piezoelectric body described later, the D2 axis is defined as being parallel to the upper surface of the piezoelectric body and being orthogonal to the D1 axis, and the D3 axis is defined as being orthogonal to the upper surface of the piezoelectric body.

[0107] The filter 5 outputs a signal having a frequency within a predetermined passband among the signals input to the input terminal 31I to the output terminal 31O. The signal having a frequency outside the passband is released to the GND terminal 31G connected to the reference potential portion. In addition, these terminals are sometimes collectively referred to as terminals 31. The number of terminals 31, the position on the upper surface of the chip 23, the shape and size, etc. are arbitrary.

[0108] The filter 5 is formed by connecting a plurality of resonators 33 (33S and 33P) in a ladder shape. That is, the filter 5 has a plurality of (one or more) series resonators 33S and a plurality of (one or more) parallel resonators 33P (parallel arms), wherein the series resonator 33S is connected in series between the input terminal 31I and the output terminal 31O, and the parallel resonator 33P is connected in parallel between the series line (series arm) of the series resonator 33S and the GND terminal 31G (reference potential portion). Each parallel resonator 33P is connected to the input terminal 31I side or the output terminal 31O side with respect to any series resonator 33S. That is, the plurality of parallel resonators 33P connect a plurality of electrically different positions in the series arm to the GND terminal 31G. The number of series resonators 33S and the number of parallel resonators 33P, and the positions of these resonators 33 on the upper surface of the chip 23 are arbitrary.

[0109] Each resonator 33 is composed of a so-called single-port elastic wave resonator. The resonator 33 includes, for example, a piezoelectric substrate 35 (at least a portion of the upper surface side thereof), an IDT electrode 37 (an excitation electrode in a higher concept) located on the upper surface of the piezoelectric substrate 35, and a pair of reflectors 39 located on both sides of the IDT electrode 37. In addition, the piezoelectric substrate 35 is shared by a plurality of resonators 33. In the description of the embodiment, in order to distinguish between a plurality of resonators 33 sharing the same piezoelectric substrate 35, for convenience, it is sometimes expressed that, for example, a combination of an IDT electrode 37 and a pair of reflectors 39 (electrode portions of the resonator 33) is a resonator 33 (for example, the resonator 33 does not include the piezoelectric substrate 35).

[0110] The piezoelectric substrate 35 has piezoelectricity at least in the region where the resonator 33 is provided on the upper surface thereof. As such a piezoelectric substrate 35, for example, a substrate whose entire substrate is composed of a piezoelectric body can be cited. In addition, for example, a so-called bonded substrate can be cited. The bonded substrate includes: a substrate (piezoelectric substrate) composed of a piezoelectric body and a supporting substrate directly bonded to the lower surface of the piezoelectric substrate with or without an adhesive. The supporting substrate may have a cavity below the piezoelectric substrate or may not have a cavity. In addition, as the piezoelectric substrate 35, for example, a supporting substrate and a substrate having a film (piezoelectric film) composed of a piezoelectric body or a plurality of films including a piezoelectric film formed on a part or the entire surface of the upper surface of the supporting substrate can be cited. The material of the piezoelectric body can be a known material, for example, lithium tantalate (LiTaO3), lithium niobate (LiNbO3) and crystal (SiO2).

[0111] The IDT electrode 37 and the reflector 39 are composed of a layered conductor arranged on the piezoelectric substrate 35. The IDT electrode 37 has a pair of comb-tooth electrodes (illustration marks omitted). The pair of comb-tooth electrodes are configured in a manner that meshes with each other. A pair of reflectors 39 are located on both sides of the IDT electrode 37 in the propagation direction of the elastic wave. The reflectors 39 are formed in a grid shape, for example. Each reflector 39 can be in an electrically floating state, or can be given a reference potential. The specific shape, size, material, etc. of the IDT electrode 37 and the reflector 39 can be various, for example, the same as the well-known ones.

[0112] When a voltage is applied to the IDT electrode 37, an elastic wave propagating in the D1 direction is excited. In addition, the elastic wave propagating in the D1 direction is converted into an electrical signal by the IDT electrode 37. At this time, the function as a resonator is realized by the effect of increasing the amplitude of the elastic wave of a specific frequency corresponding to the spacing of the plurality of electrode fingers (a plurality of teeth) of the IDT electrode 37. The pair of reflectors 39 helps to lock the elastic wave.

[0113] Although not specifically shown in the figure, the impedance of each resonator 33 is a minimum value at the resonant frequency, and the impedance is a maximum value at the anti-resonant frequency. In the plurality of series resonators 33S, the resonant frequencies are set to be substantially the same as each other, and the anti-resonant frequencies are set to be substantially the same as each other. In addition, in the plurality of parallel resonators 33P, the resonant frequencies are set to be substantially the same as each other, and the anti-resonant frequencies are set to be substantially the same as each other. The resonant frequency of the series resonator 33S and the anti-resonant frequency of the parallel resonator 33P are set to be substantially the same.

[0114] By setting the resonant frequency and anti-resonant frequency as described above, a bandpass filter can be realized. The center frequency of the passband is substantially the same as the resonant frequency of the series resonator 33S and the anti-resonant frequency of the parallel resonator 33P. The width of the passband is slightly narrower than the width from the resonant frequency of the parallel resonator 33P to the anti-resonant frequency of the series resonator 33S.

[0115] The chip 23 may be composed of a piezoelectric substrate 35 for most of the chip 23. Specifically, for example, the chip 23 may include a piezoelectric substrate 35 and a relatively thin layer overlapping the surface of the piezoelectric substrate 35. As the relatively thin layer, for example, there can be listed: a conductive layer (IDT electrode 37, etc.) overlapping the upper surface of the piezoelectric substrate 35, and an insulating protective film covering most of the upper surface of the piezoelectric substrate 35 (for example, the area excluding the terminal 31) from above the conductive layer. In addition, the chip 23 may also have a layer covering the side or lower surface of the piezoelectric substrate 35.

[0116] The chip 23 of the structure described in the previous paragraph is, for example, such that the surface on the +D3 side is aligned with the upper surface ( Figure 2 The chip 23 is mounted on the multilayer substrate 21A with its upper surface facing the chip 23. At this time, the terminal 31 of the chip 23 and the pad 29 of the multilayer substrate 21A face each other and are bonded with a conductive bonding material (not shown) therebetween. Between the chip 23 and the multilayer substrate 21 (on the resonator 33 in other viewpoints), a space having a height substantially equivalent to the thickness of the bonding material bonding the terminal 31 and the pad 29 is formed.

[0117] In addition, for example, although not specifically shown in the figure, in addition to the above structure, the chip 23 may also have a box-shaped insulating cover covering the upper surface of the piezoelectric substrate 35. The cover forms a space above the resonator 33. The chip 23 has, for example, a columnar terminal located above the terminal 31 and penetrating the cover. The chip 23 is a structure in which the surface of the cover on the +D3 side and the upper surface ( Figure 2 At this time, the upper surface of the columnar terminal and the pad 29 of the multilayer substrate 21A face each other and are bonded with a conductive bonding material (not shown) therebetween.

[0118] (2.1.4. Construction example related to connection)

[0119] As described so far, in the top view (when observing the upper surface of the multilayer substrate 21A), the relative positions of the four filters 5 are arbitrary, and the positions of the terminals 31 (31I, 31O, and 31G) of each filter 5 are also arbitrary, and the positions of the terminals 3 (3A, 3B, 3T, and 3R and the terminal 3 for reference potential not shown) of the multilayer substrate 21A are also arbitrary. Figure 1 The circuit structure described above and the specific structure of the conductor 27 of the multilayer substrate 21A connecting the plurality of terminals 31 and the plurality of terminals 3 are also arbitrary. Figure 2 In FIG. 1 , it is shown that in a mode where the two transmission filters 5T have the same structure and the two reception filters 5R have the same structure, the input side of each of the two transmission filters 5T is connected to the transmission terminal 3T side ( Figure 1 The left side in the figure), and the assumed input side of each of the two reception filters 5R is connected to the transmission terminal 3T side ( Figure 1 left side of the figure).

[0120] exist Figure 2 In the example, the terminal 31 ( Figure 3 ) is given a reference numeral 29I. In addition, a pad 29 connected to a terminal 31 on the assumed output side of the filter 5 is given a reference numeral 29O. Figure 2 In FIG. 5 , the four filters 5 are arranged clockwise in the order of the first transmission filter 5TA, the first reception filter 5RA, the second transmission filter 5TB, and the second reception filter 5RB. In addition, this arrangement can be understood as Figure 1 The four filters 5 are arranged the same on paper (the +y side is understood as along Figure 1 on the top of the paper).

[0121] For any filter 5, the pads 29I and 29O are located at a pair of diagonal corners of the filter 5. For any transmission filter 5T, the pad 29I is located at the -x side and the -y side, and the pad 29O is located at the +x side and the +y side. In addition, for any reception filter 5R, the pad 29I is located at the -x side and the +y side, and the pad 29O is located at the +x side and the -y side.

[0122] In the above arrangement, the two pads 29 connected to each other are located at two adjacent corners of the two chips including the two pads 29. As a result, the structure of the wiring (conductor 27) of the multilayer substrate 21A connecting the two pads 29 can be simplified. In addition, as described above, Figure 2 The wiring shown is schematic. However, Figure 2It is conceivable that the wiring may include, for example, two via conductors of substantially the same shape and size extending downward from two pads 29 and a conductor layer (conductor pattern) connecting the two via conductors. The conductor pattern may extend linearly with a constant width, for example.

[0123] (2.1.5. Configuration example of phase shifter)

[0124] exist Figure 2 In the embodiment, the phase shifter 9 is composed of a transmission line having a length of λ / 2. Figure 2 In FIG. 1 , for convenience, the transmission line constituting the phase shifter 9 is represented by a thick line to distinguish it from other wirings. However, the cross-sectional area of ​​the transmission line constituting the phase shifter 9 is arbitrary, for example, the cross-sectional area of ​​the transmission line can be the same as the cross-sectional area of ​​other wirings. Figure 2 middle, and Figure 1 Similarly, the embodiment in which the phase shifter 9 is located between the second transmission filter 5TB and the second branch point 19R is exemplified. Unless otherwise specified, the description herein may be based on this embodiment.

[0125] like Figure 2 As schematically shown in the figure, the wiring connecting the first transmit filter 5TA and the first receive filter 5RA, and the wiring connecting the second transmit filter 5TB and the second receive filter 5RB can be set to the same length as each other. In addition, the wiring connecting the first transmit filter 5TA and the first branch point 19T, and the wiring connecting the second receive filter 5RB and the first branch point 19T can be set to the same length as each other. On the other hand, the wiring connecting the second transmit filter 5TB and the second branch point 19R (including the wiring of the phase shifter 9) can be longer than the wiring connecting the first receive filter 5RA and the second branch point 19R by λ / 2. Thus, a phase difference of 180° can be achieved. The λ / 2 transmission line can also be the same when it is set in the other three positions.

[0126] exist Figure 2 In FIG. 1 , the λ / 2 transmission line is shown as a conductor layer (conductor pattern) extending linearly with a constant width. The λ / 2 transmission line may actually have such a structure or another structure. For example, the λ / 2 transmission line may include a via conductor or a conductor pattern extending by appropriately bending.

[0127] (2.2. Second construction example)

[0128] In the description of the second configuration example, basically only the differences from the first configuration example are described. For features not specifically mentioned, they may be the same as the first configuration example or may be inferred from the first configuration example.

[0129] Figure 4 1 is a schematic perspective view showing the main part of the structure of a duplexer 1B, which is an example of the duplexer 1, and corresponds to the first structural example. Figure 2 .

[0130] In summary, the duplexer 1B of the second configuration example is different from the duplexer 1A of the first configuration example in that each filter 5 is not provided as a chip 23 but each duplexer 7 is provided as a chip 25. Specifically, it is as follows.

[0131] The duplexer 1B includes a multilayer substrate 21B and two chips 25 mounted on the multilayer substrate 21B. Like the multilayer substrate 21A of the first structural example, the multilayer substrate 21B includes a plurality of terminals 3 located on the lower surface. The plurality of terminals 3, for example, include an antenna terminal 3A, a transmission terminal 3T, a reception terminal 3R, a resistor terminal 3B, and a reference potential terminal (not shown), like the plurality of terminals 3 of the first structural example.

[0132] Like the multilayer substrate 21A of the first construction example, the multilayer substrate 21B has a plurality of pads 29 on which the chip 25 is mounted. However, due to the difference between the chip 25 and the chip 23 of the first construction example, the number, position, and function of the plurality of pads 29 are different from those of the plurality of pads 29 of the first construction example. The plurality of pads 29 of the second construction example, for example, have at least four pads 29 (only three are shown) connected to the antenna terminal 3A (or the resistor terminal 3B), the transmission terminal 3T, the reception terminal 3R, and the terminal 3 for the reference potential (not shown) for each chip 25. The plurality of pads 29 can be provided, for example, at four corners capable of supporting the chip 25.

[0133] Figure 5 2 is a schematic plan view of the chip 25 as viewed from the multilayer substrate 21B side. Figure 3 However, for convenience, Figure 5 Compared to Figure 3 , is schematically represented. Specifically, Figure 5 In FIG. 1 , the IDT electrode 37 and the reflector 39 are represented by rectangles.

[0134] The specific structure of the filter 5 included in the duplexer 7 can be various structures as described above. Here, the ladder filter same as the first construction example is taken as an example. The duplexer 7 has a transmission filter 5T and a reception filter 5R. Except that the piezoelectric substrate 35 is shared by the transmission filter 5T and the reception filter 5R, these filters 5 are basically the same as the filter 5 of the chip 23 of the first construction example.

[0135] For convenience, imagine Figure 5The first duplexer 7A of the two duplexers 7 is shown. At this time, the chip 25 has a terminal 31A connected to the antenna terminal 3A, a terminal 31T connected to the transmission terminal 3T, a terminal 31R connected to the reception terminal 3R, and a GND terminal 31G connected to the terminal 3 (not shown) for the reference potential. The plurality of series resonators 33S of the transmission filter 5T are connected in series between the terminal 31A and the terminal 31T. The plurality of series resonators 33S of the reception filter 5R are connected in series between the terminal 31A and the terminal 31R. The positions of the various terminals and the positions of the various resonators 33 on the upper surface of the chip 25 are arbitrary.

[0136] return Figure 4 In a top view (when observing the upper surface of the multilayer substrate 21B), the relative positions of the two duplexers 7 (chips 25) are arbitrary. In addition, the positions of the terminals 31 in each chip 25 are also arbitrary, and the positions of the terminals 3 in the multilayer substrate 21B are also arbitrary. Figure 1 The circuit structure described above and the specific structure of the conductor 27 of the multilayer substrate 21B connecting the plurality of terminals 31 and the plurality of terminals 3 are also arbitrary. Figure 4 , a connection example in which two duplexers 7 (chips 25) have the same structure is shown.

[0137] exist Figure 4 In the example, terminals 31A, 31T and 31R ( Figure 5 ) are given reference numerals 29A, 29T, and 29R. In the first duplexer 7A, as described above, the terminals 31A, 31T, and 31R are terminals connected to the antenna terminal 3A, the transmission terminal 3T, and the reception terminal 3R. The terminals 31A, 31T, and 31R in the second duplexer 7B are terminals connected to the antenna terminal 3A, the transmission terminal 3T, and the reception terminal 3R when the second duplexer 7B is used as the first duplexer 7A.

[0138] It can be understood from the positions of the pads 29T and 29R that in each chip 25, the terminals 31T and 31R are arranged along one side of the chip 25. In a top view, the two chips 25 are arranged in such a way that the sides where the terminals 31T and 31R are arranged are opposite to each other. In other viewpoints, the two chips 25 are arranged in opposite directions to each other in a top view. The terminals 31A of the two chips 25 (refer to the position of the pads 29A) are arranged at a 180° rotationally symmetrical position relative to the center between the two chips 25.

[0139] In the above-mentioned arrangement, the two pads 29 connected to each other are adjacent to each other. That is, the pad 29T associated with the first duplexer 7A is adjacent to the pad 29R associated with the second duplexer 7B, and the pad 29R associated with the first duplexer 7A is adjacent to the pad 29T associated with the second duplexer 7B. As a result, the structure of the wiring (conductor 27) of the multilayer substrate 21B connecting the two pads 29 can be simplified. In addition, Figure 4 The wiring shown is schematic. However, the wiring connecting the pads 29 to each other is based on Figure 4 For example, it is conceivable that two via conductors of substantially the same shape and size extending downward from two pads 29 and a conductor layer (conductor pattern) connecting the two via conductors to each other may be included.

[0140] In addition, if Figure 4 As shown, in a top view, the arrangement of making the second duplexer 7B inverted relative to the first duplexer 7A and adjacent to each other can also be applied to the arrangement of the pads 29A, 29T and 29R different from the example shown in the figure. For example, the two pads 29 connected to each other may not be adjacent to each other. In this case, since the positions of the two pads 29 connected to each other in the x direction are consistent, the wiring structure of the multilayer substrate 21B can be simplified.

[0141] exist Figure 4 In the embodiment, as in the first configuration example, the phase shifter 9 is composed of a λ / 2 transmission line located between the second branch point 19R and the second transmission filter 5TB. Specifically, for example, Figure 4 As schematically shown in FIG. 1 , the wiring connecting the pad 29T associated with the first duplexer 7A (the pad 29 connected to the first transmission filter 5TA) and the first branch point 19T, and the wiring connecting the pad 29R associated with the second duplexer 7B (the pad 29 connected to the second reception filter 5RB) and the first branch point 19T are set to be the same length as each other. On the other hand, the wiring connecting the pad 29T associated with the second duplexer 7B (the pad 29 connected to the second transmission filter 5TB) and the second branch point 19R can be longer by λ / 2 than the wiring connecting the pad 29R associated with the first duplexer 7A (the pad 29 connected to the first reception filter 5RA) and the second branch point 19R.

[0142] (2.3. Other construction examples)

[0143] Although the correspondence between the filter and the chip is not specifically illustrated, it can also be a method other than the first construction example and the second construction example. For example, all four filters 5 can be set on the same chip (in other viewpoints, set on the same piezoelectric substrate 35). It is also possible that one of the two duplexers 7 (for example, the first duplexer 7A) is composed of one chip 25, and the other duplexer (for example, the second duplexer 7B) is composed of two chips 23. The first transmission filter 5TA and the second transmission filter 5TB can be set on the same chip (the same piezoelectric substrate 35), and the first reception filter 5RA and the second reception filter 5RB can be set on the same chip (the same piezoelectric substrate 35).

[0144] (2.4. Node construction example)

[0145] As described above, the resistor element 11 may be included in the duplexer 1 or may not be included in the duplexer 1 (or may be external to the duplexer 1). Therefore, when considering two methods to extract features related to the connection of the resistor element 11 (in other viewpoints, when only focusing on the duplexer 1 without the resistor element 11 to determine whether the technology disclosed in the present invention is applicable), the node 17 may be focused on. The node 17 may be set in various ways corresponding to various structures of the duplexer 1.

[0146] In the first construction example, Figure 2 As shown, the node 17 is provided in the multilayer substrate 21A. Specifically, the junction of the wiring extending from the pad 29I associated with the second transmission filter 5TB and the wiring extending from the pad 29O associated with the second reception filter 5RB is set as the node 17. More specifically, although Figure 2 The wiring is schematic, but it can be understood that it represents a method of forming the node 17 by the connection part of the conductor layer and the via conductor. Different from the above, for example, the node 17 may be formed by the junction of the wiring formed by three conductor layers. In addition, for example, the wiring extending from the pad 29I related to the second transmission filter 5TB and the wiring extending from the pad 29O related to the second reception filter 5RB may each reach the resistor terminal 3B, and the resistor terminal 3B may become the node 17.

[0147] In the second construction example, it is understood that Figure 5 In the case where the chip 25 shown constitutes the second duplexer 7B, although Figure 5Although no reference numeral is given in the figure, the node 17 is provided in the chip 25. Specifically, the portion where the wiring extending from the transmission filter 5T to the terminal 31A and the wiring extending from the reception filter 5R to the terminal 31A meet is the node 17. Unlike the example shown in the figure, the wiring extending from the transmission filter 5T to the terminal 31A and the wiring extending from the reception filter 5R to the terminal 31A may each reach the terminal 31A, and the terminal 31A may become the node 17.

[0148] As described above, node 17 can be provided in various ways. Whether to provide node 17 connected to or connectable to resistor element 11 can be reasonably determined based on common technical knowledge, etc. Typically, as can be understood from the above example, node 17 is the confluence of three wirings, or a terminal where two wirings converge separately. In addition, the confluence of three wirings can be understood as a branch point. In addition, since the terminal where two wirings converge is connected to other devices (other wirings in other viewpoints), it can be understood as a branch point. Therefore, node 17 can be said to be located at a branch point. A connection object of the branch point is connected to resistor element 11, or becomes a structure (such as a terminal) that can be connected to other devices of duplexer 1.

[0149] (3. Communication device including duplexer)

[0150] Figure 6 1 is a block diagram showing the main parts of a communication device 151 as an application example of the duplexer 1. The communication device 151 includes a module 171 and a housing 173 for storing the module 171. The module 171 performs wireless communication using radio waves and includes the duplexer 1. Here, the duplexer 1 schematically shows only the first transmission filter 5TA and the first reception filter 5RA.

[0151] In the module 171, the transmission information signal TIS including the information to be transmitted is modulated and up-converted (converted into a high-frequency signal with a carrier frequency) by the RF-IC (Radio Frequency Integrated Circuit) 153 (an example of an integrated circuit element), thereby forming a transmission signal TS. The transmission signal TS is removed from the unnecessary components outside the transmission passband by the bandpass filter 155, amplified by the amplifier 157, and input to the duplexer 1 (transmission terminal 3T). Then, the duplexer 1 (first transmission filter 5TA) removes the unnecessary components outside the transmission passband from the input transmission signal TS, and outputs the removed transmission signal TS from the antenna terminal 3A to the antenna 159. The antenna 159 converts the input electrical signal (transmission signal TS) into a wireless signal (radio wave) and transmits it.

[0152] In addition, in the module 171, the wireless signal (radio wave) received by the antenna 159 is converted into an electrical signal (received signal RS) by the antenna 159 and input to the duplexer 1 (antenna terminal 3A). The duplexer 1 (first receive filter 5RA) removes unnecessary components outside the passband for reception from the input received signal RS and outputs it from the receiving terminal 3R to the amplifier 161. The output received signal RS is amplified by the amplifier 161, and unnecessary components outside the passband for reception are removed by the bandpass filter 163. Then, the received signal RS is down-converted and demodulated by the RF-IC 153, thereby forming a received information signal RIS.

[0153] In addition, the transmitted information signal TIS and the received information signal RIS can be low-frequency signals (baseband signals) containing appropriate information, such as analog sound signals or digitized sound signals. The passband of the wireless signal can be appropriately set. The modulation method can be any one of phase modulation, amplitude modulation, frequency modulation, or a combination of any two or more of them. The circuit method diagram shows a direct conversion method, but it can also be set to other appropriate methods, such as a double superheterodyne method. In addition, Figure 6 The diagram schematically shows only the main parts, and a low-pass filter, an isolator, etc. may be added at appropriate positions, and the positions of the amplifiers, etc. may be changed.

[0154] In the module 171, for example, the components from the RF-IC 153 to the antenna 159 are mounted or built into the same circuit board. Thus, the duplexer 1 and other components are combined and modularized. The duplexer 1 may be included in the communication device 151 without being modularized. In addition, the components exemplified as the components of the module 171 may be located outside the module or may not be housed in the housing 173. For example, the antenna 159 may be exposed outside the housing 173.

[0155] (4. Summary of implementation methods)

[0156] As described above, the splitter (duplexer 1) has: a first filter (first transmission filter 5TA), a second filter (first reception filter 5RA), a third filter (second transmission filter 5TB), a fourth filter (second reception filter 5RB) and a 180° phase shifter (phase shifter 9). The first transmission filter 5TA connects the common terminal (antenna terminal 3A) and the first terminal (transmission terminal 3T), and corresponds to the first passband (transmission band) (allowing the signal of the transmission band to pass). The first reception filter 5RA connects the antenna terminal 3A and the second terminal (reception terminal 3R), and corresponds to the second passband (reception band) that does not overlap with the transmission band (allowing the signal of the reception band to pass). The second transmission filter 5TB connects the node 17 located at the branch point and the reception terminal 3R, and corresponds to the transmission band. The second reception filter 5RB connects the node 17 and the transmission terminal 3T, and corresponds to the reception band. The phase shifter 9 is located closer to the transmission terminal 3T than the first transmission filter 5TA and the second reception filter 5RB, or closer to the reception terminal 3R than the first reception filter 5TB and the second transmission filter 5TB. In addition, the phase shifter 9 makes the output signals of two paths based on the same input signal in opposite phases, wherein the two paths are: a path (first path RT1) from the transmission terminal 3T via the first transmission filter 5TA and the first reception filter 5RA to the reception terminal 3R, and a path (second path RT2) from the transmission terminal 3T via the second reception filter 5RB and the second transmission filter 5TB to the reception terminal 3R.

[0157] Therefore, as described above, the leakage signal and the cancellation signal can be canceled out, thereby improving the isolation characteristics. Since the phase shifter 9 is not located between the first transmission filter 5TA and the first reception filter 5RA and between the second transmission filter 5TB and the second reception filter 5RB, for example, the possibility of generating unexpected standing waves can be reduced by the phase shifter 9. In addition, for example, as represented by the second configuration example, when the first duplexer 7A and the second duplexer 7B are respectively assembled into one group, the configurations of the two can be made the same.

[0158] In the first passband (transmission band) and the second passband (reception band), the pass characteristics of the first filter (first transmission filter 5TA) and the pass characteristics of the third filter (second transmission filter 5TB) can be set to be the same. In addition, in the transmission band and the reception band, the pass characteristics of the second filter (first reception filter 5RA) and the pass characteristics of the fourth filter (second reception filter 5RB) can be set to be the same. In any frequency included in the transmission band and the reception band, the delay time of the first transmission filter 5TA and the delay time of the second transmission filter 5TB can be set to be the same. In the above-mentioned frequency, the delay time of the first reception filter 5RA and the delay time of the second reception filter 5RB can be made the same.

[0159] In this case, for example, in the transmission band and the reception band, the above-mentioned cancellation effect is improved, and the isolation characteristics are improved. In addition, in the simulation calculation performed by the inventor of the present application, by providing the second duplexer 7B, the isolation of -60dB to -70dB in the reception band and the transmission band when only the first duplexer 7A is used is improved to -90dB to -100dB (achieving an isolation improvement of 30dB to 40dB).

[0160] The phase shifter 9 can be composed of a transmission line. The transmission line can have a length equivalent to half the wavelength (λ / 2) of the following signal when it propagates along the transmission line, that is, the frequency of the signal is the same as any frequency (for example, the center frequency of any one of the above three bands) included in the first passband (transmission band) and the second passband (reception band) and the band between them. The λ / 2 transmission line can be located in any one of the following four ranges (positions). Between the first branch point 19T and the first transmission filter 5TA, wherein the first branch point 19T is a branch point where the path from the first terminal (transmission terminal 3T) branches to the first filter (first transmission filter 5TA) and the fourth filter (second transmission filter 5TB). Between the first branch point 19T and the second receiving filter 5RB. Between the second branch point 19R and the first receiving filter 5RA, wherein the second branch point 19R is a branch point where the path from the second terminal (reception terminal 3R) branches to the second filter (first reception filter 5RA) and the third filter (second transmission filter 5TB). Between the second branch point 19R and the second transmission filter 5TB.

[0161] In this case, for example, the phase shifter 9 can be formed by lengthening the wiring length of one of the four ranges, so the structure can be simplified. In addition, the design of the phase shifter 9 for impedance matching is also easier than the method in which the phase shifter 9 is composed of parts dispersed in multiple positions.

[0162] As shown in the first and second configuration examples, the duplexer 1 may include a multilayer substrate (21A or 21B) and one or more chips (23 or 25) mounted on the multilayer substrate. The multilayer substrate may include a transmission line constituting the phase shifter 9. The one or more chips (23 or 25) may include a first filter (a first transmission filter 5TA), a second filter (a first reception filter 5RA), a third filter (a second transmission filter 5TB), and a fourth filter (a second reception filter 5RB).

[0163] In this case, for example, a filter requiring a specific structure and / or material such as an elastic wave filter is implemented by the chip 23 or 25, and the duplexer 1 is implemented by only providing a transmission line as the phase shifter 9 in the multilayer substrate 21A or 21B. That is, the structure is simple.

[0164] As shown in the first construction example, the duplexer 1 may have a multilayer substrate 21A and first to fourth chips (23) mounted on the multilayer substrate 21A. The multilayer substrate 21A may have a common terminal (antenna terminal 3A), a first terminal (transmitting terminal 3T), a second terminal (receiving terminal 3R), and a node 17. The first chip (23) may have a first filter (first transmitting filter 5TA). The second chip (23) may have a second filter (first receiving filter 5RA). The third chip (23) may have a third filter (second transmitting filter 5TB). The fourth chip may have a fourth filter (second receiving filter 5RB).

[0165] The structure of the first chip (the first transmit filter 5TA) and the structure of the third chip (the second transmit filter 5TB) may be the same.

[0166] The structure of the second chip (the first receive filter 5RA) and the structure of the fourth chip (the second receive filter 5RB) may be the same.

[0167] In this case, for example, because the structures of two transmission filters 5T are identical to each other, various characteristics are identical to each other in a wider frequency band. This is also applicable to two receiving filters 5R. Therefore, for example, the intensity of leakage signal and elimination signal is easily equal, and in addition, the phase of two signals is easily made to be anti-phase by phase shifter 9. As a result, the effect of improving isolation characteristics increases. In addition, not only leakage signal and elimination signal, for example, the nonlinear distortion produced in two transmission filters 5T also becomes anti-phase, and expects to be offset each other. In addition, for example, owing to being able to use the same chip for two transmission filters 5T (and two receiving filters 5R), therefore, productivity improves.

[0168] As shown in the second construction example, the duplexer 1 may have a multilayer substrate 21B, and a fifth and sixth chips (25) mounted on the multilayer substrate 21B. The multilayer substrate 21B may have a common terminal (antenna terminal 3A), a first terminal (transmitting terminal 3T), a second terminal (receiving terminal 3R), and a node 17. The fifth and sixth chips (25) may have the same structure as each other. The fifth and sixth chips (25) may each have: a third terminal (31A), a fourth terminal (31T), a fifth terminal (31R), a fifth filter (transmitting filter 5T), and a sixth filter (receiving filter 5R). The transmitting filter 5T may be connected to the terminal 31A and the terminal 31T. The receiving filter 5R may be connected to the terminal 31A and the terminal 31R. In the fifth chip (first duplexer 7A), the terminal 31A may be connected to the common terminal (antenna terminal 3A), the terminal 31T may be connected to the first terminal (transmitting terminal 3T), and the terminal 31R may be connected to the second terminal (receiving terminal 3R). Thus, the fifth filter (transmit filter 5T) can constitute the first filter (first transmit filter 5TA), and the sixth filter (receive filter 5R) can constitute the second filter (first receive filter 5RA). In the sixth chip (second duplexer 7B), terminal 31A can be connected to node 17, terminal 31T can be connected to receive terminal 3R, and terminal 31R can be connected to transmit terminal 3T. Thus, the sixth filter (receive filter 5R) can constitute the third filter (second receive filter 5RB), and the fifth filter (transmit filter 5T) can constitute the fourth filter (second transmit filter 5TB).

[0169] In this case, for example, since the structures of the two duplexers 7 are identical to each other, various characteristics are identical to each other within a wide frequency band. Therefore, the strengths of the leakage signal and the cancellation signal are easily equal, and the phases of the two signals are easily reversed by the phase shifter 9. As a result, the effect of improving the isolation characteristics is increased. In addition, not only the leakage signal and the cancellation signal, for example, the nonlinear distortion generated in the two duplexers 7 is also reversed, and it is expected that they are offset from each other. In addition, for example, since the same chip 25 can be used for the two duplexers 7, the productivity is improved.

[0170] The duplexer 1 may have a resistive element 11 connected to a node 17 .

[0171] In this case, as described above, the effect of the antenna terminal 3A on the leakage signal can be reproduced in the cancellation signal. As a result, the isolation characteristic is improved. In addition, for example, since the duplexer 1 has the resistor element 11, the design burden of the circuit board (not shown) on which the duplexer 1 is mounted can be reduced.

[0172] The communication device 151 may have a duplexer 1, an antenna 159 connected to a common terminal (antenna terminal 3A), a resistor element 11 connected to a node 17 (which the duplexer 1 may or may not have), and an integrated circuit element (RF-IC153) connected to a first terminal (transmitting terminal 3T) and a second terminal (receiving terminal 3R).

[0173] According to such a communication device 151 , the isolation characteristics are improved due to the effects of the above-mentioned duplexer 1 .

[0174] In the above embodiment, the duplexer 1 is an example of a splitter. The first transmission filter 5TA is an example of a first filter. The first reception filter 5RA is an example of a second filter. The second transmission filter 5TB is an example of a third filter. The second reception filter 5RB is an example of a fourth filter. The antenna terminal 3A is an example of a common terminal. The transmission terminal 3T is an example of a first terminal. The reception terminal 3R is an example of a second terminal. The transmission band is an example of a first passband. The reception band is an example of a second passband. The four chips 23 are examples of the first to fourth chips. The two chips 25 are examples of the fifth and sixth chips. The terminal 31A is an example of a third terminal. The terminal 31T is an example of a fourth terminal. The terminal 31R is an example of a fifth terminal. The transmission filter 5T of the chip 25 is an example of a fifth filter. The reception filter 5R of the chip 25 is an example of a sixth filter. The RF-IC 153 is an example of an integrated circuit element.

[0175] The technology of the present invention is not limited to the above-described embodiment, and can be implemented in various forms.

[0176] For example, the duplexer shown in the embodiment may be part of a four-way multiplexer. In other viewpoints, a common terminal (an antenna terminal in the embodiment) may be connected to three or more filters. The wave splitter may be a duplexer that synthesizes two signals from a first terminal and a second terminal and outputs them to a common terminal, or separates a signal from a common terminal and outputs it to a first terminal and a second terminal, or may be a structure that can be understood in this way. In other viewpoints, a duplexer may not be understood as a structure of a duplexer only before being integrated into a communication device, etc.

[0177] Explanation of symbols

[0178] 1: duplexer (wave splitter); 3A: antenna terminal (common terminal); 3T: transmitting terminal (first terminal); 3R: receiving terminal (second terminal); 5TA: first transmitting filter (first filter); 5RA: first receiving filter (second filter); 5TB: second transmitting filter (third filter); 5RB: second receiving filter (fourth filter); 9: phase shifter (180° phase shifter); 17: node.

Claims

1. Wave splitter, with: A first filter connected to the common terminal and the first terminal and corresponding to the first passband; a second filter connected to the common terminal and the second terminal and corresponding to a second passband that does not overlap with the first passband; a third filter, connecting the node at the branch point and the second terminal, and corresponding to the first passband; a fourth filter, connected to the node and the first terminal, and corresponding to the second passband; A 180° phase shifter is located on a side closer to the first terminal than the first filter and the fourth filter, or is located on a side closer to the second terminal than the second filter and the third filter, and makes output signals of two paths based on the same input signal in anti-phase with each other, wherein the two paths are a path from the first terminal via the first filter and the second filter to the second terminal, and a path from the first terminal via the fourth filter and the third filter to the second terminal.

2. The splitter according to claim 1, wherein in the first passband and the second passband, The passing characteristic of the first filter is the same as the passing characteristic of the third filter; The pass characteristic of the second filter is the same as the pass characteristic of the fourth filter; At any frequency included in the first passband and the second passband, The delay time of the first filter is the same as the delay time of the third filter; The delay time of the second filter is the same as the delay time of the fourth filter.

3. The splitter according to claim 1 or 2, The 180° phase shifter is composed of a transmission line; The transmission line has a length corresponding to half the wavelength of a signal propagating along the transmission line, wherein the signal has a frequency that is the same as any frequency included in the first passband and the second passband and in a frequency band therebetween; The transmission line is located at: between the first branch point and the first filter, wherein The first branch point is a branch point where the path from the first terminal branches to the first filter and the fourth filter; between the first branch point and the fourth filter; between a second branch point and the second filter, wherein the second branch point is a branch point where a path from the second terminal branches to the second filter and the third filter; or, between the second branch point and the third branch point.

4. The splitter according to any one of claims 1 to 3, comprising: a multi-layer substrate having a transmission line constituting the 180° phase shifter; One or more chips are mounted on the multi-layer substrate and include: the first filter, the second filter, the third filter, and the fourth filter.

5. The splitter according to any one of claims 1 to 4, comprising: A multi-layer substrate having: the common terminal, the first terminal, the second terminal and the node; A first chip, mounted on the multi-layer substrate, having the first filter; A second chip, mounted on the multi-layer substrate, having the second filter; A third chip, mounted on the multi-layer substrate, having the third filter; A fourth chip, mounted on the multi-layer substrate, having the fourth filter; The structure of the first chip is the same as the structure of the third chip; The structure of the second chip is the same as that of the fourth chip.

6. The splitter according to any one of claims 1 to 4, comprising: A multi-layer substrate having: the common terminal, the first terminal, the second terminal and the node; The fifth chip and the sixth chip are mounted on the multi-layer substrate and have the same structure as each other; The fifth chip and the sixth chip each have: a third terminal, a fourth terminal, and a fifth terminal; a fifth filter connected to the third terminal and the fourth terminal; a sixth filter connected to the third terminal and the fifth terminal; In the fifth chip, The third terminal is connected to the common terminal, the fourth terminal is connected to the first terminal, and the fifth terminal is connected to the second terminal, whereby the fifth filter constitutes the first filter and the sixth filter constitutes the second filter; In the sixth chip, The third terminal is connected to the node, the fourth terminal is connected to the second terminal, and the fifth terminal is connected to the first terminal, whereby the sixth filter constitutes the third filter and the fifth filter constitutes the fourth filter. 7 . The branching filter according to claim 1 , further comprising a resistance element connected to the node.

8. A communication device having: The splitter according to any one of claims 1 to 7; an antenna connected to the common terminal; a resistive element connected to the node; The integrated circuit element is connected to the first terminal and the second terminal.

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