Chip aging test method and system

Abstract

The invention discloses a chip aging test method and system. The chip aging test method provided by the embodiment of the invention comprises the following steps: sending a control signal to an aging test chip, and enabling the aging test chip to enter an aging mode under the control of the control signal; when the aging test chip is in the aging mode, acquiring state information fed back by the aging test chip; and judging whether the aging test chip reaches an aging expectation or not according to the state information. According to the chip aging test method and system provided by the embodiment of the invention, the aging test record of the aging test chip is externally realized, the design complexity of the chip is reduced, and the area required by the chip is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and in particular to a chip aging testing method and system. Background Art

[0002] With the advancement of science and technology and the widespread application of electronic products, chips have been used more and more widely. During the long-term use of chips, due to the instability of environmental factors such as temperature, humidity, and voltage, the electronic components inside the chip are prone to aging, resulting in performance degradation or even failure. In order to ensure the reliability of the chip, aging testing of the chip is indispensable.

[0003] Chip aging test is an important method for evaluating the performance and reliability of integrated circuits (ICs) after long-term use. It simulates various environments and stress conditions that the chip may encounter in actual use, runs the chip for a long time and monitors the changes in its performance indicators to evaluate the chip performance and reliability. In the prior art, the aging test records the aging test time or the number of aging tests inside the chip, and the chip needs to add corresponding designs, which increases the chip design complexity, increases the chip area, and cannot be monitored in real time.

[0004] Therefore, it is hoped that there will be a new chip aging test method and system that can overcome the above problems. Summary of the invention

[0005] In view of the above problems, an object of the present invention is to provide a chip aging test method and system, so as to reduce the design complexity of the chip and reduce the area required for the chip.

[0006] According to one aspect of the present invention, a chip aging test method is provided, comprising:

[0007] Sending a control signal to the aging test chip, and under the control of the control signal, the aging test chip enters an aging mode;

[0008] When the aging test chip is in the aging mode, obtaining state information fed back by the aging test chip; and

[0009] According to the state information, it is determined whether the aging test chip meets the aging expectation.

[0010] Optionally, the chip aging test method further includes:

[0011] Placing the aging test chip on an aging board;

[0012] Establishing an aging test environment on the aging board;

[0013] The sending of a control signal to the aging test chip, and the aging test chip entering the aging mode under the control of the control signal, comprises:

[0014] The aging control board sends an aging mode entry timing to the aging test chip, so that the aging test chip enters the aging mode.

[0015] After receiving the aging mode entry timing, the aging test chip analyzes the aging mode entry timing.

[0016] Optionally, the chip aging test method further includes:

[0017] Obtaining IO flip information of the aging test chip; and

[0018] Determine whether the aging test chip enters the aging mode according to the IO flip information; and / or determine whether the aging test chip is in the aging mode according to the IO flip information.

[0019] Optionally, judging whether the aging test chip meets aging expectations according to the state information includes:

[0020] Acquire first IO data of the aging test chip within a first test time period;

[0021] According to the first IO data, obtaining a first IO flip count in the first IO data;

[0022] When the value of the first IO flipping times is greater than or equal to the first threshold, the test in the first test time period passes;

[0023] When the value of the first IO flip count is less than the first threshold, the test in the first test time period fails;

[0024] The result of passing the test in the first test time period or failing the test in the first test time period is used to determine whether the aging test chip meets aging expectations.

[0025] Optionally, judging whether the aging test chip meets aging expectations according to the state information further includes:

[0026] Respectively acquiring IO data of the aging test chip in multiple test time periods;

[0027] Obtaining the IO flip times corresponding to the multiple test time periods according to the IO data corresponding to the multiple test time periods respectively;

[0028] The multiple test time periods correspond to multiple thresholds;

[0029] Determine whether the test in the corresponding test time period is passed according to whether the values ​​of the IO flip times corresponding to the multiple test time periods are greater than or equal to the corresponding thresholds;

[0030] According to the number of the test time periods and the number of the test time periods that passed the test, it is determined whether the aging test chip meets the aging expectation.

[0031] wherein the multiple test time periods include the first test time period;

[0032] The first threshold is determined according to the first IO data.

[0033] Optionally, the aging control board monitors the aging test chip in real time;

[0034] When the aging test chip detects a test abnormality, the aging test is terminated.

[0035] Optionally, the chip aging test method further includes:

[0036] The aging control board receives and stores the status information;

[0037] The aging control board determines whether the aging test chip meets the aging expectation according to the status information, and obtains and stores the determination result;

[0038] Classifying the aging test chips according to the judgment result; and

[0039] After the test requirements are met, the aging test is terminated.

[0040] According to another aspect of the present invention, a chip aging test system is provided, comprising:

[0041] An aging control board, the aging control board is connected to the aging test chip to send a control signal to the aging test chip; under the control of the control signal, the aging test chip enters an aging mode;

[0042] The aging control board comprises:

[0043] a receiving unit, wherein the receiving unit obtains state information fed back by the aging test chip when the aging test chip is in the aging mode;

[0044] A judgment unit is used to judge whether the aging test chip meets the aging expectation according to the status information.

[0045] Optionally, the chip aging test system further includes:

[0046] The aging board is used to establish an aging test environment and to place the aging test chip.

[0047] Optionally, the receiving unit is connected to the aging test chip to obtain IO flip information of the aging test chip;

[0048] The judging unit is connected to the receiving unit to obtain the IO flip information;

[0049] The judging unit judges whether the aging test chip enters the aging mode according to the IO flip information, and / or judges whether the aging test chip is in the aging mode according to the IO flip information;

[0050] The judging unit judges whether the aging test chip reaches the aging expectation according to the state information to obtain a judgment result;

[0051] The aging control board also includes:

[0052] A storage unit is connected to the judgment unit to receive the judgment result and store the judgment result.

[0053] According to the chip aging test method and system provided by the embodiment of the present invention, the aging test record of the aging test chip is realized externally, which reduces the design complexity of the chip and reduces the area required for the chip.

[0054] Furthermore, the aging test chip receives and analyzes the aging mode entry timing to enter the aging mode, and the control method is simple and accurate.

[0055] Furthermore, whether to enter / be in the aging mode is determined according to the IO flip information of the aging test chip, thereby ensuring the accuracy of the test process.

[0056] Furthermore, whether the chip has passed the aging test is determined based on the number of IO flips, and the determination method is simple and efficient.

[0057] Furthermore, whether the aging test is passed is determined according to the number of IO flips in multiple test time periods, and then the aging test chips are classified according to the proportion of chips that pass the aging test in multiple test time periods, which can efficiently classify the chips.

[0058] Further,

[0059] The aging test board monitors the status information of the chip during the aging test in real time. When an abnormality is detected, the test is stopped in time, which can reduce the test cost, reduce the chip life loss and avoid wasting the aging test machine time. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0061] Figure 1 A method flow chart of a chip aging test method according to Embodiment 1 of the present invention is shown;

[0062] Figure 2 A schematic diagram of a chip aging test system according to a first embodiment of the present invention is shown;

[0063] Figure 3 A method flow chart of a chip aging test method according to a second embodiment of the present invention is shown;

[0064] Figure 4 A schematic diagram of an application scenario of an aging board according to Embodiment 2 of the present invention is shown;

[0065] Figure 5 A schematic structural diagram of an aging control board according to the second embodiment of the present invention is shown. DETAILED DESCRIPTION

[0066] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, identical elements are represented by identical or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown in the drawings.

[0067] The specific implementation of the present invention is further described in detail below in conjunction with the accompanying drawings and examples. Many specific details of the present invention are described below, such as the structure, materials, dimensions, processing technology and techniques of the components, so that the present invention can be more clearly understood. However, as those skilled in the art can understand, the present invention can be implemented without following these specific details.

[0068] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Moreover, if the component is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0069] Figure 1 FIG. 2 shows a method flow chart of a chip aging test method according to Embodiment 1 of the present invention. Figure 1 As shown, the chip aging test method according to the first embodiment of the present invention includes the following steps:

[0070] In step S101, a control signal is sent to the aging test chip, and under the control of the control signal, the aging test chip enters an aging mode;

[0071] For example, the aging control board sends a control signal to the aging test chip. Under the control of the control signal, the aging test chip enters the aging mode.

[0072] In step S102, when the aging test chip is in the aging mode, status information fed back by the aging test chip is obtained;

[0073] When the aging test chip is in the aging mode, the state information fed back by the aging test chip is obtained. Optionally, the state information includes but is not limited to IO interface flip information. Optionally, the aging control board obtains the state information fed back by the aging test chip in real time.

[0074] In step S103, it is determined whether the aging test chip meets aging expectations based on the status information.

[0075] For example, the aging control board determines whether the aging test chip meets the aging expectation based on the status information. Optionally, the analysis (judgment) algorithm of the aging test board includes but is not limited to: counting the IO flips (of the aging test chip), and if the number of flips is greater than a certain value, it means that the aging test has passed, otherwise the aging test has failed.

[0076] In an optional embodiment of the present invention, the chip aging test is applied to the chip after packaging, accelerating the chip aging under high temperature and high pressure, stimulating early chip failure, and making the chip enter a stable working period. After the aging test chip enters the aging mode, the aging test chip generates an excitation to drive the aging test chip register and memory to work, and the start time and end time of the work are saved by external detection. The process of chip aging test can include the following steps:

[0077] Step 1: Determine the purpose and test items of the aging test chip. Determine the test objectives and test contents according to actual needs, including test time, environmental conditions, stress factors, etc.

[0078] Step 2: Design an aging test plan for the aging test chip. Design a test plan based on the characteristics of the aging test chip and the stress factors it is subjected to, including stress type, stress level, test time, test conditions, etc.

[0079] Step 3: Implement aging test. Implement aging test chip aging test according to the test plan, and monitor various parameters and performance indicators during the test process.

[0080] Step 4: Analyze the aging test results. Analyze and process the test data to evaluate the life and reliability of the aging test chip.

[0081] In an optional embodiment of the present invention, the chip aging test method further includes the following steps:

[0082] The aging test chip is placed on the aging board, and the aging test chip is connected to the aging board through physical wiring, for example. The connection between the aging test chip and the aging board may include electrical connection, mechanical connection, etc.

[0083] Establish an aging test environment on the aging board. The aging board is a test device used to simulate the reliability and performance stability of the aging test chip under long-term use and load conditions. The aging board usually contains a series of circuits and components to provide appropriate test loads, voltages, frequencies, temperatures and other parameters to simulate the environmental conditions of the aging test chip in actual use.

[0084] Optionally, sending a control signal to the aging test chip, and under the control of the control signal, the aging test chip entering the aging mode includes:

[0085] The aging control board sends an aging mode entry timing to the aging test chip, so that the aging test chip enters the aging mode.

[0086] The aging test chip analyzes the aging mode entry timing after receiving the aging mode entry timing.

[0087] In an optional embodiment of the present invention, the chip aging test method further includes:

[0088] Get the IO flip information of the aging test chip. IO flip information refers to the information that the state of the input and output (IO) port in the digital circuit changes. This change usually refers to a change from a high level to a low level, or from a low level to a high level.

[0089] The (aging control board) determines whether the aging test chip enters the aging mode according to the IO flip information, and / or the (aging control board) determines whether the aging test chip is in the aging mode according to the IO flip information.

[0090] In an optional embodiment of the present invention, judging whether the aging test chip meets the aging expectation according to the state information includes:

[0091] Acquire first IO data of the aging test chip within a first test time period;

[0092] According to the first IO data, obtaining a first IO flip count in the first IO data;

[0093] When the value of the first IO flipping times is greater than or equal to the first threshold, the test in the first test time period passes;

[0094] When the value of the first IO flip count is less than the first threshold, the test in the first test time period fails;

[0095] The result of passing the test in the first test time period or failing the test in the first test time period is used to determine whether the aging test chip meets aging expectations.

[0096] Optionally, judging whether the aging test chip meets aging expectations according to the state information further includes:

[0097] Respectively acquiring IO data of the aging test chip in multiple test time periods;

[0098] Obtaining the IO flip times corresponding to the multiple test time periods according to the IO data corresponding to the multiple test time periods respectively;

[0099] The multiple test time periods correspond to multiple thresholds;

[0100] Determine whether the test in the corresponding test time period is passed according to whether the values ​​of the IO flip times corresponding to the multiple test time periods are greater than or equal to the corresponding thresholds;

[0101] According to the number of the test time periods and the number of the test time periods that passed the test, it is determined whether the aging test chip meets the aging expectation.

[0102] wherein the multiple test time periods include the first test time period;

[0103] The first threshold is determined according to the first IO data.

[0104] In an optional embodiment of the present invention, the aging control board monitors the aging test chip in real time; when the aging test chip detects a test abnormality, the aging test is terminated.

[0105] Optionally, the chip aging test method further includes:

[0106] The aging control board receives and stores the status information;

[0107] The aging control board determines whether the aging test chip meets the aging expectation according to the status information, and obtains and stores the determination result;

[0108] Classifying the aging test chips according to the judgment result; and

[0109] After the test requirements are met, the aging test is terminated.

[0110] Figure 2FIG. 1 shows a schematic diagram of a chip aging test system according to Embodiment 1 of the present invention. Figure 2 As shown, the chip aging test system according to the first embodiment of the present invention includes an aging control board 100. The aging control board 100 includes a receiving unit 110 and a judging unit 120.

[0111] Specifically, the aging control board 100 is connected to the aging test chip to send a control signal to the aging test chip. Under the control of the control signal, the aging test chip enters the aging mode.

[0112] The receiving unit 110 obtains the state information fed back by the aging test chip when the aging test chip is in the aging mode.

[0113] The judging unit 120 judges whether the aging test chip meets the aging expectation according to the status information.

[0114] Optionally, the receiving unit 110 is connected to the aging test chip to obtain IO flip information of the aging test chip.

[0115] The judgment unit 120 is connected to the receiving unit 110 to obtain the IO flip information. The judgment unit 120 judges whether the aging test chip enters the aging mode according to the IO flip information, and / or (the judgment unit 120) judges whether the aging test chip is in the aging mode according to the IO flip information. The judgment unit 120 judges whether the aging test chip meets the aging expectation according to the state information to obtain a judgment result.

[0116] The aging control board 100 further includes a storage unit 130. The storage unit 130 is connected to the judgment unit 120 to receive the judgment result and store the judgment result.

[0117] In an optional embodiment of the present invention, the chip aging test system further includes an aging board 200. The aging board 200 is used to establish an aging test environment and to place the aging test chip.

[0118] Figure 3 A method flow chart of a chip aging test method according to the second embodiment of the present invention is shown. Figure 4 A schematic diagram of an application scenario of a burn-in board according to the second embodiment of the present invention is shown. Figure 5 A schematic structural diagram of an aging control board according to the second embodiment of the present invention is shown.

[0119] Combination Figures 3 to 5 As shown, the chip aging test system according to the second embodiment of the present invention includes an aging control board 100, an aging furnace, an aging board 200 and an aging test chip.

[0120] Multiple aging test chips are installed on the aging board 200 ( Figure 4The schematic diagram shows that the first aging test chip 301 and the second aging test chip 302 are mounted on the aging board 200, and the (multiple) aging boards 200 are stored in the aging furnace. The aging control board 100 is outside the aging furnace and is connected to the aging board through physical wiring.

[0121] The aging control board 100 includes a controller 140. The controller 140 implements, for example, any one (or several) of the functions of the above-mentioned receiving unit, judging unit and storage unit or other functions.

[0122] The chip aging test method according to the second embodiment of the present invention comprises the following steps:

[0123] In step S201, after the aging board is powered on, the chip enters the test mode;

[0124] After the aging board is powered on, the aging test chip enters the test mode.

[0125] In step S202, the aging control board sends a control signal to the chip to make the chip enter an aging mode;

[0126] The aging control board sends a control signal to the (aging test) chip, which puts the chip into aging mode.

[0127] In step S203, the aging control board monitors chip status information;

[0128] The aging control board monitors chip status information, such as real-time monitoring of chip feedback status information.

[0129] In step S204, the aging control board stores the received chip status information;

[0130] The aging control board stores the received chip status information.

[0131] In step S205, the aging control board analyzes the received chip status information;

[0132] The aging control board analyzes the status information of the received chip.

[0133] In step S206, it is determined whether the chip has reached the expected aging state;

[0134] Determine whether the chip has reached the expected aging. When it is determined that the chip has reached the expected aging, execute step S207; when it is determined that the chip has not reached the expected aging, execute step S208.

[0135] In step S207, it is determined whether the chip aging time has been reached;

[0136] Determine whether the chip aging time has been reached. If it is determined that the chip aging time has been reached, execute step S209; if it is determined that the chip aging time has not been reached, return to execute step S203.

[0137] In step S208, the aging test is ended and the chip aging test failure is recorded;

[0138] End the aging test and record that the chip has failed the aging test.

[0139] In step S209, the aging test is ended and it is recorded that the chip aging test has passed.

[0140] End the aging test and record that the chip has passed the aging test.

[0141] Optionally, the result of whether the aging test is passed or not is recorded so as to classify the aging test chips later. In addition, the aging test is terminated after reaching the (predetermined) aging test time.

[0142] In a specific embodiment of the present invention, the burn-in control board sends a burn-in mode entry sequence to the (burn-in test) chip to make the chip enter the burn-in test mode, wherein the analysis of the burn-in test sequence is implemented by chip hardware.

[0143] During the aging test, the chip is externally (to the aging control board) proven through IO flipping to prove that the chip has entered the aging test mode and that the chip is operating normally.

[0144] The aging control board processes the signal (status information) returned by the chip as follows:

[0145] For each aging test chip, every 10 minutes (or other durations), the aging control board driver (BIDriver) samples the IO data of the aging test chip 5000 times (it can also be set to other times according to actual needs).

[0146] Each time an (IO) rollover is detected, the count value is increased by one (the count can be completed by the aging control board). When the count reaches 200 times (the number can be set according to requirements), the Flag is set to pass, otherwise the Flag is set to fail.

[0147] The predetermined aging test time is, for example, 4 hours. At the end of 4 hours, the number of times the Flag is passed will be read 24 times.

[0148] When all Flags are pass, the result is judged as 1_BIN1;

[0149] When the number of Flag passes is greater than 90%, that is, greater than or equal to 22 times, it is determined as result 2_BIN2;

[0150] When the number of Flag passes is less than 90%, that is, less than 22 times, it is determined as result 3_BIN3.

[0151] After the aging control board processes the status information, it can classify the aging test chips into three categories (results 1-3). Optionally, the above three results can be reverse-labeled on the BI (aging control board) map with three colors for classification and automatic BIN classification.

[0152] According to the chip aging test method and system of the embodiment of the present invention, the chip aging test recording function is realized by an external aging test board, which can reduce the complexity of chip design and reduce the chip area; further, the aging test board monitors the status information of the chip during the aging test in real time and analyzes it, and promptly controls to stop the test when an abnormality is monitored, thereby reducing the test cost, reducing the chip life loss and avoiding the waste of the aging test machine; the aging test board supports the aging status information retention and analysis capabilities, and the collected data can be used for data statistical analysis, thereby providing data support for the regular maintenance of the aging board, improving test efficiency and test quality. The optional embodiment of the present application also requires the chip to have an aging operation indication flip signal.

[0153] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0154] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A chip aging test method, comprising: Sending a control signal to the aging test chip, and under the control of the control signal, the aging test chip enters an aging mode; When the aging test chip is in the aging mode, obtaining status information fed back by the aging test chip; as well as According to the state information, it is determined whether the aging test chip meets the aging expectation.

2. The chip aging test method according to claim 1, wherein: The chip aging test method further includes: Placing the aging test chip on an aging board; Establishing an aging test environment on the aging board; The sending of a control signal to the aging test chip, and the aging test chip entering the aging mode under the control of the control signal, comprises: The aging control board sends an aging mode entry timing to the aging test chip, so that the aging test chip enters the aging mode. After receiving the aging mode entry timing, the aging test chip analyzes the aging mode entry timing.

3. The chip aging test method according to claim 1, wherein: The chip aging test method further includes: Obtaining IO flip information of the aging test chip; and Determine whether the aging test chip enters the aging mode according to the IO flip information; and / or determine whether the aging test chip is in the aging mode according to the IO flip information.

4. The chip aging test method according to claim 1, wherein: The determining, according to the state information, whether the aging test chip has reached the aging expectation includes: Acquire first IO data of the aging test chip within a first test time period; According to the first IO data, obtaining a first IO flip count in the first IO data; When the value of the first IO flipping times is greater than or equal to the first threshold, the test in the first test time period passes; When the value of the first IO flip count is less than the first threshold, the test in the first test time period fails; The result of passing the test in the first test time period or failing the test in the first test time period is used to determine whether the aging test chip meets aging expectations.

5. The chip aging test method according to claim 4, wherein: The step of judging whether the aging test chip has reached the aging expectation according to the state information further comprises: Respectively acquiring IO data of the aging test chip in multiple test time periods; Obtaining the IO flip times corresponding to the multiple test time periods according to the IO data corresponding to the multiple test time periods respectively; The multiple test time periods correspond to multiple thresholds; Determine whether the test in the corresponding test time period is passed according to whether the values ​​of the IO flip times corresponding to the multiple test time periods are greater than or equal to the corresponding thresholds; According to the number of the test time periods and the number of the test time periods that passed the test, it is determined whether the aging test chip meets the aging expectation. wherein the multiple test time periods include the first test time period; The first threshold is determined according to the first IO data.

6. The chip aging test method according to claim 1, wherein: The aging control board monitors the aging test chip in real time; When the aging test chip detects a test abnormality, the aging test is terminated.

7. The chip aging test method according to claim 1, wherein: The chip aging test method further includes: The aging control board receives and stores the status information; The aging control board determines whether the aging test chip meets the aging expectation according to the status information, and obtains and stores the determination result; Classifying the aging test chips according to the judgment result; and After the test requirements are met, the aging test is terminated.

8. A chip aging test system, comprising: An aging control board, the aging control board is connected to the aging test chip to send a control signal to the aging test chip; Under the control of the control signal, the aging test chip enters an aging mode; The aging control board comprises: a receiving unit, wherein the receiving unit obtains state information fed back by the aging test chip when the aging test chip is in the aging mode; A judgment unit is used to judge whether the aging test chip meets the aging expectation according to the status information.

9. The chip aging test system according to claim 8, wherein: The chip aging test system also includes: The aging board is used to establish an aging test environment and to place the aging test chip.

10. The chip aging test system according to claim 8, wherein: The receiving unit is connected to the aging test chip to obtain IO flip information of the aging test chip; The judging unit is connected to the receiving unit to obtain the IO flip information; The judging unit judges whether the aging test chip enters the aging mode according to the IO flip information, and / or judges whether the aging test chip is in the aging mode according to the IO flip information; The judging unit judges whether the aging test chip reaches the aging expectation according to the state information to obtain a judgment result; The aging control board also includes: A storage unit is connected to the judgment unit to receive the judgment result and store the judgment result.

Images