Visual modeling mixing rate real-time simulation system

Abstract

The invention discloses a visual modeling mixed rate real-time simulation system. The system comprises a simulation computer, a model development computer, a simulation machine client computer, an automatic test computer, a signal conditioning board card, a fault injection unit, a tested unit, an FPGA model machine and a clock synchronizer. Wherein the simulation computer is used for completing loading and operation control of a simulation model; the model development computer is used for completing programming and development debugging of the simulation model; the simulation machine client computer is used for completing operation monitoring of the simulation model; the automatic test computer is used for completing simulation test driving control of the simulation model in a signal loop; the signal conditioning board card is used for converting a digital signal after the simulation model runs into an analog signal; the fault injection unit is used for completing a soft fault injection function and an emergency fault injection function of a fault mode; the tested unit is used for configuring a tested object; the FPGA model machine is used for loading and running the compiled FPGA source code; and the clock synchronizer is used for completing synchronization of model simulation.

Description

Technical Field

[0001] The invention relates to the field of model simulation, and in particular to a visual modeling mixed rate real-time simulation system. Background Art

[0002] At present, the design of aircraft engine control systems and software mainly refers to some international mainstream processes such as SAE ARP 4754, DO-178 and DO-331. The system development process ARP4754 points out the classic double V process of system requirements analysis, system design and system verification, and DO-178 proposes the process of software from requirements, coding to integrated testing. However, there is no general process and typical method for how to implement the system design process from system requirements to software requirements. Summary of the invention

[0003] A brief summary of one or more aspects is given below to provide a basic understanding of these aspects. This summary is not an exhaustive overview of all conceived aspects, and is neither intended to identify the key or critical elements of all aspects nor to define the scope of any or all aspects. Its only purpose is to give some concepts of one or more aspects in a simplified form as a prelude to a more detailed description that will be given later.

[0004] The purpose of the present invention is to solve the above-mentioned problems and provide a visual modeling mixed rate real-time simulation system, which solves the current commercial aircraft engine model-based design (MBD) process to carry out control system prototype verification, software integration verification, software and hardware integration verification, and fuel system joint verification (semi-physical verification). Due to the large number of disciplines involved in carrying out system-level verification and unclear interfaces, it is difficult to locate and troubleshoot problems that arise during the integration and operation of the real-time simulation system. The professional layout of the simulation integration link is optimized, the division of labor and integration efficiency of the simulation system is improved, and the quality and work efficiency of carrying out simulation experiments are improved.

[0005] The technical solution of the present invention is:

[0006] The present invention provides a visual modeling mixed rate real-time simulation system, comprising a simulation computer, a model development computer, a simulation machine client computer, an automatic test computer, a signal conditioning board, a fault injection unit, a unit under test, an FPGA model machine and a clock synchronization machine; wherein,

[0007] The simulation computer is used to complete the loading and operation control of the simulation model;

[0008] The model development computer is used to complete the programming, development and debugging of the simulation model;

[0009] The simulation machine client computer is used to complete the operation monitoring of the simulation model;

[0010] The automatic test computer is used to complete the simulation test drive control of the simulation model in the signal loop;

[0011] The signal conditioning board is used to convert the digital signal after the simulation model runs into an analog signal;

[0012] The fault injection unit is used to complete the soft fault and fault injection functions of the fault mode;

[0013] The unit under test is used to configure the object under test;

[0014] The FPGA model machine is used to load and run the compiled FPGA source code;

[0015] The clock synchronization machine is used to complete the clock synchronization during model simulation.

[0016] According to one embodiment of the visual modeling mixed rate real-time simulation system of the present invention, the simulation computer, the model development computer, the automatic testing computer, the simulation machine client computer and the FPGA model machine constitute a computer local area network, and the deployment and operation of the visual modeling mixed rate real-time simulation system are completed through the constructed computer local area network.

[0017] According to one embodiment of the visual modeling mixed-rate real-time simulation system of the present invention, the simulation computer, signal conditioning board, fault injection unit and unit under test are connected one by one in a point-to-point series manner to form a signal loop, and signal transmission, conversion and closed-loop are completed through the constructed signal loop.

[0018] According to an embodiment of the visual modeling mixed rate real-time simulation system of the present invention, the simulation computer includes a simulation control and operating environment, a simulation machine OS terminal, a compiler, a simulation machine operating environment scheduling machine, a simulation machine virtual network console server, a human-computer interaction device, a file receiver, and a model interface parser; wherein,

[0019] The simulation control and operation environment is used to provide the simulation computer internal model scheduling, monitoring, test case loading, signal interconnection, model and CPU core mapping functions;

[0020] The simulator OS terminal is used to provide the simulator operation application program interface;

[0021] Compilers are used to convert high-level languages ​​into binary target languages;

[0022] The simulation machine running environment scheduling machine is used to complete the scheduling of the simulation running environment;

[0023] The emulator virtual network console server is used to provide a emulator client login interface for remote network access;

[0024] The human-computer interaction device is used to provide a simulation model control operation interface;

[0025] The file receiver is used to parse the communication signals received through the hardware network interface of the emulator;

[0026] The model interface parser is used to call the model and convert the called model interface into the model interface encapsulation source code of the new standard interface.

[0027] According to an embodiment of the visual modeling mixed rate real-time simulation system of the present invention, the simulation control and operation environment includes a simulation environment state machine, a model distributor, a model signal interconnector, a model loader, a real-time operation monitor and a use case loader; wherein,

[0028] The simulation environment state machine is used to uniformly schedule the execution of the model distributor, model signal interconnector, model loader, real-time operation monitor and use case loader, and accept the scheduling execution information fed back by the model distributor, model signal interconnector, model loader, real-time operation monitor and use case loader;

[0029] The model distributor is used to distribute the simulation model;

[0030] The model signal interconnector is used to complete the interconnection of signals between simulation models;

[0031] The model loader is used to provide status information of the use case execution;

[0032] The real-time operation monitor is used to complete the real-time operation monitoring of the simulation model;

[0033] The use case loader is used to complete the loading of simulation use cases.

[0034] According to one embodiment of the visual modeling mixed-rate real-time simulation system of the present invention, the simulation control and operating environment statically configures different models to specific CPU cores through a model allocator, establishes the operating timing between the models, and then simulates and runs each model according to the model operating timing, thereby realizing the parallel simulation strategy of the visual modeling mixed-rate real-time simulation system.

[0035] According to an embodiment of the visual modeling mixed rate real-time simulation system of the present invention, the model development computer includes a graphical modeling environment, a Make file generator, a model code generator, a file sender, an FPGA code generator, an FPGA compiler and an FPGA target code loader; wherein,

[0036] The graphical modeling environment is used to provide a graphical model development environment;

[0037] The Make file generator is used to generate Make files;

[0038] The model code generator is used to convert the low-speed model file into high-level language source code;

[0039] The file sender is used to send the high-level language source code and the corresponding Make file to the simulation computer;

[0040] FPGA code generator is used to convert high-speed model files into FPGA code;

[0041] FPGA compiler is used to compile FPGA code;

[0042] The FPGA target code loader is used to load the FPGA target code.

[0043] According to an embodiment of the visual modeling mixed rate real-time simulation system of the present invention, the model development computer adopts a high-speed and low-speed model division strategy, and builds a low-speed model and a high-speed model respectively through a low-speed model development environment and a high-speed model development environment; wherein,

[0044] The low-speed model development environment includes a graphical modeling environment, a Make file generator, a model code generator, and a file sender;

[0045] The high-speed model development environment includes a graphical modeling environment, an FPGA code generator, an FPGA compiler, and an FPGA target code loader.

[0046] According to an embodiment of the visual modeling mixed rate real-time simulation system of the present invention, the simulation machine client computer includes a virtual network console client, a remote simulation machine desktop interaction interface and a human-computer interaction device; wherein,

[0047] The virtual network console client exchanges information with the simulated computer through the computer local area network;

[0048] The remote simulation machine desktop interactive interface is used to provide remote control instructions;

[0049] Human-computer interaction equipment is used to provide human-computer control instructions.

[0050] According to one embodiment of the visual modeling mixed-rate real-time simulation system of the present invention, the automatic testing computer includes an operating system terminal and a use case transceiver; wherein the operating system terminal is used to load test cases and test case scripts, and call the use case transceiver to complete the data transmission of the test cases.

[0051] According to an embodiment of the visual modeling mixed rate real-time simulation system of the present invention, the FPGA model machine includes an FPGA target code loader, a FLASH memory, an FPGA chip and a high-speed data communication interface; wherein,

[0052] The FPGA target code loader is used to load the FPGA source code model binary file;

[0053] The FLASH memory is used to store the FPGA code loaded by the FPGA target code loader;

[0054] The FPGA chip is used to run the FPGA code stored in the FLASH memory;

[0055] The high-speed data communication interface is used to read high-speed model interface data.

[0056] According to an embodiment of the visual modeling mixed rate real-time simulation system of the present invention, the visual modeling mixed rate real-time simulation system adopts an operating system with real-time characteristics and triggers real-time simulation through a software timer or a physical clock.

[0057] Compared with the prior art, the present invention has the following beneficial effects: the present invention provides a visual modeling mixed rate real-time simulation system for the simulation design of commercial aviation engine models, provides a standard implementation process for each process of engine model simulation design, and builds high- and low-speed models through a graphical interface, thereby achieving the unification of hybrid model modeling. In addition, the present invention divides the high- and low-speed models, and runs the high- and low-speed models on different physical entities respectively, ensuring the physical isolation of the hybrid system and the independence of the high- and low-speed models from each other, thereby significantly improving the work efficiency of fault location during the simulation process. At the same time, the present invention adopts a parallel simulation strategy of loading different models to different CPU cores, which ensures the true parallel operation of the hybrid model, improves the performance of the model simulation operation, and improves the real-time confidence. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] The above features and advantages of the present invention can be better understood after reading the detailed description of the embodiments of the present disclosure in conjunction with the following drawings. In the drawings, the components are not necessarily drawn to scale, and components with similar related properties or features may have the same or similar reference numerals.

[0059] Figure 1 1 is an architectural diagram showing an embodiment of a visual modeling mixed-rate real-time simulation system of the present invention.

[0060] Figure 2 It is a data interaction diagram showing an embodiment of the visual modeling mixed rate real-time simulation system of the present invention.

[0061] Explanation of symbols:

[0062] (1): Simulation computer,

[0063] (2): Model development computer,

[0064] (3): Simulation machine client computer,

[0065] (4): Automatic test computer,

[0066] (5): Signal conditioning board,

[0067] (6): Fault injection unit,

[0068] (7): Unit under test (UUT),

[0069] (8): FPGA model machine,

[0070] (9): Clock synchronizer,

[0071] (1.0): Simulation control and operating environment,

[0072] (1.1): Simulation machine OS terminal,

[0073] (1.2): Compiler,

[0074] (1.3): Model allocator,

[0075] (1.4) Model signal interconnector,

[0076] (1.5): Model loader,

[0077] (1.6): Real-time operation monitor,

[0078] (1.7): Use case loader,

[0079] (1.8): Simulation environment state machine,

[0080] (1.9): Simulator operating environment scheduler,

[0081] (1.10): Simulator virtual network console server,

[0082] (1.20): File Receiver,

[0083] (1.21): Model dynamic library file,

[0084] (1.22): Model executable file,

[0085] (1.23): Model and CPU core binding relationship and timing files,

[0086] (1.24): Mode signal binding relationship file,

[0087] (1.25): Simulation engineering operation data,

[0088] (1.26): Human-computer interaction equipment,

[0089] (1.27): Model interface parser,

[0090] (1.28) Model interface encapsulation source code

[0091] (2.1): Graphical modeling environment,

[0092] (2.2): Low-speed model file,

[0093] (2.3): Make file generator,

[0094] (2.4): Model code generator,

[0095] (2.5): High-level language source code,

[0096] (2.6): Make file template,

[0097] (2.7): Make file,

[0098] (2.8): File sender,

[0099] (2.11): FPGA source code,

[0100] (2.12): FPGA source code,

[0101] (2.13): FPGA code generator,

[0102] (2.14): FPGA compiler,

[0103] (2.15): FPGA target code,

[0104] (2.16): FPGA target code loader,

[0105] (3.1): Virtual Network Console Client,

[0106] (3.2): Remote simulation machine desktop interactive interface,

[0107] (3.3): Human-computer interaction equipment,

[0108] (4.1): Test cases,

[0109] (4.2): Test control script,

[0110] (4.3): Operating system terminal,

[0111] (4.4): Use case transceiver,

[0112] (8.01): FPGA target code loader,

[0113] (8.02): FLASH memory,

[0114] (8.03): FPGA chips,

[0115] (8.04): High-speed data communication interface. DETAILED DESCRIPTION

[0116] The present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments. Note that the aspects described below in conjunction with the accompanying drawings and specific embodiments are only exemplary and should not be construed as limiting the scope of protection of the present invention in any way.

[0117] An embodiment of a mixed-rate real-time simulation system for visual modeling is disclosed herein. Figure 1 1 is an architectural diagram showing an embodiment of the visual modeling mixed rate real-time simulation system of the present invention. Figure 1 As shown, in this embodiment, it includes a simulation computer (1), a model development computer (2), a simulation machine client computer (3), an automatic test computer (4), a signal conditioning board (5), a fault injection unit (FIU) (6), a unit under test (UUT) (7), an FPGA model machine (8) and a clock synchronization machine (9). Among them, the simulation computer (1) is used to complete the loading and operation control of the simulation model; the model development computer (2) is used to complete the programming and development debugging of the simulation model; the simulation machine client computer (3) is used to complete the operation monitoring of the simulation model; the automatic test computer (4) is used to complete the simulation test drive control of the simulation model in the signal loop; the signal conditioning board (5) is used to convert the digital signal after the simulation model is run into an analog signal; the fault injection unit (6) is used to complete the injection function of the soft fault and the fault of the fault mode; the unit under test (7) is used to configure the object under test; the FPGA model machine (8) is used to load and run the compiled FPGA source code; the clock synchronization machine (9) is used to complete the clock synchronization during the model simulation.

[0118] Specifically, in this embodiment, the simulation computer (1), the model development computer (2), the automatic test computer (4), the simulation machine client computer (3) and the FPGA model machine (8) constitute a computer local area network (0). The deployment and operation of the visual modeling mixed rate real-time simulation system are completed through the constructed computer local area network (0). The specific process is as follows:

[0119] The simulation machine client computer (3) logs in and remotely controls the simulation computer (1) through the remote login client, and then completes the graphical modeling and model code generation through the model development computer (2), and sends the generated high-level language source code (with model dynamic library) and Make file of the low-speed model to the simulation computer (1) through the UDP protocol, and completes the generation and loading and running of the model source file to the executable model file through the simulation computer (1). For the FPGA code of the high-speed model, the model development computer (2) sends the generated FPGA code of the high-speed model to the FPGA model machine (8) through the UDP protocol, and the binary FPGA target code received after communication is transferred to the FLASH memory through the FPGA model machine (8), and the code in the FLASH memory is loaded into the FPGA chip after power-on, and runs at high speed and in real time. The automatic test computer (4) sends the compilation of the use case, the use case file and the use case execution script file to the simulation computer (1) for control. In this way, through the above collaborative operation, the deployment and operation of the visual modeling slow rate real-time simulation system are completed, and at this time, the visual modeling mixed rate real-time simulation system can support the simulation test activities of the high-level language model and the FPGA language model at the same time.

[0120] In addition, in this embodiment, the simulation computer (1), the signal conditioning board (5), the fault injection unit (6) and the unit under test (7) are connected one by one in a point-to-point series manner to form a signal loop. The signal transmission, conversion and closed loop are completed through the constructed signal loop. The specific process is as follows:

[0121] The simulation computer (1) transmits the continuous quantity and switch quantity of the simulation model to the signal conditioning board (5) through the cable through the analog signal. At the same time, the simulation computer (1) transmits the bus signal (such as ARINC, TTP, 1553B, 422 / 485 / 232, etc.) in the model to the signal conditioning board (5) through another cable through the digital bus signal. The signal conditioning board (5) conditions the received analog signal and switch signal into an electrical signal with corresponding signal physical electrical characteristics and transmits it to the fault injection unit (6). The fault injection unit (6) disconnects and shorts the loop of the corresponding signal cable to achieve the corresponding fault injection. The signal output by the signal conditioning board (5) via the fault injection unit (6) forms a direct loop or an excitation-response secondary loop through the unit under test (7), thereby achieving the simulation of a real electrical signal with a disconnection and short circuit function.

[0122] Furthermore, in this embodiment, the simulation computer (1) includes a simulation control and runtime environment SCRE (1.0), a simulation machine OS terminal (1.1), a compiler (1.2), a simulation machine runtime environment scheduler (1.9), a simulation machine virtual network console server (1.10), a human-computer interaction device (1.26), a file receiver (1.20), and a model interface parser (1.27). Among them, the simulation control and operation environment SCRE (1.0) is used to provide the simulation computer (1) with internal model scheduling, monitoring, test case loading, signal interconnection, model and CPU core mapping functions; the simulation machine OS terminal (1.1) is used to provide the simulation machine operation application interface; the compiler (1.2) is used to convert the high-level language into a binary target language; the simulation machine operation environment scheduler (1.9) is used to complete the scheduling of the simulation operation environment; the simulation machine virtual network console server (1.10) is used to provide a simulation machine client login interface for remote network access; the human-computer interaction device is used to provide a simulation model control operation interface; the file receiver (1.20) is used to parse the communication signal received through the simulation machine hardware network interface; the model interface parser (1.27) is used to call the model and convert the called model interface into a new standard interface model interface encapsulation source code. Figure 2 is a data interaction diagram showing an embodiment of the visual modeling mixed rate real-time simulation system of the present invention, see Figure 2 , the internal data flow of the simulation computer (1) is as follows:

[0123] The file receiver (1.20) is used to receive the model and script files sent from the file transmitter (2.8) via the computer local area network (0), and output them to the model dynamic library file (1.21). The model interface parser (1.27) identifies the model dynamic library file from the model dynamic library file (1.21), and then generates the model interface encapsulation source code (1.28). Then, the compiler (1.2) is called in the simulator OS terminal (1.1) to load the model interface encapsulation source code (1.28). At this time, if the compilation link passes, the Model executable file (1.22) is output; if it fails, the fault diagnosis information is output, and the graphical modeling environment (2.1) is returned to re-carry out modeling and compilation debugging.

[0124] The simulator operation environment scheduler (1.9) is used to receive the test control script (4.2) sent by the use case loader (4.4) via the computer local area network (0). At the same time, the simulator operation environment scheduler (1.9) receives the operation instruction sent by the simulator virtual network console server (1.10). The simulator operation environment scheduler (1.9) schedules and selects the use case control script (4.1) automatically loaded through the network and the control instruction from the remote simulator interaction interface (3.2), and outputs the scheduling instruction information to the SCRE state machine (1.8), and receives the operation feedback information of the simulation control and operation environment SCRE (1.0) from the SCRE state machine (1.8), and completes the interactive control of the simulation control and operation environment SCRE (1.0) and other external components in turn.

[0125] Furthermore, in this embodiment, the simulation control and runtime environment SCRE (1.0) includes a simulation environment state machine (1.8), a model distributor (1.3), a model signal interconnector (1.4), a model loader (1.5), a real-time operation monitor (1.6), and a use case loader (1.7). The simulation environment state machine (1.8) is used to uniformly schedule the execution of the model distributor (1.3), the model signal interconnector (1.4), the model loader (1.5), the real-time operation monitor (1.6), and the use case loader (1.7), and accept the scheduling execution information fed back by the model distributor (1.3), the model signal interconnector (1.4), the model loader (1.5), the real-time operation monitor (1.6), and the use case loader (1.7). The model distributor (1.3) is used to distribute simulation models; the model signal interconnector (1.4) is used to complete the interconnection of signals between simulation models; the model loader (1.5) is used to provide the status information of the use case execution; the real-time operation monitor (1.6) is used to complete the real-time operation monitoring of the simulation model; the use case loader (1.7) is used to complete the loading of simulation use cases. Among them, the internal process of the simulation control and operation environment (1.0) is as follows:

[0126] The model distributor (1.3) is used to receive the Model executable file (1.22), and complete the binding relationship between the Model and the CPU core and the generation of the timing file (1.23) through the human-computer interaction configuration of the operator. At the same time, the model signal interconnector (1.4) completes the generation of the Model signal binding relationship file (1.24) after the human-computer interaction configuration of the operator. The real-time operation monitor (1.6) is used to complete the generation of the simulation project operation data (1.25), and the use case loader (1.7) is used to complete the reading and parsing of the test case sent from the operating system terminal (4.3) via the computer local area network (0), and then output the parsed data to the model loader (1.5), and obtain the status information of the use case execution from the model loader (1.5). In addition, the use case loader (1.7) also needs to feed back the use case execution record information to the operating system terminal (4.3).

[0127] In addition, in this embodiment, the simulation control and operation environment SCRE (1.0) statically configures different models to specific CPU cores through the model distributor (1.3), establishes the operation sequence between the models, and generates the corresponding (1.16) Model and CPU core binding relationship and timing file script by the model loader (1.5). When the simulation control and operation environment SCRE (1.0) is running, the model loader (1.5) loads the (1.16) script, and then the simulation machine operating system loads it to a specific CPU core, and each model runs in parallel according to the characteristic timing, thereby realizing the parallel simulation strategy of the visual modeling mixed rate real-time simulation system.

[0128] Furthermore, in this embodiment, the model development computer (2) includes a graphical modeling environment (2.1) (2.1), a Make file generator (2.3), a model code generator (2.4), a file sender (2.8), an FPGA code generator (2.13), an FPGA compiler (2.14) and an FPGA target code loader (2.16), wherein the graphical modeling environment (2.1) is used to provide a graphical model development environment; the Make file generator (2.3) is used to generate a Make file; the model code generator (2.4) is used to convert a low-speed model file into a high-level language source code; the file sender (2.8) is used to send the high-level language source code and the corresponding Make file to the simulation computer (1); the FPGA code generator (2.13) is used to convert a high-speed model file into an FPGA code; the FPGA compiler (2.14) is used to compile the FPGA code; and the FPGA target code loader is used to load the FPGA target code.

[0129] In this embodiment, the graphical modeling environment (2.1) provided by the visual modeling mixed rate real-time simulation system runs on the model development computer (2), and the mixed model simulation is performed through this graphical environment. During operation, graphical operations such as mouse dragging, copying, pasting, and double-clicking can be used to complete the configuration of operands and operators represented by various graphical symbols, thereby completing the text language compilation corresponding to the logic or algorithm through the graphical operation of the mouse and completing the construction of the model. In addition, this embodiment can configure the simulation environment of the model through the graphical model development environment, thereby completing the configuration of the model simulation and the calculation engine (such as step size, settler, diagnostic options, etc.), and completing the operation control of the simulation (start, pause and end) through mouse operation. In addition, the graphical model development environment of this embodiment can complete the compilation of software models and hardware models separately, and by configuring different source code generators, complete the generation of software source files (such as C language source code files) or hardware FPGA source files (such as VHDL language source code files) from graphical language models, and then by associating different compilers, complete the generation of binary files that can run on a real-time operating system from software language source files, or complete the generation of binary files that can run on FPGA chips from hardware language source files.

[0130] Specifically, in this embodiment, the model development computer (2) adopts a high-speed and low-speed model division strategy, and builds a low-speed model and a high-speed model respectively through a low-speed model development environment and a high-speed model development environment. Among them, the low-speed model development environment includes a graphical modeling environment (2.1), a Make file generator (2.3), a model code generator (2.4) and a file sender (2.8), and the high-speed model development environment includes a graphical modeling environment (2.1), an FPGA code generator (2.13), an FPGA compiler (2.14) and an FPGA target code loader (2.16). The model development computer (2) builds a low-speed model and a high-speed model respectively through a low-speed model development environment and a high-speed model development environment. Among them, the low-speed model building process is as follows:

[0131] The low-speed model file (2.2) output by the graphical modeling environment (2.1) is used as the input of the model code generator (2.4), and the high-level language source code (2.5) ((C / Ada / Fortran) etc.) is output. At the same time, the low-speed model file (2.2) and the Make file template (2.6) are used as the input of the Make file generator (2.3), and the Make file (2.7) is output. Then, the high-level language source code (2.5) and the Make file (2.7) are sent to the simulation computer (1) via the computer local area network (0) through the file sender (2.8). At the same time, the simulation computer (1) transmits the feedback diagnostic information to the graphical modeling environment (2.1) through the computer local area network (0), and displays it in the graphical modeling environment (2.1).

[0132] For the construction of the high-speed model, the high-speed model development environment needs to be combined with the FPGA model machine (8). The FPGA model machine (8) includes an FPGA target code loader (8.01) for loading the FPGA source code model binary file, a FLASH memory (8.02) for storing the loaded FPGA code, an FPGA chip (8.03) for running the FPGA code, and a high-speed data communication interface (8.04) for reading the high-speed model interface data. The high-speed model construction process is as follows:

[0133] The high-speed model model file (2.12) output by the graphical modeling environment (2.1) is used as the input of the FPGA code generator (2.13), and then the FPGA source code (2.11) output by the FPGA code generator (2.13) is used as the input of the FPGA compiler (2.14) to generate the FPGA target code (2.15). The FPGA target code (2.15) is loaded into the FPGA target code loader (8.01) of the FPGA model machine (8) after the FPGA target code loader (2.16) communicates via the computer local area network (0), and is then transferred and stored in the onboard FLASH memory (8.02) of the FPGA model machine (8). After the FPGA model machine (8) is powered on, the FPGA code in the FLASH memory (8.02) is automatically loaded into the FPGA chip (8.03), the high-speed model is executed in parallel, and the high-speed data communication interface (8.04) is continuously refreshed to complete the high-speed reading and writing of data. The FPGA target code loader (8.01) simultaneously completes the loading of the FPGA chip (8.03) and the acquisition of the operating status diagnostic information, and after communicating via the computer local area network (0), it is loaded into the FPGA target code loader (2.16).

[0134] Furthermore, in this embodiment, the simulation machine client computer (3) includes a virtual network console client (3.1), a remote simulation machine desktop interactive interface (3.2) and a human-computer interaction device (3.3). The virtual network console client (3.1) interacts with the simulation computer (1) via the computer local area network (0), the remote simulation machine desktop interactive interface (3.2) is used to provide remote control instructions, and the human-computer interaction device (3.3) is used to provide human-computer control instructions. Its internal process is as follows:

[0135] The human-computer interaction device (3.3) and the remote simulation machine desktop interaction interface (3.2) complete the interaction of operation instructions, transmit the control information to the virtual network console client (3.1) through the remote simulation machine desktop interaction interface (3.2), and receive the interface information of the simulation machine from the virtual network console client (3.1). At the same time, the virtual network console client (3.1) exchanges information with the simulation machine virtual network console server (1.10) of the simulation computer (1) through the computer local area network (0).

[0136] Furthermore, in this embodiment, the automatic test computer (4) includes an operating system terminal (4.3) and a test case transceiver (4.4). The operating system terminal (4.3) is used to load test cases and test case scripts, and call (4.4) the test case transceiver to complete the data transmission of the test case, and complete the use case execution information from the simulation machine running environment scheduling machine (1.9) via the computer local area network (0).

[0137] In addition, in this embodiment, the visual modeling mixed-rate real-time simulation system adopts an operating system with real-time characteristics and triggers real-time simulation through a software timer or a physical clock.

[0138] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but should be granted the widest scope consistent with the principles and novel features disclosed herein.

[0139] Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits, and algorithm steps described in conjunction with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or a combination of the two. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps are generally described above in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. The technician may implement the described functionality in different ways for each specific application, but such implementation decisions should not be interpreted as resulting in a departure from the scope of the present invention.

[0140] The various illustrative logic blocks, modules, and circuits described in conjunction with the embodiments disclosed herein may be implemented or executed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in cooperation with a DSP core, or any other such configuration.

[0141] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software module may reside in a RAM memory, a flash memory, a ROM memory, an EPROM memory, an EEPROM memory, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor so that the processor can read and write information from / to the storage medium. In an alternative, a storage medium may be integrated into a processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In an alternative, the processor and the storage medium may reside in a user terminal as discrete components.

[0142] In one or more exemplary embodiments, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented as a computer program product in software, each function may be stored on or transmitted by a computer-readable medium as one or more instructions or codes. Computer-readable media include both computer storage media and communication media, including any medium that facilitates the transfer of a computer program from one place to another. Storage media may be any available medium that can be accessed by a computer. As an example and not limitation, such a computer-readable medium may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, disk storage or other magnetic storage device, or any other medium that can be used to carry or store the desired program code in the form of an instruction or data structure and can be accessed by a computer. Any connection is also properly referred to as a computer-readable medium. For example, if the software is transmitted from a website, a server, or other remote source using a coaxial cable, a fiber optic cable, a twisted pair, a digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwaves, the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwaves are included in the definition of the medium. Disk and disc as used herein include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc, wherein disk often reproduces data magnetically, while disc reproduces data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

Claims

1. A visual modeling mixed rate real-time simulation system, characterized in that: It includes a simulation computer, a model development computer, a simulation machine client computer, an automatic test computer, a signal conditioning board, a fault injection unit, a unit under test, an FPGA model machine and a clock synchronization machine; among which, The simulation computer is used to complete the loading and operation control of the simulation model; The model development computer is used to complete the programming, development and debugging of the simulation model; The simulation machine client computer is used to complete the operation monitoring of the simulation model; The automatic test computer is used to complete the simulation test drive control of the simulation model in the signal loop; The signal conditioning board is used to convert the digital signal after the simulation model runs into an analog signal; The fault injection unit is used to complete the soft fault and fault injection functions of the fault mode; The unit under test is used to configure the object under test; The FPGA model machine is used to load and run the compiled FPGA source code; The clock synchronization machine is used to complete the clock synchronization during model simulation.

2. The visual modeling mixed rate real-time simulation system according to claim 1, characterized in that: The simulation computer, model development computer, automatic test computer, simulation machine client computer and FPGA model machine constitute a computer local area network, and the deployment and operation of the visual modeling mixed rate real-time simulation system are completed through the constructed computer local area network.

3. The visual modeling mixed rate real-time simulation system according to claim 1, characterized in that: The simulation computer, signal conditioning board, fault injection unit and unit under test are connected one by one in a point-to-point series manner to form a signal loop, and the signal transmission, conversion and closed loop are completed through the constructed signal loop.

4. The visual modeling mixed rate real-time simulation system according to claim 1, characterized in that: The simulation computer includes a simulation control and operating environment, a simulation machine OS terminal, a compiler, a simulation machine operating environment dispatcher, a simulation machine virtual network console server, a human-computer interaction device, a file receiver, and a model interface parser; among them, The simulation control and operation environment is used to provide the simulation computer internal model scheduling, monitoring, test case loading, signal interconnection, model and CPU core mapping functions; The simulator OS terminal is used to provide the simulator operation application program interface; Compilers are used to convert high-level languages ​​into binary target languages; The simulation machine running environment scheduling machine is used to complete the scheduling of the simulation running environment; The emulator virtual network console server is used to provide a emulator client login interface for remote network access; The human-computer interaction device is used to provide a simulation model control operation interface; The file receiver is used to parse the communication signals received through the hardware network interface of the emulator; The model interface parser is used to call the model and convert the called model interface into the model interface encapsulation source code of the new standard interface.

5. The visual modeling mixed rate real-time simulation system according to claim 4, characterized in that: The simulation control and operation environment includes a simulation environment state machine, a model distributor, a model signal interconnector, a model loader, a real-time operation monitor and a use case loader; among them, The simulation environment state machine is used to uniformly schedule the execution of the model distributor, model signal interconnector, model loader, real-time operation monitor and use case loader, and accept the scheduling execution information fed back by the model distributor, model signal interconnector, model loader, real-time operation monitor and use case loader; The model distributor is used to distribute the simulation model; The model signal interconnector is used to complete the interconnection of signals between simulation models; The model loader is used to provide status information of the use case execution; The real-time operation monitor is used to complete the real-time operation monitoring of the simulation model; The use case loader is used to complete the loading of simulation use cases.

6. The visual modeling mixed rate real-time simulation system according to claim 5, characterized in that: The simulation control and running environment statically configures different models to specific CPU cores through the model distributor and establishes the running timing between models. Then, each model is simulated and run according to the model running timing to realize the parallel simulation strategy of the visual modeling mixed-rate real-time simulation system.

7. The visual modeling mixed rate real-time simulation system according to claim 1, characterized in that: The model development computer includes a graphical modeling environment, a Make file generator, a model code generator, a file sender, an FPGA code generator, an FPGA compiler and an FPGA target code loader; wherein, The graphical modeling environment is used to provide a graphical model development environment; The Make file generator is used to generate Make files; The model code generator is used to convert the low-speed model file into high-level language source code; The file sender is used to send the high-level language source code and the corresponding Make file to the simulation computer; FPGA code generator is used to convert high-speed model files into FPGA code; FPGA compiler is used to compile FPGA code; The FPGA target code loader is used to load the FPGA target code.

8. The visual modeling mixed rate real-time simulation system according to claim 7, characterized in that: The model development computer adopts a high-speed and low-speed model division strategy, and builds a low-speed model and a high-speed model respectively through a low-speed model development environment and a high-speed model development environment; wherein, The low-speed model development environment includes a graphical modeling environment, a Make file generator, a model code generator, and a file sender; The high-speed model development environment includes a graphical modeling environment, an FPGA code generator, an FPGA compiler, and an FPGA target code loader.

9. The visual modeling mixed rate real-time simulation system according to claim 1, characterized in that: The simulation machine client computer includes a virtual network console client, a remote simulation machine desktop interactive interface and a human-computer interactive device; wherein, The virtual network console client exchanges information with the simulated computer through the computer local area network; The remote simulation machine desktop interactive interface is used to provide remote control instructions; Human-computer interaction equipment is used to provide human-computer control instructions.

10. The visual modeling mixed rate real-time simulation system according to claim 1, characterized in that: The automatic test computer includes an operating system terminal and a test case transceiver; wherein the operating system terminal is used to load test cases and test case scripts, and call the test case transceiver to complete the data transmission of the test cases.

11. The visual modeling mixed rate real-time simulation system according to claim 1, characterized in that: The FPGA model machine includes an FPGA target code loader, a FLASH memory, an FPGA chip, and a high-speed data communication interface; The FPGA target code loader is used to load the FPGA source code model binary file; The FLASH memory is used to store the FPGA code loaded by the FPGA target code loader; The FPGA chip is used to run the FPGA code stored in the FLASH memory; The high-speed data communication interface is used to read high-speed model interface data.

12. The visual modeling mixed rate real-time simulation system according to claim 1, characterized in that: The visual modeling mixed rate real-time simulation system adopts an operating system with real-time characteristics and triggers real-time simulation through a software timer or a physical clock.

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