Digital low dropout regulator and electronic device using same

Abstract

The invention provides a digital low dropout regulator and an electronic device using the same. The bit low dropout regulator comprises a voltage comparison circuit, a switch control circuit, a power switch module and an asynchronous frequency generation circuit. The voltage comparison circuit is used for comparing a reference voltage with an output voltage and outputting a comparison result signal accordingly. The switch control circuit is used for generating a switch control signal based on the comparison result signal. The power switch module is used for switching a conduction state under the control of a switch control signal so as to adjust the magnitude of the output voltage. The asynchronous frequency generating circuit is used for generating a reference frequency signal which is asynchronous with a system frequency signal used by the load circuit and has a high frequency, so that the switch control circuit can update the output switch control signal based on the reference frequency signal.

Description

Technical Field

[0001] The invention relates to a voltage stabilizing circuit technology, and in particular to a digital low voltage dropout regulator and an electronic device using the same. Background Art

[0002] Different electronic devices have different supply voltage requirements, so the conversion of supply voltage has always been an important research field. Voltage conversion can generally be divided into two ways: switching regulator and linear regulator. Linear regulators have their advantages, such as fast response to input voltage or load changes, low output voltage ripple and noise, simple circuit structure, small size, and relatively low price. Digital low-dropout linear regulators (DLDO) have become the main choice for low-power step-down and voltage stabilization circuits due to their improved conversion efficiency, small size and low noise.

[0003] In the traditional digital low-dropout regulator circuit design, the voltage regulation speed is mainly determined by the system frequency. However, the system frequency speed cannot be set too high because the power consumption of the entire device must also be considered. Therefore, the voltage regulation speed of the traditional digital low-dropout regulator is difficult to improve because it is limited by the system frequency speed. Summary of the invention

[0004] The present application provides a digital low voltage dropout regulator and an electronic device using the same, which can more quickly respond to changes in load current to adjust the output voltage so that the output voltage can be stabilized at a reference voltage at any time.

[0005] The present application provides a digital low-dropout regulator suitable for regulating the output voltage provided to a load circuit. The digital low-dropout regulator includes a voltage comparison circuit, a switch control circuit, a power switch module, and an asynchronous frequency generation circuit. The voltage comparison circuit is used to compare a reference voltage with an output voltage, and output a comparison result signal accordingly. The switch control circuit is coupled to the voltage comparison circuit to generate a switch control signal based on the comparison result signal. The power switch module is used to switch the conduction state under the control of the switch control signal to adjust the magnitude of the output voltage. The asynchronous frequency generation circuit is coupled to the switch control circuit and the voltage comparison circuit to generate a reference frequency signal that is not synchronized with the system frequency signal used by the load circuit. The switch control circuit updates the output switch control signal based on the reference frequency signal so that the output voltage approaches the reference voltage. The frequency of the reference frequency signal is higher than the frequency of the system frequency signal.

[0006] The present application provides an electronic device, including a load circuit and a digital low-dropout regulator. The load circuit is used to perform a load function based on an output voltage and a system frequency signal. The digital low-dropout regulator is coupled to the load circuit and is used to adjust the output voltage provided to the load circuit based on a reference frequency signal so that the output voltage approaches the reference voltage. The reference frequency signal is triggered when the level of the system frequency signal changes, and the frequency of the reference frequency signal is higher than the frequency of the system frequency signal.

[0007] Based on the above, the digital low-dropout voltage regulator of the present application and the electronic device using the same can provide a reference frequency signal with a higher frequency relative to the system frequency signal as a reference timing for the digital low-dropout voltage regulator to perform voltage regulation. Therefore, the digital low-dropout voltage regulator of the embodiment of the present application can adjust the output voltage more quickly so that the output voltage can be stably maintained close to the reference voltage. In addition, since the trigger time, frequency and number of pulses of the reference frequency signal of the embodiment of the present application can be programmed, rapid voltage regulation can be performed only within the time interval when the output voltage may change significantly, and there is no need to continuously send high-frequency pulses at all times. Therefore, it can take into account the power consumption performance of the electronic device and improve the stability of the overall power supply. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A functional block diagram of an electronic device and a digital low dropout regulator thereof according to an embodiment of the present application is shown;

[0009] Figure 2A FIG. 1 is a circuit diagram of a digital low dropout regulator according to an embodiment of the present application;

[0010] Figure 2B Plotted as Figure 2A A signal timing diagram of a digital low dropout regulator of an embodiment;

[0011] Figure 3A A circuit diagram of a digital low dropout regulator according to another embodiment of the present application is shown; and

[0012] Figure 3B Plotted as Figure 3A A signal timing diagram of a digital low dropout regulator according to an embodiment. DETAILED DESCRIPTION

[0013] The present application proposes a new digital low dropout regulator and an electronic device using the same to solve the problems mentioned in the background technology. In order to make the features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. The following description contains specific information related to the exemplary embodiments in the present application. The drawings and the accompanying detailed descriptions in the present application are only exemplary embodiments. However, the present application is not limited to these exemplary embodiments. Those skilled in the art will think of other variations and embodiments of the present application. Unless otherwise specified, the same or corresponding components in the drawings may be indicated by the same or corresponding figure numbers. In addition, the drawings and illustrations in the present application are generally not drawn to scale and are not intended to correspond to actual relative sizes.

[0014] Figure 1 This is a functional block diagram of an electronic device and a digital low dropout regulator according to an embodiment of the present application. Figure 1 The electronic device 10 of this embodiment may be a microcontroller (MCU), a digital signal processor (DSP) or a digital circuit such as an FPGA, but the present application is not limited thereto. The electronic device 10 includes a load circuit 50 and a digital low dropout regulator 100 .

[0015] The load circuit 50 receives the output voltage VOUT from its power supply terminal and performs a load function based on the output voltage VOUT and the system frequency signal CLK_SYS, wherein the load circuit 50 may be, for example, a transmission module, an access controller, a memory module, a power management module, a sensor or a peripheral input / output device, etc., but the present application is not limited thereto. The digital low-dropout regulator 100 is coupled to the power supply terminal of the load circuit 50 to adjust the output voltage VOUT provided to the load circuit 50 so that the output voltage VOUT approaches the set reference voltage VREF.

[0016] The digital low dropout regulator 100 controls the on / off of multiple power switches based on the relative relationship between the current output voltage VOUT and the reference voltage VREF, and further adjusts the output voltage VOUT provided to the load circuit 50 by controlling the charging and discharging of the output capacitor COUT.

[0017] In the present embodiment, the digital low-dropout regulator 100 uses a reference frequency signal CLK_ASYN that is not synchronized with the system frequency signal CLK_SYS as a reference timing for voltage regulation. In other words, the voltage regulation speed of the digital low-dropout regulator 100 is determined based on the frequency of the reference frequency signal CLK_ASYN, wherein the frequency of the reference frequency signal CLK_ASYN is higher than the frequency of the system frequency signal CLK_SYS. Therefore, compared to a digital low-dropout regulator that uses the system frequency signal CLK_SYS for voltage regulation, the digital low-dropout regulator 100 of the present embodiment can more quickly regulate the output voltage VOUT to be close to the reference voltage VREF.

[0018] Specifically, the digital low dropout regulator 100 includes a voltage comparison circuit 110, a switch control circuit 120, a power switch module 130, and an asynchronous frequency generation circuit 140. An input terminal of the voltage comparison circuit 110 is coupled to the power terminal of the load circuit 50 to receive the output voltage VOUT, wherein the voltage comparison circuit 110 compares the reference voltage VREF with the output voltage, and outputs a comparison result signal SCR according to the comparison result.

[0019] The switch control circuit 120 is coupled to the voltage comparison circuit 110 and is used to generate a switch control signal SCTL based on the comparison result signal SCR, wherein the switch control circuit 120 updates the switch control signal SCTL based on the comparison result signal SCR in each cycle of the reference clock signal CLK_ASYN. In this embodiment, the switch control signal SCTL can be a signal of multiple bits, and the number of bits corresponds to the number of power switches included in the power switch module 130.

[0020] The power switch module 130 is coupled to the output terminal of the switch control circuit 120 to receive the switch control signal SCTL, and is used to switch the conduction state under the control of the switch control signal SCTL to adjust the magnitude of the output voltage VOUT. In this embodiment, the power switch module 130 may include a plurality of power switches connected in parallel, the plurality of power switches are connected in series between the power supply voltage VDD and the output capacitor COUT, and the control terminals of the plurality of power switches may respectively receive corresponding signals in the switch control signal SCTL.

[0021] For example, if the power switch module 130 includes 4 power switches, the switch control signal SCTL may be, for example, a 4-bit signal, wherein the 4 power switches may respectively receive the first to fourth bits of the switch control signal SCTL to determine whether to be turned on or off. For example, if the switch control signal SCTL is a signal of (1, 0, 0, 0), the signal with a bit value of "1" may represent an enable signal for turning on the power switch, and the signal with a bit value of "0" may represent a disable signal for turning off the power switch. Therefore, when the power switch module 130 receives the switch control signal SCTL of (1, 0, 0, 0), the power switch receiving the enable signal will be turned on, and the other power switches receiving the disable signal will be turned off.

[0022] The asynchronous frequency generating circuit 140 is coupled to the switch control circuit 120 and the voltage comparison circuit 110 , and is used to generate a reference frequency signal CLK_ASYN which is asynchronous with the system frequency signal CLK_SYS used by the load circuit 50 and has a higher frequency.

[0023] In this embodiment, since the switch control circuit 120 updates the generated switch control signal SCTL based on the reference frequency signal CLK_ASYN with a higher frequency, the digital low dropout regulator 100 can adjust the output voltage VOUT more quickly so that the output voltage VOUT can be stably maintained close to the reference voltage VREF.

[0024] In addition, since the load circuit 50 usually triggers its load function in response to the rising edge / falling edge of the system clock signal CLK_SYS, when the level of the system clock signal CLK_SYS changes, there will usually be a larger change in the load current ILOAD, causing the output voltage VOUT to be unstable.

[0025] In some embodiments, in order to better maintain power supply stability, the asynchronous frequency generating circuit 140 can also be designed to generate a reference frequency signal CLK_ASYN based on the level change of the system frequency signal CLK_SYS, so that the digital low-dropout regulator 100 performs rapid voltage regulation at the rising edge / falling edge of the system frequency signal CLK_SYS, so as to quickly regulate the output voltage VOUT to be stable based on the higher frequency reference frequency signal CLK_ASYN during the period when the output voltage VOUT may fluctuate.

[0026] In other words, the asynchronous frequency generating circuit 140 of the present embodiment can generate a predetermined number of pulses as a reference timing for the switch control circuit 120 to generate the switch control signal SCTL only within a trigger period when the rising edge and / or falling edge of the system clock signal CLK_SYS occurs, wherein the length of the trigger period and the predetermined number can be selected based on the circuit design of the asynchronous frequency generating circuit 140.

[0027] In this way, since the digital low dropout regulator 100 can only perform rapid voltage regulation during the time period when the output voltage VOUT may vary significantly, it does not need to continuously send high-frequency pulses at all times. Therefore, it can take into account the power consumption performance of the electronic device 10 while also improving the stability of the overall power supply.

[0028] Below FIG. 2A to FIG. 3B The digital low dropout regulator 100 and the electronic device using the same are specifically described with reference to different circuit embodiments.

[0029] Please refer to Figure 2A and Figure 2B ,in Figure 2A is a circuit diagram of a digital low dropout regulator according to an embodiment of the present application, and Figure 2B for Figure 2A The digital low dropout regulator 200 of the present embodiment is used to adjust the output voltage VOUT provided to the load circuit 50 , and includes a voltage comparison circuit 210 , a switch control circuit 220 , a power switch module 230 and an asynchronous frequency generation circuit 240 .

[0030] The voltage comparison circuit 210 of the present embodiment may be implemented, for example, by an error amplifier (hereinafter referred to as "error amplifier 210" for explanation), but the present application is not limited thereto. The error amplifier 210 may be used to compare the voltages received at its two input terminals (i.e., the output voltage VOUT and the reference voltage VREF), and output a comparison result signal SCR according to the comparison result. The error amplifier 210 may determine the time point for comparing the output voltage VOUT with the reference voltage VREF based on the reference frequency signal CLK_ASYN. For example, when the output voltage VOUT is greater than the reference voltage VREF, the error amplifier 210 may output a disabled comparison result signal SCR (e.g., a low level); conversely, when the output voltage VOUT is less than the reference voltage VREF, the error amplifier 210 outputs an enabled comparison result signal SCR.

[0031] The switch control circuit 220 of the present embodiment includes, for example, a bidirectional shift register 222 and a plurality of buffers BF1-BFn. The bidirectional shift register 222 generates a multi-bit signal according to the comparison result signal SCR, and updates the multi-bit signal based on the frequency of the reference frequency signal CLK_ASYN. The buffers BF1-BFn are coupled to the output end of the bidirectional shift register 222 to receive each bit signal of the multi-bit signal respectively, and are used to adjust each bit signal into a control signal Sc1-Scn that can be used to drive the power switches M1-Mn at the rear end.

[0032] The power switch module 230 of the present embodiment includes, for example, n power switches M1-Mn, where n can be a positive integer greater than 1. The power switches M1-Mn have a first terminal, a second terminal, and a control terminal, wherein the first terminals of the power switches M1-Mn receive the power supply voltage VDD; the second terminals of the power switches M1-Mn are coupled to the load circuit 50 and the output capacitor COUT; and the control terminals of the power switches M1-Mn are respectively coupled to the output terminals of the buffers BF1-BFn to receive corresponding control signals Sc1-Scn, and are turned on or off in response to the received control signals Sc1-Scn.

[0033] The asynchronous frequency generating circuit 240 of the present embodiment will trigger and generate a pulse group consisting of k pulses as the reference frequency signal CLK_ASYN at the rising edge RE and the falling edge FE of the system frequency signal CLK_SYS, wherein the pulse group occurs within the trigger period Ttr, and the pulse period T2 of the pulse group will be less than the completion of the system frequency signal CLK_SYS. In other words, when the system frequency signal CLK_SYS triggers the asynchronous frequency generating circuit 240 to generate the reference frequency signal CLK_ASYN, the asynchronous frequency generating circuit 240 will generate a pulse group as the reference frequency signal CLK_ASYN within the trigger period Ttr, wherein the frequency of the reference frequency signal CLK_ASYN will be higher than the frequency of the system frequency signal CLK_SYS. In the present embodiment, the pulse period T1 may be, for example, greater than 10ns, and the pulse period T2 may be, for example, less than or equal to 10ns, for example, between 2ns and 10ns, but the present application is not limited thereto.

[0034] In terms of the overall operation of the digital low dropout regulator 200 , when the level of the system clock signal CLK_SYS changes, the asynchronous frequency generating circuit 240 will be triggered to generate k pulses, so that the error amplifier 210 and the bidirectional shift register 222 work according to the k pulses.

[0035] During the period when the error amplifier 210 and the bidirectional shift register 222 work with reference to the k pulses, the error amplifier 210 outputs a disabled comparison result signal SCR when the output voltage VOUT is greater than the reference voltage VREF, so that the bidirectional shift register 222 outputs a corresponding byte signal based on the disabled comparison result signal SCR. After receiving the byte signal, the buffers BF1-BFn generate corresponding control signals Sc1-Scn to turn off one of the previously turned-on power switches M1-Mn, thereby reducing the output voltage VOUT.

[0036] On the other hand, the error amplifier 210 will output the enabled comparison result signal SCR when the output voltage VOUT is less than the reference voltage VREF, so that the bidirectional shift register 222 outputs the corresponding byte signal based on the enabled comparison result signal SCR-. After receiving the byte signal, the buffers BF1-BFn will generate corresponding control signals Sc1-Scn to turn on one of the previously closed power switches M1-Mn, thereby increasing the output voltage VOUT.

[0037] In this embodiment, the pulse number k, pulse period T2 and trigger period Ttr of the pulse group can be set and adjusted. That is, the designer can adjust the circuit design of the asynchronous frequency generating circuit 240 according to the actual voltage regulation required by the electronic device, so that the reference frequency signal CLK_ASYN conforms to the set format, thereby allowing the digital low dropout regulator 200 to perform voltage regulation according to the required timing.

[0038] In some embodiments, if the rising edge RE or the falling edge FE of the system frequency signal CLK_SYS occurs within the trigger period Ttr of generating the pulse group, the asynchronous frequency generating circuit 240 can reset the reference frequency signal CLK_ASYN so that the asynchronous frequency generating circuit 240 re-issues k pulses for voltage regulation, and the trigger period Ttr will also be restarted.

[0039] Next refer to Figure 3A and Figure 3B ,in Figure 3A is a circuit diagram of a digital low dropout regulator according to another embodiment of the present application, and Figure 3B for Figure 3A A signal timing diagram of a digital low dropout regulator according to an embodiment.

[0040] The digital low dropout regulator 300 of the present embodiment includes a voltage comparison circuit 310, a switch control circuit 320, a power switch module 330 and an asynchronous frequency generation circuit 340. The configuration and operation of the switch control circuit 320, the power switch module 330 and the asynchronous frequency generation circuit 340 are similar to those of the aforementioned Figure 2AThe switch control circuit 220, the power switch module 230 and the asynchronous frequency generating circuit 240 are described in detail, so the related descriptions can refer to the descriptions of the above embodiments and will not be repeated here.

[0041] This embodiment and the aforementioned Figure 2A and Figure 2B The difference between the embodiments is that the voltage comparison circuit 310 of the present embodiment outputs a comparison completion signal SCF to the asynchronous frequency generation circuit 340 after the comparison is completed. The asynchronous frequency generation circuit 340 can determine the frequency of the reference clock signal CLK_ASYN according to the comparison completion signal SCF.

[0042] For example, the voltage comparison circuit 310 may output an enabled comparison completion signal SCF (e.g., a pulse) after completing the comparison. On the other hand, the asynchronous frequency generation circuit 340 maintains the reference frequency signal CLK_ASYN at a low level after issuing the pulse. The asynchronous frequency generation circuit 340 will trigger the generation of the next pulse only when it receives the enabled comparison completion signal SCF.

[0043] In other words, in this embodiment, the asynchronous clock generating circuit 240 not only determines the time point of generating the pulse group based on the level change of the system clock signal CLK_SYS, but also determines the time interval between two adjacent pulses in the pulse group based on the comparison completion signal SCF that is enabled.

[0044] In summary, the digital low-dropout voltage regulator of the present application and the electronic device using the same can provide a reference frequency signal with a higher frequency relative to the system frequency signal as a reference timing for the digital low-dropout voltage regulator to perform voltage regulation. Therefore, the digital low-dropout voltage regulator of the embodiment of the present application can adjust the output voltage more quickly so that the output voltage can be stably maintained close to the reference voltage. In addition, since the trigger time, frequency and number of pulses of the reference frequency signal of the embodiment of the present application can be programmed, rapid voltage regulation can be performed only within the time interval when the output voltage may change significantly, and there is no need to continuously send high-frequency pulses at all times. Therefore, it can take into account the power consumption performance of the electronic device and improve the stability of the overall power supply.

[0045] Although the present application has been disclosed using the above-mentioned embodiments, they are not intended to limit the present application. Any person skilled in the art may make various changes and modifications to the above-mentioned embodiments without departing from the spirit and scope of the present application, and the changes and modifications still fall within the technical scope protected by the present application. Therefore, the scope of protection of the present application shall be based on the definition of the claims.

Claims

1. A digital low dropout regulator, characterized in that: Suitable for regulating an output voltage provided to a load circuit, the digital low dropout regulator comprises: a voltage comparison circuit, used for comparing a reference voltage with the output voltage, and outputting a comparison result signal accordingly; a switch control circuit, coupled to the voltage comparison circuit, for generating a switch control signal based on the comparison result signal; a power switch module, configured to be controlled by the switch control signal to switch the conduction state, so as to adjust the magnitude of the output voltage; and an asynchronous frequency generating circuit, coupled to the switch control circuit and the voltage comparison circuit, for generating a reference frequency signal that is asynchronous with a system frequency signal used by the load circuit, The switch control circuit updates the output switch control signal based on the reference frequency signal so that the output voltage approaches the reference voltage. The frequency of the reference frequency signal is higher than the frequency of the system frequency signal.

2. The digital low dropout regulator according to claim 1, characterized in that: The asynchronous frequency generating circuit triggers the generation of the reference frequency signal in response to at least one of a rising edge and a falling edge of the system frequency signal.

3. The digital low dropout regulator according to claim 2, characterized in that: When the system frequency signal triggers the asynchronous frequency generating circuit to generate the reference frequency signal, the asynchronous frequency generating circuit generates a pulse group as the reference frequency signal within a triggering period.

4. The digital low dropout regulator according to claim 3, characterized in that: When the system frequency signal changes its level within the trigger period, the asynchronous frequency generating circuit resets the reference frequency signal to restart the trigger period.

5. The digital low dropout regulator according to claim 1, characterized in that: The voltage comparison circuit determines a time point for comparing the output voltage with the reference voltage based on the reference frequency signal, and the voltage comparison circuit outputs a comparison completion signal to the asynchronous frequency generation circuit after completing the comparison.

6. An electronic device, characterized in that: include: A load circuit for performing a load function based on an output voltage and a system frequency signal; as well as a digital low dropout regulator, coupled to the load circuit, for adjusting the output voltage provided to the load circuit based on a reference frequency signal so that the output voltage approaches a reference voltage, The reference frequency signal is triggered when the level of the system frequency signal changes, and the frequency of the reference frequency signal is higher than the frequency of the system frequency signal.

7. The electronic device according to claim 6, characterized in that: The digital low dropout regulator comprises: a voltage comparison circuit, used for comparing the reference voltage with the output voltage, and outputting a comparison result signal accordingly; a switch control circuit, coupled to the voltage comparison circuit, for generating a switch control signal based on the comparison result signal; a power switch module, configured to be controlled by the switch control signal to switch the conduction state, so as to adjust the magnitude of the output voltage; and An asynchronous frequency generating circuit is coupled to the switch control circuit and the voltage comparison circuit, and is used for generating the reference frequency signal based on the level change of the system frequency signal.

8. The electronic device according to claim 7, characterized in that: The voltage comparison circuit determines a time point for comparing the output voltage with the reference voltage based on the reference frequency signal, and the voltage comparison circuit outputs a comparison completion signal to the asynchronous frequency generation circuit after completing the comparison.

9. The electronic device according to claim 8, characterized in that: The asynchronous frequency generating circuit is triggered to generate a pulse group as the reference frequency signal within a triggering period in response to at least one of a rising edge and a falling edge of the system frequency signal.

10. The electronic device according to claim 9, characterized in that: The asynchronous frequency generating circuit determines a time point for generating the pulse group based on the system frequency signal, and determines a time interval between each pulse in the pulse group based on the comparison completion signal.

Images