Low voltage difference linear voltage stabilizing circuit, voltage stabilizing method and voltage stabilizer

Abstract

The present application provides a low voltage difference linear voltage stabilization circuit, a voltage stabilization method and a voltage stabilizer, which are applied to the field of integrated circuit technology, wherein the circuit includes a voltage input terminal, a voltage output terminal, a current source, an error amplifier A1, a feedback network and a power tube; the voltage input terminal is respectively connected to one end of the current source and the first end of the power tube; the other end of the current source is respectively connected to the first end of the feedback network and the negative input terminal of the error amplifier A1; the positive input terminal of the error amplifier A1 is connected to the second end of the feedback network; the output terminal of the error amplifier A1 is connected to the second end of the power tube; the third end of the power tube is respectively connected to the voltage output terminal and the third end of the feedback network. Compared with the traditional LDO circuit architecture, the present application omits the reference voltage generation circuit Vref and the feedback resistor network, reduces the generation of additional current, reduces the area of ​​the circuit and reduces power consumption.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a low voltage difference linear voltage regulator circuit, a voltage regulator method and a voltage regulator. Background Art

[0002] Low-dropout linear regulator circuit, also known as LDO circuit, is a common module in integrated circuits and is often used to convert the high-voltage power supply in the system into a stable power supply in the low-voltage domain, such as Figure 1 As shown, it is usually composed of a reference voltage generating circuit Vref, an error amplifier A1, a power tube M1 and a feedback network R1 / 2. The basic principle is that the error amplifier A1 is used to clamp the Vref voltage and the resistor feedback voltage, and M1 is used to provide output current, so that the output voltage VOUT = R2 / (R1+R2)*Vref, providing a stable voltage that is independent of the input voltage VIN for other modules. It can be seen that a reference voltage generating circuit Vref is required in traditional LDOs. This circuit is usually formed based on a bandgap reference, which not only generates additional current but also increases the area of ​​the circuit.

[0003] Based on this, a new technical solution is needed. Summary of the invention

[0004] In view of this, the present application provides a low voltage difference linear voltage regulator circuit, a voltage regulator method and a voltage regulator.

[0005] This application provides the following technical solutions:

[0006] A low voltage difference linear voltage regulator circuit provided in the present application includes a voltage input terminal, a voltage output terminal, a current source, an error amplifier A1, a feedback network and a power tube;

[0007] The voltage input end is respectively connected to one end of the current source and the first end of the power tube;

[0008] The other end of the current source is connected to the first end of the feedback network and the negative input end of the error amplifier A1 respectively; the positive input end of the error amplifier A1 is connected to the second end of the feedback network; the output end of the error amplifier A1 is connected to the second end of the power tube;

[0009] The third end of the power tube is respectively connected to the voltage output end and the third end of the feedback network.

[0010] Preferably, the feedback network includes a circuit consisting of a plurality of field effect transistors.

[0011] Preferably, the feedback network includes a first N-channel field effect transistor NM1, a second N-channel field effect transistor NM2 and a second P-channel field effect transistor PM2; the power transistor is the first P-channel field effect transistor PM1;

[0012] The drain of the first N-channel field effect transistor NM1 serves as the first end of the feedback network, and the drain of the first N-channel field effect transistor NM1 is respectively connected to the gate of the first N-channel field effect transistor NM1 and the gate of the second N-channel field effect transistor NM2; the source of the first N-channel field effect transistor NM1 is connected to the source of the second N-channel field effect transistor NM2;

[0013] The gate of the second P-channel field effect transistor PM2 serves as the second end of the feedback network, and the gate of the second P-channel field effect transistor PM2 is respectively connected to the drain of the second P-channel field effect transistor PM2 and the drain of the second N-channel field effect transistor NM2; the source of the second P-channel field effect transistor PM2 serves as the third end of the feedback network;

[0014] The source of the first P-channel field effect transistor PM1 serves as the first end of the power transistor, the gate of the first P-channel field effect transistor PM1 serves as the second end of the power transistor, and the drain of the first P-channel field effect transistor PM1 serves as the third end of the power transistor.

[0015] Preferably, the magnitude of the reference current I1 of the current source is adjustable, and the magnitude of the output voltage VOUT of the voltage output terminal is adjusted by adjusting the magnitude of the reference current I1.

[0016] Preferably, the sizes of the second P-channel field effect transistor PM2 and the first N-channel field effect transistor NM1 are adjustable, and the output voltage VOUT of the voltage output end is adjusted by adjusting the sizes of the second P-channel field effect transistor PM2 and the first N-channel field effect transistor NM1.

[0017] Preferably, the error amplifier A1 comprises a normally operating amplifier, so that according to the clamping action of the error amplifier A1 , the voltage at the negative input terminal of the error amplifier A1 is equal to the voltage at the positive input terminal of the error amplifier A1 .

[0018] Preferably, the voltage stabilizing circuit enables the output voltage of the voltage output end to be adaptively adjusted following different process angles. Under a slow process angle, the threshold voltage Vth of the N-channel field effect transistor and the P-channel field effect transistor increases, causing the gate-source voltage Vgs to increase, and the output voltage VOUT of the voltage output end increases accordingly. Under a fast process angle, the threshold voltage Vth of the N-channel field effect transistor and the P-channel field effect transistor decreases, causing the gate-source voltage Vgs to decrease, and the output voltage VOUT of the voltage output end decreases accordingly.

[0019] A voltage stabilization method provided in the present application is characterized in that a low voltage difference linear voltage stabilization circuit is applied; the current source generates a reference current I1, and the output voltage VOUT of the voltage output end is adjusted by adjusting the size of the reference current I1 and / or adjusting the size of the second P-channel field effect transistor PM2 and the first N-channel field effect transistor NM1.

[0020] In one embodiment, the output voltage of the voltage output terminal is adaptively adjusted following different process angles. Under a slow process angle, the threshold voltage Vth of the N-channel field effect transistor and the P-channel field effect transistor increases, causing the gate-source voltage Vgs to increase, and the output voltage VOUT of the voltage output terminal increases accordingly. Under a fast process angle, the threshold voltage Vth of the N-channel field effect transistor and the P-channel field effect transistor decreases, causing the gate-source voltage Vgs to decrease, and the output voltage VOUT of the voltage output terminal decreases accordingly.

[0021] A voltage stabilizer provided according to the present application includes any of the low voltage difference linear voltage stabilizer circuits described above.

[0022] Compared with the prior art, the beneficial effects that can be achieved by at least one of the above technical solutions adopted in the present application include at least:

[0023] Compared with the traditional LDO circuit architecture, the present application omits the reference voltage generating circuit Vref and the feedback resistor network, reduces the generation of additional current, reduces the circuit area and reduces power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 is a schematic diagram of a conventional low dropout linear regulator circuit architecture;

[0026] Figure 2 is a schematic diagram of the circuit architecture of the low dropout linear regulator of the present application. DETAILED DESCRIPTION

[0027] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0028] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0029] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspect described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0030] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0031] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the examples can be practiced without these specific details.

[0032] The applicant has conducted in-depth research and improved exploration on low voltage difference linear voltage regulator circuits and found that: the traditional LDO also requires a resistor feedback network. When low static current is required, this resistor is usually very large, which increases the circuit area. Finally, the output voltage of the traditional LDO is usually stable at different process angles. For example, when used to power digital circuits, the output voltage of the LDO will be designed to cover the minimum voltage for the digital circuit to work normally at all process angles and leave a certain margin. Usually, at a slow process angle, the required power supply voltage is higher, and at a fast process angle, the required power supply voltage is lower. Therefore, if the power supply voltage required at the slow process angle is designed, for the fast process angle, the excessively high power supply voltage means a waste of power consumption.

[0033] Based on this, the technical solutions provided by the embodiments of the present application are described below in conjunction with the accompanying drawings.

[0034] The embodiment of this specification proposes a low voltage drop linear regulator circuit, such as Figure 2 As shown, it includes a voltage input terminal, a voltage output terminal, a current source, an error amplifier A1, a feedback network and a power tube.

[0035] The voltage input end is respectively connected to the input end of the current source and the first end of the power tube; the output end of the current source is respectively connected to the first end of the feedback network and the negative input end of the error amplifier A1; the positive input end of the error amplifier A1 is connected to the second end of the feedback network; the output end of the error amplifier A1 is connected to the second end of the power tube; the third end of the power tube is respectively connected to the voltage output end and the third end of the feedback network.

[0036] The current source generates a reference current I1, and the power tube is used to provide an output current.

[0037] In one embodiment, if Figure 2 As shown, the feedback network includes a circuit composed of multiple field effect transistors. The field effect transistors include N-channel field effect transistors and P-channel field effect transistors.

[0038] In one embodiment, if Figure 2 As shown, the feedback network includes a first N-channel field effect transistor NM1, a second N-channel field effect transistor NM2 and a second P-channel field effect transistor PM2; the power transistor is the first P-channel field effect transistor PM1.

[0039] The drain of the first N-channel field effect transistor NM1 serves as the first end of the feedback network, and the drain of the first N-channel field effect transistor NM1 is respectively connected to the gate of the first N-channel field effect transistor NM1 and the gate of the second N-channel field effect transistor NM2; the source of the first N-channel field effect transistor NM1 is connected to the source of the second N-channel field effect transistor NM2.

[0040] The gate of the second P-channel field effect transistor PM2 serves as the second end of the feedback network, and the gate of the second P-channel field effect transistor PM2 is respectively connected to the drain of the second P-channel field effect transistor PM2 and the drain of the second N-channel field effect transistor NM2; the source of the second P-channel field effect transistor PM2 serves as the third end of the feedback network.

[0041] The source of the first P-channel field effect transistor PM1 serves as the first end of the power transistor, the gate of the first P-channel field effect transistor PM1 serves as the second end of the power transistor, and the drain of the first P-channel field effect transistor PM1 serves as the third end of the power transistor.

[0042] The power tube is used to provide output current, that is, the first P-channel field effect tube PM1 provides output current.

[0043] In one embodiment, if Figure 2 As shown, the magnitude of the reference current I1 of the current source can be adjusted, and the magnitude of the output voltage VOUT of the voltage output terminal can be adjusted by adjusting the magnitude of the reference current I1.

[0044] In one embodiment, if Figure 2 As shown, the sizes of the second P-channel field effect transistor PM2 and the second N-channel field effect transistor NM2 are adjustable, and the size of the output voltage VOUT of the voltage output terminal is adjusted by adjusting the sizes of the second P-channel field effect transistor PM2 and the second N-channel field effect transistor NM2.

[0045] In one embodiment, if Figure 2 As shown, the error amplifier A1 includes a normally working amplifier, so that according to the clamping action of the error amplifier A1, the voltage at the negative input terminal of the error amplifier A1 is equal to the voltage at the positive input terminal of the error amplifier A1. The error amplifier A1 of the present application can be any amplifier that can work normally.

[0046] In one embodiment, if Figure 2 As shown, the voltage stabilizing circuit enables the output voltage of the voltage output end to be adaptively adjusted following different process angles. Under a slow process angle, the threshold voltage Vth of the N-channel field effect transistor and the P-channel field effect transistor increases, causing the gate-source voltage Vgs to increase, and the output voltage VOUT of the voltage output end increases accordingly. Under a fast process angle, the threshold voltage Vth of the N-channel field effect transistor and the P-channel field effect transistor decreases, causing the gate-source voltage Vgs to decrease, and the output voltage VOUT of the voltage output end decreases accordingly.

[0047] The present application is a low voltage drop linear regulator circuit with low power consumption and small area. Figure 2As shown, the LDO circuit architecture of the present application is composed of a reference current I1, an error amplifier A1, a feedback network NM1 / NM2 / PM2, and a power tube PM1, and PM1 is used to provide an output current. It can be seen that compared with the traditional LDO circuit architecture, the reference voltage generating circuit Vref and the feedback resistor network are omitted, and the reference current I1 itself is also required in the error amplifier A1, so there is no extra reference current circuit, so the LDO of the present application has advantages in power consumption and area. Due to the clamping effect of the error amplifier A1, the Va voltage is equal to the Vb voltage, Vb=Va=Vgsn, VOUT=Vb+Vgsp=Vgsn+Vgsp, so the LDO output voltage of the present application is the sum of the Vgs voltages of PMOS and NMOS, for example, the sum of the Vgs voltages of PM2 and NM1, that is, the output voltage can be adjusted by adjusting the size of the reference current I1, or adjusting the size of NM1 and PM2. It can be seen from the expression of the output voltage that the output voltage of the LDO is different at different process angles. At a slow process angle, since the vth of NMOS and PMOS increases, such as PM2 and NM1, Vgs also increases, and the output voltage of the LDO also increases. At a fast process angle, since the Vth of NMOS and PMOS decreases, Vgs also decreases, and the output voltage of the LDO also decreases. The output of the LDO can be automatically adjusted as the process angle changes, which is an adaptive process. Since the minimum operating voltage of the digital circuit is related to the Vth of MOS, the minimum operating voltage at different process angles is different. If the LDO of the present application is used to power the digital circuit, the output voltage of the LDO automatically follows the process angle, that is, automatically follows its minimum operating voltage, to avoid waste of power consumption. In addition, in some embodiments, the size of the output voltage can also be adjusted by adjusting the size of NM2 and PM2.

[0048] Wherein, Va represents the voltage at the negative input terminal of the error amplifier A1; Vb represents the voltage at the positive input terminal of the error amplifier A1; Vc represents the voltage at the output terminal of the error amplifier A1; Vgsn represents the gate-source voltage of the N-channel field effect transistor, for example, the gate-source voltage of the first N-channel field effect transistor NM1; Vgsp represents the gate-source voltage of the P-channel field effect transistor, for example, the gate-source voltage of the second P-channel field effect transistor PM2; PMOS represents the P-channel field effect transistor; NMOS represents the N-channel field effect transistor; Vth represents the threshold voltage, and Vgs represents the gate-source voltage. VOUT represents the output voltage of the voltage output terminal, and VIN represents the input voltage of the voltage input terminal.

[0049] The LDO of the present application has two advantages over the traditional LDO. First, the circuit is simple and small in area, and the reference voltage generation circuit and the resistor feedback network are omitted. Second, the output voltage is the sum of the Vgs of NMOS and PMOS, and can automatically follow the changes in the process angle to adapt to the minimum operating voltage required by the digital circuit under different process angles, thereby achieving the purpose of saving power consumption.

[0050] The present specification also discloses a voltage stabilization method. Figure 2 As shown, a low voltage difference linear voltage regulator circuit using any of the above embodiments is applied; the current source generates a reference current I1, and the output voltage VOUT of the voltage output terminal is adjusted by adjusting the size of the reference current I1 and / or adjusting the size of the second P-channel field effect transistor PM2 and the first N-channel field effect transistor NM1.

[0051] In one embodiment, if Figure 2 As shown, the output voltage of the voltage output end is adaptively adjusted following different process angles. Under a slow process angle, the threshold voltage Vth of the N-channel field effect transistor and the P-channel field effect transistor increases, causing the gate-source voltage Vgs to increase, and the output voltage VOUT of the voltage output end increases accordingly. Under a fast process angle, the threshold voltage Vth of the N-channel field effect transistor and the P-channel field effect transistor decreases, causing the gate-source voltage Vgs to decrease, and the output voltage VOUT of the voltage output end decreases accordingly.

[0052] The present specification also provides a voltage stabilizer, such as Figure 2 As shown, it includes a low voltage difference linear voltage regulator circuit of any one of the above embodiments.

[0053] In this specification, the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the embodiments described later, the description is relatively simple, and the relevant parts can be referred to the partial description of the previous embodiments.

[0054] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A low voltage drop linear voltage regulator circuit, characterized in that: It includes a voltage input terminal, a voltage output terminal, a current source, an error amplifier A1, a feedback network and a power tube; The voltage input end is respectively connected to one end of the current source and the first end of the power tube; The other end of the current source is connected to the first end of the feedback network and the negative input end of the error amplifier A1 respectively; the positive input end of the error amplifier A1 is connected to the second end of the feedback network; the output end of the error amplifier A1 is connected to the second end of the power tube; The third end of the power tube is connected to the voltage output end and the third end of the feedback network respectively; The feedback network includes a first N-channel field effect transistor NM1, a second N-channel field effect transistor NM2 and a second P-channel field effect transistor PM2; the power transistor is the first P-channel field effect transistor PM1; The drain of the first N-channel field effect transistor NM1 serves as the first end of the feedback network, and the drain of the first N-channel field effect transistor NM1 is respectively connected to the gate of the first N-channel field effect transistor NM1 and the gate of the second N-channel field effect transistor NM2; the source of the first N-channel field effect transistor NM1 is connected to the source of the second N-channel field effect transistor NM2; The gate of the second P-channel field effect transistor PM2 serves as the second end of the feedback network, and the gate of the second P-channel field effect transistor PM2 is respectively connected to the drain of the second P-channel field effect transistor PM2 and the drain of the second N-channel field effect transistor NM2; the source of the second P-channel field effect transistor PM2 serves as the third end of the feedback network; The source of the first P-channel field effect transistor PM1 serves as the first end of the power transistor, the gate of the first P-channel field effect transistor PM1 serves as the second end of the power transistor, and the drain of the first P-channel field effect transistor PM1 serves as the third end of the power transistor.

2. The low voltage difference linear voltage regulator circuit according to claim 1, characterized in that: The feedback network includes a circuit composed of a plurality of field effect transistors.

3. The low voltage difference linear voltage regulator circuit according to claim 1, characterized in that: The magnitude of the reference current I1 of the current source can be adjusted, and the magnitude of the output voltage VOUT of the voltage output terminal can be adjusted by adjusting the magnitude of the reference current I1.

4. The low voltage difference linear voltage regulator circuit according to claim 1, characterized in that: The sizes of the second P-channel field effect transistor PM2 and the first N-channel field effect transistor NM1 are adjustable, and the size of the output voltage VOUT of the voltage output terminal is adjusted by adjusting the sizes of the second P-channel field effect transistor PM2 and the first N-channel field effect transistor NM1.

5. The low voltage difference linear voltage regulator circuit according to claim 1, characterized in that: The error amplifier A1 includes a normally operating amplifier, so that according to the clamping action of the error amplifier A1 , the voltage at the negative input terminal of the error amplifier A1 is equal to the voltage at the positive input terminal of the error amplifier A1 .

6. The low voltage difference linear voltage regulator circuit according to claim 1, characterized in that: The voltage stabilizing circuit enables the output voltage of the voltage output end to be adaptively adjusted following different process angles. Under a slow process angle, the threshold voltage Vth of the N-channel field effect transistor and the P-channel field effect transistor increases, so that the gate-source voltage Vgs increases, and the output voltage VOUT of the voltage output end increases accordingly. Under a fast process angle, the threshold voltage Vth of the N-channel field effect transistor and the P-channel field effect transistor decreases, so that the gate-source voltage Vgs decreases, and the output voltage VOUT of the voltage output end decreases accordingly.

7. A voltage stabilization method, characterized in that: The low voltage difference linear voltage regulator circuit according to claim 1 is applied; the current source generates a reference current I1, and the output voltage VOUT of the voltage output terminal is adjusted by adjusting the size of the reference current I1 and / or adjusting the size of the second P-channel field effect transistor PM2 and the first N-channel field effect transistor NM1.

8. The voltage stabilization method according to claim 7, characterized in that: The output voltage at the voltage output end is adaptively adjusted following different process angles. Under a slow process angle, the threshold voltage Vth of the N-channel field effect transistor and the P-channel field effect transistor increases, causing the gate-source voltage Vgs to increase, and the output voltage VOUT at the voltage output end increases accordingly. Under a fast process angle, the threshold voltage Vth of the N-channel field effect transistor and the P-channel field effect transistor decreases, causing the gate-source voltage Vgs to decrease, and the output voltage VOUT at the voltage output end decreases accordingly.

9. A voltage stabilizer, characterized in that: It comprises the low voltage difference linear voltage stabilizing circuit described in any one of claims 1 to 6.

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