Low dropout linear regulator with bypass mode and negative voltage generation circuit

Abstract

The application relates to a low-dropout linear voltage regulator with a bypass mode and a negative voltage generation circuit. The low-dropout linear voltage regulator comprises a bypass mode switching circuit configured to switch a working mode according to a power supply voltage; and a power tube configured as an output transistor of a low-dropout voltage regulator for outputting a stable voltage; wherein the working mode comprises a normal working mode and a bypass mode; in the case that the power supply voltage is lower than a power supply voltage threshold, the bypass mode switching circuit switches the working mode of the low-dropout linear voltage regulator to the bypass mode, so that the loop of the low-dropout linear voltage regulator is disabled, and the output end of the low-dropout linear voltage regulator outputs the power supply voltage. The application can directly output the power supply voltage when the LDO loop is disabled due to the decrease of the power supply voltage.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronics, and in particular to a low dropout linear regulator with a bypass mode and a negative voltage generation circuit. BACKGROUND

[0002] A low dropout linear regulator (LDO) is a kind of voltage reference, which is usually used to supply power to other functional circuits or modules, such as oscillators, clock buffers, charge pump modules in SOC systems.

[0003] However, since the LDO is a step-down model, when the power supply voltage is low to a certain extent, the LDO will not work normally due to the voltage margin problem, which will result in failure to supply power to other circuits or modules. SUMMARY

[0004] Therefore, the embodiments of the present application provide a low dropout linear regulator with a bypass mode and a negative voltage generation circuit to solve at least one problem in the background art.

[0005] In a first aspect, the embodiments of the present application provide a low dropout linear regulator with a bypass mode, which comprises:

[0006] a bypass mode switching circuit configured to switch the working mode of the low dropout linear regulator according to the power supply voltage; and

[0007] a power tube configured as an output transistor of the low dropout linear regulator for outputting a stable voltage;

[0008] wherein the working mode comprises a normal working mode and a bypass mode;

[0009] in the case that the power supply voltage is lower than a power supply voltage threshold, the bypass mode switching circuit switches the working mode of the low dropout linear regulator to the bypass mode, so that the loop of the low dropout linear regulator is disabled, and the output end of the low dropout linear regulator outputs the power supply voltage;

[0010] in the case that the power supply voltage is higher than the power supply voltage threshold, the bypass mode switching circuit switches the working mode of the low dropout linear regulator to the normal working mode, so that the low dropout linear regulator works normally, and the output end of the low dropout linear regulator outputs the stable voltage output by the power tube.

[0011] In combination with the first aspect, in an optional implementation manner,

[0012] The bypass mode switching circuit comprises:

[0013] a switching control module configured to generate a corresponding start-stop signal and bypass signal according to the power supply voltage;

[0014] a first switch module configured to be turned on or turned off under the control of the bypass signal, so that the output end of the low-dropout linear regulator switches to output the power supply voltage or the stable voltage; and

[0015] a second switch module configured to be turned on or turned off under the control of the start-stop signal, so that the power tube is turned off to disable the loop of the low-dropout linear regulator, or the power tube is turned on to enable the low-dropout linear regulator to work normally.

[0016] In combination with the first aspect, in an optional implementation,

[0017] The switching control module comprises:

[0018] a voltage dividing module configured to divide the power supply voltage to obtain a divided voltage;

[0019] a comparator configured to generate a first-level comparison output signal when the divided voltage is lower than a second reference voltage, and generate a second-level comparison output signal when the divided voltage is higher than the second reference voltage;

[0020] a first inverter configured to invert the comparison output signal to obtain the bypass signal; and

[0021] a second inverter configured to invert the bypass signal to obtain the start-stop signal.

[0022] In combination with the first aspect, in an optional implementation,

[0023] The voltage dividing module comprises a third resistor and a fourth resistor;

[0024] a first end of the third resistor is configured to obtain the power supply voltage, and a second end of the third resistor is connected with a first input end of the comparator and a first end of the fourth resistor respectively and configured to provide the divided voltage;

[0025] a second end of the fourth resistor is grounded.

[0026] In combination with the first aspect, in an optional implementation,

[0027] The first switch module comprises a second switch NMOS tube;

[0028] The second switch module comprises a first switch PMOS tube.

[0029] With reference to the first aspect, in an optional implementation of the first aspect,

[0030] The comparator comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth PMOS transistor, a fifth NMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh NMOS transistor, a twelfth PMOS transistor, a thirteenth NMOS transistor, a fourteenth PMOS transistor, and a fifteenth NMOS transistor.

[0031] The gate of the first NMOS transistor is configured as a first input terminal of the comparator, and the gate of the second NMOS transistor is configured as a second input terminal of the comparator and obtains a second reference voltage.

[0032] The source of the first NMOS transistor and the source of the second NMOS transistor are respectively connected with the drain of the third NMOS transistor, the source of the third NMOS transistor is connected with a ground terminal, and the gate of the third NMOS transistor is configured to obtain a first low bias voltage.

[0033] The drain of the first NMOS transistor is respectively connected with the gate of the fourth PMOS transistor, the drain of the sixth PMOS transistor, the gate of the sixth PMOS transistor, the gate of the seventh PMOS transistor, and the drain of the eighth PMOS transistor; the drain of the second NMOS transistor is respectively connected with the gate of the tenth PMOS transistor, the drain of the ninth PMOS transistor, the gate of the ninth PMOS transistor, the gate of the eighth PMOS transistor, and the drain of the seventh PMOS transistor; the source of the fourth PMOS transistor, the source of the sixth PMOS transistor, the source of the seventh PMOS transistor, the source of the eighth PMOS transistor, the source of the ninth PMOS transistor, and the source of the tenth PMOS transistor are respectively configured to obtain a power supply voltage.

[0034] The drain of the fourth PMOS transistor is respectively connected with the drain of the fifth NMOS transistor, the gate of the fifth NMOS transistor, and the gate of the eleventh NMOS transistor; the drain of the tenth PMOS transistor is respectively connected with the drain of the eleventh NMOS transistor, the gate of the twelfth PMOS transistor, and the gate of the thirteenth NMOS transistor; the drain of the twelfth PMOS transistor is respectively connected with the drain of the thirteenth NMOS transistor, the gate of the fourteenth PMOS transistor, and the gate of the fifteenth NMOS transistor; the source of the twelfth PMOS transistor and the source of the fourteenth PMOS transistor are respectively configured to obtain a power supply voltage; and the source of the fifth NMOS transistor, the source of the eleventh NMOS transistor, the source of the thirteenth NMOS transistor, and the source of the fifteenth NMOS transistor are respectively connected with a ground terminal.

[0035] The drain of the fourteenth PMOS transistor and the drain of the fifteenth NMOS transistor are connected and configured as an output terminal of the comparator.

[0036] With reference to the first aspect, in an optional implementation of the low-dropout linear voltage regulator with bypass mode, the low-dropout linear voltage regulator further comprises an error amplifier and a feedback circuit.

[0037] The first input terminal of the error amplifier is configured to obtain a first reference voltage, the second input terminal of the error amplifier is connected with the output terminal of the feedback circuit, and the output terminal of the error amplifier is connected with the gate terminal of the power tube.

[0038] The input terminal of the feedback circuit is connected with the output terminal of the low-dropout linear voltage regulator.

[0039] With reference to the first aspect, in an optional implementation of the low-dropout linear voltage regulator with bypass mode, the low-dropout linear voltage regulator further comprises an error amplifier and a feedback circuit.

[0040] The error amplifier comprises a sixteenth PMOS tube, a seventeenth PMOS tube, an eighteenth PMOS tube, a nineteenth NMOS tube, a twentieth NMOS tube, a twenty-first NMOS tube, a twenty-second NMOS tube, a twenty-third NMOS tube, a twenty-fourth NMOS tube, a twenty-fifth PMOS tube, a twenty-sixth PMOS tube, and a compensation capacitor.

[0041] The gate of the sixteenth PMOS tube is configured as the first input terminal of the error amplifier EA, and the gate of the seventeenth PMOS tube is configured as the second input terminal of the error amplifier.

[0042] The drain of the sixteenth PMOS tube is connected with the drain, the gate of the nineteenth NMOS tube, and the gate of the twentieth NMOS tube respectively, and the drain of the seventeenth PMOS tube is connected with the drain, the gate of the twenty-first NMOS tube, and the gate of the twenty-second NMOS tube respectively; the drain of the twentieth NMOS tube is connected with the source of the twenty-third NMOS tube, and the drain of the twenty-second NMOS tube is connected with the source of the twenty-fourth NMOS tube; the drain of the twenty-third NMOS tube is connected with the drain, the gate of the twenty-fifth PMOS tube, and the gate of the twenty-sixth PMOS tube respectively, and the drain of the twenty-fourth NMOS tube is connected with the drain of the twenty-sixth PMOS tube and configured as the output terminal of the error amplifier.

[0043] The source of the sixteenth PMOS tube and the source of the seventeenth PMOS tube are connected with the drain of the eighteenth PMOS tube respectively; the source of the eighteenth PMOS tube, the source of the twenty-fifth PMOS tube, and the source of the twenty-sixth PMOS tube are respectively configured to obtain a power supply voltage; and the source of the nineteenth NMOS tube, the source of the twentieth NMOS tube, the source of the twenty-first NMOS tube, and the source of the twenty-second NMOS tube are respectively connected with a ground terminal.

[0044] The gate of the twenty-third NMOS transistor and the gate of the twenty-fourth NMOS transistor are configured to obtain a second low-level bias voltage, and the gate of the eighteenth PMOS transistor M18 is configured to obtain a first high-level bias voltage;

[0045] The first end of the compensation capacitor is connected with the drain of the twenty-second NMOS transistor and the source of the twenty-fourth NMOS transistor respectively, and the second end of the compensation capacitor is connected with the output end of the low-dropout linear voltage regulator;

[0046] And / or, the feedback circuit comprises a first resistor and a second resistor;

[0047] The second input end of the error amplifier is connected with the second end of the first resistor and the first end of the second resistor respectively, the first end of the first resistor is connected with the output end of the low-dropout linear voltage regulator, and the second end of the second resistor is connected with a ground end.

[0048] In a second aspect, the embodiments of the present application provide a negative voltage generating circuit, which comprises a charge pump and a low-dropout linear voltage regulator with a bypass mode as described in the first aspect;

[0049] The power supply end of the charge pump is configured to obtain a stable voltage output by the low-dropout linear voltage regulator in a normal working mode or a power supply voltage output by the low-dropout linear voltage regulator in a bypass mode;

[0050] The charge pump is configured to output a stable negative voltage under the power supply of the voltage obtained by the power supply end.

[0051] In combination with the second aspect, in an optional implementation manner,

[0052] The charge pump comprises a thirty-sixth PMOS transistor, a thirty-seventh PMOS transistor, a thirty-eighth NMOS transistor, a thirty-ninth NMOS transistor, a second capacitor, a third capacitor, a thirty-second PMOS transistor, a thirty-third PMOS transistor, a thirty-fourth NMOS transistor, a thirty-fifth NMOS transistor, a fifth resistor and a fourth capacitor;

[0053] The gate of the thirty-sixth PMOS transistor is configured to obtain a first signal, and the gate of the thirty-ninth NMOS transistor is configured to obtain a first inverted signal; the gate of the thirty-seventh PMOS transistor is configured to obtain a second signal, and the gate of the thirty-eighth NMOS transistor is configured to obtain a second inverted signal;

[0054] The source of the thirty-sixth PMOS transistor and the source of the thirty-seventh PMOS transistor are connected with the output end of the low dropout linear regulator respectively, the source of the thirty-eighth NMOS transistor and the source of the thirty-ninth NMOS transistor are connected with the ground end respectively, the drain of the thirty-sixth PMOS transistor is connected with the drain of the thirty-eighth NMOS transistor and the first end of the second capacitor respectively, the drain of the thirty-seventh PMOS transistor is connected with the drain of the thirty-ninth NMOS transistor and the first end of the third capacitor respectively; the second end of the second capacitor is connected with the drain of the thirty-second PMOS transistor, the drain of the thirty-fourth NMOS transistor, the gate of the thirty-third PMOS transistor and the gate of the thirty-fifth NMOS transistor respectively, the second end of the third capacitor is connected with the drain of the thirty-third PMOS transistor, the drain of the thirty-fifth NMOS transistor, the gate of the thirty-second PMOS transistor and the gate of the thirty-fourth NMOS transistor respectively; the source of the thirty-second PMOS transistor and the source of the thirty-third PMOS transistor are connected with the ground end respectively, the source of the thirty-fourth NMOS transistor and the source of the thirty-fifth NMOS transistor are connected with the first end of the fifth resistor respectively, the second end of the fifth resistor is connected with the first end of the fourth capacitor and configured to output a negative voltage, and the second end of the fourth capacitor is connected with the ground end.

[0055] The technical scheme provided by the embodiment of the present application has the beneficial effects that: through the bypass mode switching circuit, the working mode of the low dropout linear regulator (LDO) can be switched according to the power supply voltage, so that when the power supply voltage decreases to a certain extent, i.e., is lower than the power supply voltage threshold, the defect that the LDO cannot work normally is overcome, the LDO can be switched from the normal working mode to the bypass mode, and at this time, the output end of the LDO directly outputs the power supply voltage. Therefore, the output end of the LDO can output a stable voltage when the LDO works normally, and can output the power supply voltage when the LDO cannot work normally, so that the output is not closed due to the LDO not working normally, i.e., the power supply capability is not lost, the power supply voltage can be used to continue to supply power to the subsequent functional modules such as the negative voltage generation module, and the LDO is ensured to be a relatively stable voltage reference source, so that the voltage output of the LDO is continuous and uninterrupted.

[0056] Some of the aspects and advantages of the embodiments of the present application will be presented in the following description, some will become apparent from the following description, or will be understood by those skilled in the art through practice of the embodiments of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0057] The drawings described herein are used to provide a further understanding of the present application, and form a part of the present application, wherein the drawings are not necessarily drawn to scale, and some local features can be enlarged or reduced to more clearly show the details of the local features. The illustrative embodiments of the present application and their descriptions are used to explain the present application, and do not constitute an improper limitation on the present application. In the drawings:

[0058] Figure 1 a schematic diagram of a principle block of a power supply system consistent with at least one embodiment of the present application;

[0059] Figure 2 a schematic diagram of a principle block of a negative voltage generating circuit consistent with at least one embodiment of the present application;

[0060] Figure 3 a schematic diagram of a principle block of a low dropout linear regulator with a bypass mode consistent with at least one embodiment of the present application;

[0061] Figure 4 a schematic diagram of a circuit of a bypass mode switching circuit consistent with at least one embodiment of the present application;

[0062] Figure 5 a schematic diagram of a circuit of a comparator consistent with at least one embodiment of the present application;

[0063] Figure 6 a schematic diagram of a circuit of a low dropout linear regulator with a bypass mode consistent with at least one embodiment of the present application;

[0064] Figure 7 a schematic diagram of a principle block of a negative voltage generating circuit consistent with at least one embodiment of the present application;

[0065] Figure 8 a schematic diagram of a circuit of a charge pump consistent with at least one embodiment of the present application. DETAILED DESCRIPTION

[0066] In order to make the technical solutions and advantages of the present application more obvious and understandable, the following will be described in detail by way of listing specific embodiments. The drawings are not necessarily drawn to scale, and local features can be enlarged or reduced to more clearly show the details of local features; unless otherwise defined, the technical and scientific terms used herein have the same meaning as the technical and scientific terms in the technical field to which the present application belongs.

[0067] The embodiments of the present application are not exhaustive, but only illustrate some embodiments, and are not specific limitations on the protection scope of the present application. Each step in an embodiment can be implemented as an independent embodiment, and the steps can be combined arbitrarily, for example, the scheme after removing some steps in an embodiment can also be implemented as an independent embodiment, and the order of the steps in an embodiment can be exchanged arbitrarily, in addition, the optional implementation manners in an embodiment can be combined arbitrarily; furthermore, the embodiments can be combined arbitrarily, for example, the steps of different embodiments or all steps of different embodiments can be combined arbitrarily, an embodiment can be combined with the optional implementation manners of other embodiments arbitrarily.

[0068] In the embodiments of the present application, the terms and / or descriptions among the embodiments are consistent and can be referred to each other if there is no special description and logical conflict, and the technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationship.

[0069] The terms used in the embodiments of the present application are only for the purpose of describing the specific embodiments, and not as a limitation of the present application.

[0070] In the embodiments of the present application, unless otherwise specified, the elements expressed in singular form, such as "one", "a", "the", "above", "said", "preceding", "this" and the like, can represent "one and only one", or "one or more", "at least one" and the like. For example, in the case of using articles such as "a", "an", "the" in English, the noun after the article can be understood as singular expression, or as plural expression.

[0071] In the embodiments of the present application, "plurality" means two or more.

[0072] In some embodiments, the terms "at least one of", "one or more", "a plurality of", "multiple" and the like can be replaced with each other.

[0073] The prefix words "first", "second" and the like in the embodiments of the present application are only for distinguishing different description objects, and do not constitute a limitation on the position, order, priority, value or content of the description objects. The description of the description objects is referred to the description in the context of the embodiments, and should not be considered as redundant limitation because of the use of the prefix words. For example, the value of the description object is not limited by the ordinal number, and can be one or more. Taking "first device" as an example, the value of "device" can be one or more. In addition, the objects modified by different prefix words can be the same or different, for example, the description object is "device", and "first device" and "second device" can be the same device or different devices, and their types can be the same or different.

[0074] In some embodiments, the term "connected" can mean that there is mutual transmission of electrical signals or data between the connected end and the connected end, which can be understood as "electrically connected", "communicatively connected" and the like. The "connection" can be a direct connection between two components, or an indirect connection established through other components, or a communication within two components, or any other possible connection form.

[0075] In some embodiments, the terms "greater than", "greater than or equal to", "not less than", "more than", "more than or equal to", "not less than", "higher than", "higher than or equal to", "not lower than", "above", "exceed" and the like can be replaced with each other, and the terms "less than", "less than or equal to", "not greater than", "less than", "less than or equal to", "not more than", "lower than", "lower than or equal to", "not higher than", "below" and the like can be replaced with each other.

[0076] In some embodiments, high voltage and low voltage, or high level and low level, or high voltage and low voltage, can be relative values, not limited to absolute values.

[0077] In some embodiments, the transistor can be a single transistor; it can also be a series and / or parallel connection of multiple transistors, and has a functional pole corresponding to each functional pole of the single transistor respectively, and has the same working state as the single transistor, such as the on state and the off state. For example, the single transistor can be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor, abbreviated as MOS tube), and its functional poles can include gate G, source S, drain D and substrate B. Then the series and / or parallel connection of multiple transistors has gate G, source S, drain D and substrate B corresponding to gate G, source S, drain D and substrate B of the single transistor respectively, and the working state of the MOS tube. The MOS tube can include P-type MOS tube (abbreviated as PMOS tube) and N-type MOS tube (abbreviated as NMOS tube).

[0078] In some embodiments, the LDO circuit can use different names such as LDO, low dropout regulator, low dropout regulator, low dropout linear voltage regulator, etc. Here, the name is not limited.

[0079] Figure 1 A schematic diagram of a power supply system is shown, which is consistent with at least one embodiment of the present application. As shown, the power supply system includes a reference voltage generator and a functional module. The stable voltage vout_ref output by the reference voltage generator is used to supply power to one or more functional modules.

[0080] In an exemplary embodiment, the reference voltage generator can include a low dropout linear regulator (LDO). The LDO has high stability, fast dynamic response and stable output characteristics, and can supply power to a negative voltage generation module, etc., so as to ensure the stability of the negative voltage generated by the negative voltage generation module.

[0081] In an exemplary embodiment, Figure 2A schematic diagram of a principle block diagram of one specific example of a negative voltage generation circuit is shown. As shown, the negative voltage generation module 200 can include an oscillator, a clock buffer and a charge pump. In order to ensure that the negative voltage generated by the negative voltage generation module 200 is always kept at a suitable potential, a reference voltage generator (such as an LDO) is first needed to provide a relatively stable voltage reference source for the oscillator, the clock buffer and the charge pump. Then, under the supply of the stable voltage vout_ref output by the LDO, the clock buffer can generate two opposite clock signals (clk and clkb) according to the oscillation signal output by the oscillator, to be provided to the charge pump, and finally the charge pump outputs a stable negative voltage vneg.

[0082] However, if the supply voltage is reduced, and the more advanced processes can adopt lower supply voltage, and the LDO is a step-down model, when the supply voltage is low to a certain extent, due to the problem of voltage margin, the LDO cannot work normally, i.e. the LDO is closed and no stable voltage vout_ref is output, which affects the power supply to the functional modules such as the oscillator, the clock buffer and the charge pump, so that they cannot work normally.

[0083] Therefore, an embodiment of the present application provides a low-dropout linear voltage regulator with a bypass mode, Figure 3 A schematic diagram of a principle block diagram of one specific example of the low-dropout linear voltage regulator with a bypass mode in the embodiment of the present application is shown. As shown, the low-dropout linear voltage regulator with a bypass mode includes:

[0084] a bypass mode switching circuit 100 configured to switch the working mode of the low-dropout linear voltage regulator according to a supply voltage vdda; and

[0085] a power transistor MP configured as an output transistor of the low-dropout linear voltage regulator, for outputting a stable voltage vout_ref;

[0086] wherein the working mode includes a normal working mode and a bypass mode;

[0087] In a case where the supply voltage vdda is lower than a supply voltage threshold, the bypass mode switching circuit 100 switches the working mode of the low-dropout linear voltage regulator to the bypass mode, so that the loop of the low-dropout linear voltage regulator is disabled, and the output end OUT of the low-dropout linear voltage regulator outputs the supply voltage vdda;

[0088] When the power supply voltage vdda is higher than the power supply voltage threshold, the bypass mode switching circuit 100 switches the working mode of the low-dropout linear regulator to the normal working mode, so that the low-dropout linear regulator works normally, and the output terminal OUT of the low-dropout linear regulator outputs the stable voltage vout_ref output by the power tube MP.

[0089] Thus, the bypass mode switching circuit can switch the working mode of the low-dropout linear regulator according to the power supply voltage, so that when the power supply voltage decreases to a certain extent, i.e., is lower than the power supply voltage threshold, the low-dropout linear regulator can be switched from the normal working mode to the bypass mode, and the output terminal of the low-dropout linear regulator directly outputs the power supply voltage at this time. Therefore, the output terminal of the low-dropout linear regulator can output a stable voltage when the low-dropout linear regulator works normally, and can output a power supply voltage when the low-dropout linear regulator cannot work normally, so that the output is not closed due to the failure of the low-dropout linear regulator to work normally, i.e., the power supply capability is not lost, and the power supply voltage can be used to continue to supply power to the subsequent functional modules such as the negative voltage generating module, so as to ensure that the low-dropout linear regulator is a relatively stable voltage reference source, and the low-dropout linear regulator output is continuous and uninterrupted.

[0090] In the embodiment of the application, the power tube MP can include at least one of the following: MOSFET; BJT (Bipolar Junction Transistor, simply referred to as triode); IGBT (Insulated Gate Bipolar Transistor); GTO (Gate Turn-Off Thyristor); SCR (Silicon Controlled Rectifier); MCT (MOS Controlled Thyristor); IGCT (Integrated Gate Commutated Thyristor); IEGT (Injection Enhanced Gate Transistor). The power tube MP can include a control terminal, a first signal terminal and a second signal terminal, and its working principle is that the passage between the first signal terminal and the second signal terminal is turned on or turned off under the control of the control signal input at the control terminal, so as to connect or block the signal transmission between the first signal terminal and the second signal terminal. For example, the first signal terminal can be a source terminal, and correspondingly, the second signal terminal can be a drain terminal; or conversely, the first signal terminal can be a drain terminal, and correspondingly, the second signal terminal can be a source terminal. Exemplarily, the power tube MP can be a PMOS tube.

[0091] The manner of switching the LDO working mode according to the power supply voltage vdda in the bypass mode switching circuit 100 can be set according to actual needs, for example, at least one of the following can be included: switching is realized by using a switching module; switching is controlled by using a circuit with signal processing capability, including a CPU (Central Processing Unit), a GPU (graphics processing unit), a circuit with instruction reading and running capability, an FPGA, a circuit with a fixed or reconfigurable logic relationship to realize a certain function, or other circuits, to control the switching of the LDO loop according to the power supply voltage obtained by the circuit to control the normal working or failure of the LDO loop; and the like.

[0092] The power supply voltage threshold value can be set according to actual needs, for example, it can be determined according to the voltage margin.

[0093] The overall architecture of the low dropout linear regulator with a bypass mode provided by the embodiments of the present application mainly includes two parts: an LDO main loop structure mainly composed of an error amplifier EA, a power tube MP and a feedback circuit 300; and an output switching structure mainly composed of a bypass mode switching circuit 100.

[0094] Figure 4 A circuit schematic diagram of a specific example of the bypass mode switching circuit in the embodiments of the present application is shown. As shown in the figure, in an optional embodiment, the bypass mode switching circuit includes:

[0095] The switching control module 101 is configured to generate corresponding start-stop signals b and bypass signals a according to the power supply voltage vdda;

[0096] The first switching module 102 is configured to be turned on or turned off under the control of the bypass signal a, so that the output end OUT of the low dropout linear regulator switches to output the power supply voltage vdda or the stable voltage vout_ref; and

[0097] The second switching module 103 is configured to be turned on or turned off under the control of the start-stop signal b, so that the power tube MP is turned off to make the loop of the low dropout linear regulator invalid, or the power tube MP is turned on to make the low dropout linear regulator work normally.

[0098] In the exemplary embodiments, a comparator can be used to determine whether the power supply voltage vdda decreases, for example, the power supply voltage vdda can be directly compared with the power supply voltage threshold value, or the power supply voltage vdda can be divided and then compared with a reference voltage, and the like.

[0099] The correspondence between the bypass signal a and the start-stop signal b can be a correlation or an inverse correlation, which can be determined according to the effective level of the control signal required by the first switch module 102 and the second switch module 103 controlled by the bypass signal a and the start-stop signal b, respectively. For example, if the effective level of the control signal required by the first switch module 102 (such as an NMOS tube) and the second switch module 103 (such as a PMOS tube) is inverse, that is, one is high and the other is low, the bypass signal a and the start-stop signal b can be inversely correlated.

[0100] In the exemplary embodiment, when the first switch module 102 is turned on under the control of the bypass signal a, the output end OUT of the low-dropout linear regulator can output the power supply voltage vdda, at this time the second switch module 103 can be turned on under the control of the start-stop signal b, the power tube MP can be controlled to be disconnected, and the loop of the low-dropout linear regulator is disabled.

[0101] On the contrary, when the second switch module 103 is disconnected under the control of the start-stop signal b, the power tube MP can be controlled to be turned on, and the low-dropout linear regulator works normally, at this time the first switch module 102 can be disconnected under the control of the bypass signal a, and the output end OUT of the low-dropout linear regulator can output the stable voltage vout_ref.

[0102] In this way, the embodiment of the present application realizes the control of the voltage value output by the LDO output end according to the power supply voltage by switching the control of the first switch module and the second switch module under the control of the corresponding start-stop signal and bypass signal, that is, controlling the working mode of the switching LDO, and ensuring that the LDO output end can output voltage regardless of whether the LDO can normally work due to the power supply voltage, so that the LDO output is continuous and uninterrupted.

[0103] In an optional embodiment, the switching control module 101 comprises:

[0104] The voltage dividing module 1011 is configured to divide the power supply voltage vdda to obtain a divided voltage V1;

[0105] The comparator COM is configured to generate a first level comparison output signal when the divided voltage V1 is lower than the second reference voltage Vref2, and generate a second level comparison output signal when the divided voltage V1 is higher than the second reference voltage Vref2;

[0106] The first inverter U1 is configured to invert the comparison output signal to obtain the bypass signal a; and

[0107] The second inverter U2 is configured to invert the bypass signal a to obtain the start-stop signal b.

[0108] In the embodiments of the present application, the first level can be a high level or a low level, and correspondingly, the second level can be a low level or a high level.

[0109] In this way, the embodiments of the present application compare the divided voltage obtained by dividing the power supply voltage by the voltage dividing module with the second reference voltage, and obtain the bypass signal and the start-stop signal which are opposite to each other through two cascaded inverters, thereby improving the reliability and stability of the on-off control of the first switch module and the second switch module.

[0110] Reference Figure 4 Fig. 1 shows a specific example of a voltage dividing module 1011, but is not limited thereto.

[0111] In an optional embodiment, the voltage dividing module 1011 includes a third resistor R3 and a fourth resistor R4.

[0112] The first end of the third resistor R3 is configured to obtain the power supply voltage vdda, and the second end of the third resistor R3 is connected to the first input end of the comparator COM and the first end of the fourth resistor R4, and is configured to provide the divided voltage V1.

[0113] The second end of the fourth resistor R4 is grounded at the terminal vssa.

[0114] In the embodiments of the present application, the third resistor R3 and the fourth resistor R4 can each be a single resistor, or a series and / or parallel connection of multiple resistors, and can further include a passive resistor network or an active resistor network of resistors, capacitors, inductors, etc.

[0115] In an optional embodiment, the first switch module 102 includes a second switch NMOS transistor Mc2.

[0116] The second switch module 103 includes a first switch PMOS transistor Mc1.

[0117] In the exemplary embodiments, when the power supply is normal, the power supply voltage is divided by R3 and R4, and then compared with the second reference voltage Vref2, and the comparator COM generates a high level, so the bypass signal a is low, and the start-stop signal b is high, i.e., Mc1 and Mc2 are turned off, the LDO works normally, and the output is stable.

[0118] When the power supply voltage decreases, the voltage after being divided by R3 and R4 also decreases, so the comparator COM generates a low level, and for the same reason, the bypass signal a is high, and the start-stop signal b is low, Mc1 is turned on, the gate end of MP is directly pulled to the power supply voltage, the LDO loop is invalid, and no longer works, at this time, Mc2 is also turned on, and the LDO output end OUT directly outputs the power supply voltage, and then supplies power to the subsequent negative voltage generating module.

[0119] The switch tubes used by the first switch module 102 and the second switch module 103 can also include at least one of the following: BJT (triode), SCR (silicon controlled), GTO (gate turn-off thyristor), IGBT (insulated gate bipolar transistor), MCT (MOS controlled thyristor), SIT (static induction transistor), and the like.

[0120] Figure 5 The circuit schematic diagram of a specific example of the comparator in the embodiment of the application is shown, but the specific circuit structure of the comparator COM is not limited to the circuit structure shown in the Figure 5 The comparator COM includes a first NMOS tube M1, a second NMOS tube M2, a third NMOS tube M3, a fourth PMOS tube M4, a fifth NMOS tube M5, a sixth PMOS tube M6, a seventh PMOS tube M7, an eighth PMOS tube M8, a ninth PMOS tube M9, a tenth PMOS tube M10, an eleventh NMOS tube M11, a twelfth PMOS tube M12, a thirteenth NMOS tube M13, a fourteenth PMOS tube M14, and a fifteenth NMOS tube M15 in an optional embodiment, as shown in the figure.

[0121] The gate of the first NMOS tube M1 is configured as the first input end of the comparator COM, and the gate of the second NMOS tube M2 is configured as the second input end of the comparator COM and obtains the second reference voltage Vref2.

[0122] The source of the first NMOS tube M1 and the source of the second NMOS tube M2 are respectively connected with the drain of the third NMOS tube M3, the source of the third NMOS tube M3 is connected with the ground terminal vssa, and the gate of the third NMOS tube M3 is configured to obtain the first low bias voltage vbn1.

[0123] The drain of the first NMOS tube M1 is respectively connected with the gate of the fourth PMOS tube M4, the drain of the sixth PMOS tube M6, the gate of the sixth PMOS tube M6, the gate of the seventh PMOS tube M7, and the drain of the eighth PMOS tube M8; the drain of the second NMOS tube M2 is respectively connected with the gate of the tenth PMOS tube M10, the drain of the ninth PMOS tube M9, the gate of the ninth PMOS tube M9, the gate of the eighth PMOS tube M8, and the drain of the seventh PMOS tube M7; the source of the fourth PMOS tube M4, the source of the sixth PMOS tube M6, the source of the seventh PMOS tube M7, the source of the eighth PMOS tube M8, the source of the ninth PMOS tube M9, and the source of the tenth PMOS tube M10 are respectively configured to obtain the power supply voltage vdda.

[0124] The drain of the fourth PMOS transistor M4 is connected with the drain of the fifth NMOS transistor M5, the gate of the fifth NMOS transistor M5 and the gate of the eleventh NMOS transistor M11 respectively; the drain of the tenth PMOS transistor M10 is connected with the drain of the eleventh NMOS transistor M11, the gate of the twelfth PMOS transistor M12 and the gate of the thirteenth NMOS transistor M13 respectively; the drain of the twelfth PMOS transistor M12 is connected with the drain of the thirteenth NMOS transistor M13, the gate of the fourteenth PMOS transistor M14 and the gate of the fifteenth NMOS transistor M15 respectively; the source of the twelfth PMOS transistor M12 and the source of the fourteenth PMOS transistor M14 are configured to obtain a power supply voltage vdda; the source of the fifth NMOS transistor M5, the source of the eleventh NMOS transistor M11, the source of the thirteenth NMOS transistor M13 and the source of the fifteenth NMOS transistor M15 are connected with a ground terminal vssa respectively.

[0125] The drain of the fourteenth PMOS transistor M14 and the drain of the fifteenth NMOS transistor M15 are connected and configured as an output terminal vout_com of the comparator COM.

[0126] In the embodiment of the application, the first NMOS transistor M1 and the second NMOS transistor M2 are input pair transistors of the comparator COM, the gate of M1 can be configured to obtain a divided voltage V1, and the gate of M2 can be configured to obtain a second reference voltage Vref2.

[0127] In the exemplary embodiment, the divided voltage V1 can be input from the positive input terminal of the comparator COM, and the second reference voltage Vref2 can be input from the negative input terminal of the comparator COM. Then, when the divided voltage V1 is higher than the second reference voltage Vref2, the comparator COM can output a high-level comparison output signal, and then obtain a low-level bypass signal a and a high-level start-stop signal b, at this time, the first switch module 102 (such as an NMOS transistor) can be controlled to be turned off and the second switch module 103 (such as a PMOS transistor) can be controlled to be turned off, and the LDO is in a normal working mode.

[0128] When the divided voltage V1 is lower than the second reference voltage Vref2, the comparator COM can output a low-level comparison output signal, and then obtain a high-level bypass signal a and a low-level start-stop signal b, at this time, the first switch module 102 (such as an NMOS transistor) can be controlled to be turned on and the second switch module 103 (such as a PMOS transistor) can be controlled to be turned on, and the LDO is in a bypass mode.

[0129] In the embodiment of the application, the twelfth PMOS transistor M12 and the thirteenth NMOS transistor M13, and the fourteenth PMOS transistor M14 and the fifteenth NMOS transistor M15 can respectively constitute inverters, so that the comparison output signal output by the comparator COM is localized, and the output stability is improved.

[0130] Reference Figure 3 In an optional embodiment, the low-dropout linear regulator with bypass mode further comprises an error amplifier EA and a feedback circuit 300;

[0131] A first input terminal of the error amplifier EA is configured to obtain a first reference voltage Vref1, a second input terminal of the error amplifier EA is connected with an output terminal of the feedback circuit 300, and an output terminal of the error amplifier EA is connected with a gate terminal of the power transistor MP;

[0132] An input terminal of the feedback circuit 300 is connected with an output terminal of the low-dropout linear regulator.

[0133] Figure 6 A circuit schematic diagram of a specific example of the low-dropout linear regulator with bypass mode in the embodiment of the application is shown, wherein a specific circuit structure of a specific example of the error amplifier EA is shown, but is not limited thereto. As shown in the figure, in an optional embodiment, the error amplifier EA comprises a sixteenth PMOS transistor M16, a seventeenth PMOS transistor M17, an eighteenth PMOS transistor M18, a nineteenth NMOS transistor M19, a twentieth NMOS transistor M20, a twenty-first NMOS transistor M21, a twenty-second NMOS transistor M22, a twenty-third NMOS transistor M23, a twenty-fourth NMOS transistor M24, a twenty-fifth PMOS transistor M25, a twenty-sixth PMOS transistor M26, and a compensation capacitor Cc;

[0134] A gate terminal of the sixteenth PMOS transistor M16 is configured as a first input terminal of the error amplifier EA, and a gate terminal of the seventeenth PMOS transistor M17 is configured as a second input terminal of the error amplifier EA;

[0135] A drain terminal of the sixteenth PMOS transistor M16 is connected with a drain terminal, a gate terminal and a gate terminal of the nineteenth NMOS transistor M19 and the twentieth NMOS transistor M20 respectively, and a drain terminal of the seventeenth PMOS transistor M17 is connected with a drain terminal, a gate terminal and a gate terminal of the twenty-first NMOS transistor M21 and the twenty-second NMOS transistor M22 respectively; a drain terminal of the twentieth NMOS transistor M20 is connected with a source terminal of the twenty-third NMOS transistor M23, and a drain terminal of the twenty-second NMOS transistor M22 is connected with a source terminal of the twenty-fourth NMOS transistor M24; a drain terminal of the twenty-third NMOS transistor M23 is connected with a drain terminal, a gate terminal and a gate terminal of the twenty-fifth PMOS transistor M25 and the twenty-sixth PMOS transistor M26 respectively, and a drain terminal of the twenty-fourth NMOS transistor M24 is connected with a drain terminal of the twenty-sixth PMOS transistor M26 and configured as an output terminal of the error amplifier EA;

[0136] The source of the sixteenth PMOS transistor M16 and the source of the seventeenth PMOS transistor M17 are respectively connected with the drain of the eighteenth PMOS transistor M18; the source of the eighteenth PMOS transistor M18, the source of the twenty-fifth PMOS transistor M25 and the source of the twenty-sixth PMOS transistor M26 are respectively configured to obtain a power supply voltage vdda connection; the source of the nineteenth NMOS transistor M19, the source of the twentieth NMOS transistor M20, the source of the twenty-first NMOS transistor M21 and the source of the twenty-second NMOS transistor M22 are respectively connected with a ground terminal vssa;

[0137] The gate of the twenty-third NMOS transistor M23 and the gate of the twenty-fourth NMOS transistor M24 are respectively configured to obtain a second low bias voltage vbn2, and the gate of the eighteenth PMOS transistor M18 is configured to obtain a first high bias voltage vbp1.

[0138] The first end of the compensation capacitor Cc is respectively connected with the drain of the twenty-second NMOS transistor M22 and the source of the twenty-fourth NMOS transistor M24, and the second end of the compensation capacitor Cc is connected with the output terminal of the low dropout linear regulator.

[0139] In the embodiment of the application, the Miller compensation can be realized by the compensation capacitor Cc, and the output stability is improved.

[0140] In an optional embodiment, the feedback circuit 300 comprises a first resistor R1 and a second resistor R2.

[0141] The second input terminal of the error amplifier EA is respectively connected with the second end of the first resistor R1 and the first end of the second resistor R2, the first end of the first resistor R1 is connected with the output terminal of the low dropout linear regulator, and the second end of the second resistor R2 is connected with a ground terminal vssa.

[0142] In the embodiment of the application, the first input terminal of the error amplifier EA can be a negative input terminal, and the second input terminal of the error amplifier EA can be a positive input terminal. M16 and M17 can be input pair transistors of the error amplifier EA, the gate of M16 can obtain a first reference voltage Vref1, the gate of M17 can obtain a feedback signal vfb, and can be connected to a connection node between the first resistor R1 and the second resistor R2. The gate of the power transistor MP can be respectively connected to the drain of M24 and the drain of M26.

[0143] In the embodiment of the application, the specific circuit structure of the feedback circuit 300 can be set according to actual needs, and is not limited to Figure 6 the structure shown in the figure.

[0144] The first resistor R1 and the second resistor R2 and the like can be a single resistor, or can be a series and / or parallel connection of multiple resistors, and can also include a passive resistance network or an active resistance network of resistors, capacitors, inductors and the like.

[0145] The first low bias signal vbn1, the second low bias signal vbn2 and the first high bias signal vbp1 can be provided by external bias circuits, which can be controlled by a logic control circuit. These are not the invention points of the application, and the bias circuits and the logic control circuit are prior art, which will not be described in detail.

[0146] The application also provides a negative voltage generating circuit, Figure 7 A principle block diagram of a specific example of the negative voltage generating circuit in the application is shown, as shown in the figure, which can be powered by the low dropout linear regulator with bypass mode in the above-mentioned embodiment.

[0147] The negative voltage generating circuit comprises a charge pump and a low dropout linear regulator with bypass mode as described in the above-mentioned embodiment;

[0148] The power supply end of the charge pump is configured to obtain a stable voltage vout_ref output by the low dropout linear regulator in a normal working mode, or a power supply voltage vdda output in a bypass mode;

[0149] The charge pump is configured to output a stable negative voltage vneg under the power supply of the voltage obtained at the power supply end.

[0150] In this way, the charge pump is powered by the low dropout linear regulator with bypass mode, and the charge pump can provide a stable negative voltage regardless of whether the LDO can normally work due to the reduction of the power supply voltage, thereby improving the stability of the output of the charge pump.

[0151] Figure 8 A circuit diagram of a specific example of the charge pump in the application is shown, but the specific circuit structure of the charge pump is not limited to this. As shown in the figure, in an optional embodiment, the charge pump comprises a thirty-sixth PMOS transistor M36, a thirty-seventh PMOS transistor M37, a thirty-eighth NMOS transistor M38, a thirty-ninth NMOS transistor M39, a second capacitor C2, a third capacitor C3, a thirty-second PMOS transistor M32, a thirty-third PMOS transistor M33, a thirty-fourth NMOS transistor M34, a thirty-fifth NMOS transistor M35, a fifth resistor R5 and a fourth capacitor C4;

[0152] The gate of the thirty-sixth PMOS transistor M36 is configured to obtain a first signal n1, and the gate of the thirty-ninth NMOS transistor M39 is configured to obtain a first inverted signal n1b; the gate of the thirty-seventh PMOS transistor M37 is configured to obtain a second signal n2, and the gate of the thirty-eighth NMOS transistor M38 is configured to obtain a second inverted signal n2b;

[0153] The source of the thirty-sixth PMOS transistor M36 and the source of the thirty-seventh PMOS transistor M37 are connected with the output end OUT of the low-dropout linear regulator respectively, the source of the thirty-eighth NMOS transistor M38 and the source of the thirty-ninth NMOS transistor M39 are connected with the ground end vssa respectively, the drain of the thirty-sixth PMOS transistor M36 is connected with the drain of the thirty-eighth NMOS transistor M38 and the first end of the second capacitor C2 respectively, the drain of the thirty-seventh PMOS transistor M37 is connected with the drain of the thirty-ninth NMOS transistor M39 and the first end of the third capacitor C3 respectively; the second end of the second capacitor C2 is connected with the drain of the thirty-second PMOS transistor M32, the drain of the thirty-fourth NMOS transistor M34, the gate of the thirty-third PMOS transistor M33 and the gate of the thirty-fifth NMOS transistor M35 respectively, the second end of the third capacitor C3 is connected with the drain of the thirty-third PMOS transistor M33, the drain of the thirty-fifth NMOS transistor M35, the gate of the thirty-second PMOS transistor M32 and the gate of the thirty-fourth NMOS transistor M34 respectively; the source of the thirty-second PMOS transistor M32 and the source of the thirty-third PMOS transistor M33 are connected with the ground end vssa respectively, the source of the thirty-fourth NMOS transistor M34 and the source of the thirty-fifth NMOS transistor M35 are connected with the first end of the fifth resistor R5 respectively, the second end of the fifth resistor R5 is connected with the first end of the fourth capacitor C4 and configured to output the negative voltage vneg, and the second end of the fourth capacitor C4 is connected with the ground end vssa.

[0154] In the embodiment, the charge pump is powered by the stable voltage vout_ref or the power voltage vdda, so that the stability of the negative voltage output is improved.

[0155] Reference Figure 2 In an optional embodiment, the negative voltage generating circuit further comprises an oscillator and a clock buffer;

[0156] The power supply end of the oscillator and the power supply end of the clock buffer are configured to obtain the stable voltage vout_ref output by the low-dropout linear regulator in the normal working mode or the power voltage vdda output by the low-dropout linear regulator in the bypass mode respectively;

[0157] The oscillator is configured to output an oscillation signal;

[0158] The clock buffer is configured to generate two opposite clock signals according to the oscillation signal, so that the charge pump determines the first signal, the first inverse signal, the second signal and the second inverse signal according to the clock signals.

[0159] Thus, the low dropout linear regulator with the bypass mode supplies power to the oscillator and the clock buffer respectively, and the oscillator and the clock buffer can work normally regardless of whether the LDO can work normally due to the reduction of the power supply voltage, thereby improving the stability of the output of the negative voltage generation circuit.

[0160] In the embodiments of the present application, the first signal and the second signal can be two opposite clock signals output by the clock buffer, or can be signals after being localized by inverters to improve stability. The first inverted signal can be a signal obtained by inverting the first signal, and the second inverted signal can be a signal obtained by inverting the second signal.

[0161] The oscillator and the clock buffer can be set according to actual requirements, and the present application does not make detailed introduction.

[0162] The embodiments of the present application also provide a radio frequency module, which can include the low dropout linear regulator with the bypass mode of the above embodiments, or the negative voltage generation circuit of the above embodiments.

[0163] It should be understood that the above embodiments are exemplary and are not intended to include all possible implementations of the claims. Various modifications and changes can also be made on the basis of the above embodiments without departing from the scope of the present disclosure. Similarly, any combination of the technical features of the above embodiments can also be made to form additional embodiments of the present application that can not be explicitly described. Therefore, the above embodiments only express several implementation manners of the present application, and do not limit the protection scope of the patent of the present application.

Claims

1. A low dropout linear regulator with a bypass mode, characterized by, The low-dropout linear regulator comprises: a bypass mode switching circuit configured to switch a working mode of the low-dropout linear regulator according to a power supply voltage; and a power tube configured as an output transistor of the low-dropout linear regulator for outputting a stable voltage; wherein the working mode comprises a normal working mode and a bypass mode; in a case where the power supply voltage is lower than a power supply voltage threshold, the bypass mode switching circuit switches the working mode of the low-dropout linear regulator to the bypass mode, so that a loop of the low-dropout linear regulator is disabled, and an output end of the low-dropout linear regulator outputs the power supply voltage; in a case where the power supply voltage is higher than the power supply voltage threshold, the bypass mode switching circuit switches the working mode of the low-dropout linear regulator to the normal working mode, so that the low-dropout linear regulator normally works, and the output end of the low-dropout linear regulator outputs the stable voltage output by the power tube, to ensure that the output end of the low-dropout linear regulator can output a voltage regardless of whether the low-dropout linear regulator can normally work due to the power supply voltage, so that the output is continuous and uninterrupted; the bypass mode switching circuit comprises: a switching control module configured to generate corresponding start-stop signals and bypass signals according to the power supply voltage, comprising: a voltage dividing module configured to divide the power supply voltage to obtain a divided voltage; a comparator configured to generate a first-level comparison output signal in a case where the divided voltage is lower than a second reference voltage, and generate a second-level comparison output signal in a case where the divided voltage is higher than the second reference voltage; a first inverter configured to invert the comparison output signal to obtain the bypass signal; and a second inverter configured to invert the bypass signal to obtain the start-stop signal; a first switch module configured to be turned on or turned off under the control of the bypass signal, so that the output end of the low-dropout linear regulator switches to output the power supply voltage or the stable voltage; and a second switch module configured to be turned on or turned off under the control of the start-stop signal, so that the power tube is turned off to disable the loop of the low-dropout linear regulator, or the power tube is turned on to make the low-dropout linear regulator normally work; the first switch module comprises a second switch NMOS tube; the second switch module comprises a first switch PMOS tube; a gate of the second switch NMOS tube is configured to obtain the bypass signal, a drain of the second switch NMOS tube is configured to obtain the power supply voltage, and a source of the second switch NMOS tube is connected to the output end of the low-dropout linear regulator; a gate of the first switch PMOS tube is configured to obtain the start-stop signal, a source of the first switch PMOS tube is configured to obtain the power supply voltage, and a drain of the first switch PMOS tube is connected to a control end of the power tube.

2. The low-dropout linear regulator according to claim 1, wherein the voltage dividing module comprises a third resistor and a fourth resistor; a first end of the third resistor is configured to obtain the power supply voltage, a second end of the third resistor is connected to a first input end of the comparator and a first end of the fourth resistor, and is configured to provide the divided voltage; a second end of the fourth resistor is grounded.

3. The low-dropout linear regulator according to claim 1, wherein The comparator comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth PMOS transistor, a fifth NMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh NMOS transistor, a twelfth PMOS transistor, a thirteenth NMOS transistor, a fourteenth PMOS transistor and a fifteenth NMOS transistor; a gate of the first NMOS transistor is configured as a first input terminal of the comparator, and a gate of the second NMOS transistor is configured as a second input terminal of the comparator and obtains a second reference voltage; a source of the first NMOS transistor and a source of the second NMOS transistor are respectively connected with a drain of the third NMOS transistor, a source of the third NMOS transistor is connected with a ground terminal, and a gate of the third NMOS transistor is configured to obtain a first low bias voltage; a drain of the first NMOS transistor is respectively connected with a gate of the fourth PMOS transistor, a drain of the sixth PMOS transistor, a gate of the sixth PMOS transistor, a gate of the seventh PMOS transistor and a drain of the eighth PMOS transistor; a drain of the second NMOS transistor is respectively connected with a gate of the tenth PMOS transistor, a drain of the ninth PMOS transistor, a gate of the ninth PMOS transistor, a gate of the eighth PMOS transistor and a drain of the seventh PMOS transistor; a source of the fourth PMOS transistor, a source of the sixth PMOS transistor, a source of the seventh PMOS transistor, a source of the eighth PMOS transistor, a source of the ninth PMOS transistor and a source of the tenth PMOS transistor are respectively configured to obtain a power supply voltage; a drain of the fourth PMOS transistor is respectively connected with a drain of the fifth NMOS transistor, a gate of the fifth NMOS transistor and a gate of the eleventh NMOS transistor; a drain of the tenth PMOS transistor is respectively connected with a drain of the eleventh NMOS transistor, a gate of the twelfth PMOS transistor and a gate of the thirteenth NMOS transistor; a drain of the twelfth PMOS transistor is respectively connected with a drain of the thirteenth NMOS transistor, a gate of the fourteenth PMOS transistor and a gate of the fifteenth NMOS transistor; a source of the twelfth PMOS transistor and a source of the fourteenth PMOS transistor are respectively configured to obtain the power supply voltage; a source of the fifth NMOS transistor, a source of the eleventh NMOS transistor, a source of the thirteenth NMOS transistor and a source of the fifteenth NMOS transistor are respectively connected with a ground terminal; a drain of the fourteenth PMOS transistor and a drain of the fifteenth NMOS transistor are connected and configured as an output terminal of the comparator.

4. The low dropout linear regulator according to any one of claims 1-3, wherein, The low-dropout linear voltage regulator with a bypass mode further comprises an error amplifier and a feedback circuit; a first input terminal of the error amplifier is configured to obtain the first reference voltage, a second input terminal of the error amplifier is connected with an output terminal of the feedback circuit, and an output terminal of the error amplifier is connected with a gate terminal of the power transistor; an input terminal of the feedback circuit is connected with an output terminal of the low-dropout linear voltage regulator.

5. The low-dropout linear voltage regulator according to claim 4, wherein The error amplifier comprises a sixteenth PMOS transistor, a seventeenth PMOS transistor, an eighteenth PMOS transistor, a nineteenth NMOS transistor, a twentieth NMOS transistor, a twenty-first NMOS transistor, a twenty-second NMOS transistor, a twenty-third NMOS transistor, a twenty-fourth NMOS transistor, a twenty-fifth PMOS transistor, a twenty-sixth PMOS transistor and a compensation capacitor; a gate of the sixteenth PMOS transistor is configured as a first input end of the error amplifier, and a gate of the seventeenth PMOS transistor is configured as a second input end of the error amplifier; a drain of the sixteenth PMOS transistor is connected with a drain, a gate and a gate of the nineteenth NMOS transistor and the twentieth NMOS transistor respectively, a drain of the seventeenth PMOS transistor is connected with a drain, a gate and a gate of the twenty-first NMOS transistor and the twenty-second NMOS transistor respectively, a drain of the twentieth NMOS transistor is connected with a source of the twenty-third NMOS transistor, a drain of the twenty-second NMOS transistor is connected with a source of the twenty-fourth NMOS transistor, a drain of the twenty-third NMOS transistor is connected with a drain, a gate and a gate of the twenty-fifth PMOS transistor and the twenty-sixth PMOS transistor respectively, and a drain of the twenty-fourth NMOS transistor is connected with a drain of the twenty-sixth PMOS transistor and configured as an output end of the error amplifier; a source of the sixteenth PMOS transistor and a source of the seventeenth PMOS transistor are connected with a drain of the eighteenth PMOS transistor respectively, a source of the eighteenth PMOS transistor, a source of the twenty-fifth PMOS transistor and a source of the twenty-sixth PMOS transistor are configured to obtain a power supply voltage respectively, a source of the nineteenth NMOS transistor, a source of the twentieth NMOS transistor, a source of the twenty-first NMOS transistor and a source of the twenty-second NMOS transistor are connected with ground ends respectively; a gate of the twenty-third NMOS transistor and a gate of the twenty-fourth NMOS transistor are configured to obtain a second low bias voltage respectively, and a gate of the eighteenth PMOS transistor is configured to obtain a first high bias voltage; a first end of the compensation capacitor is connected with the drain of the twenty-second NMOS transistor and the source of the twenty-fourth NMOS transistor respectively, and a second end of the compensation capacitor is connected with an output end of the low-dropout linear voltage regulator; and / or, the feedback circuit comprises a first resistor and a second resistor; the second input end of the error amplifier is connected with a second end of the first resistor and a first end of the second resistor respectively, a first end of the first resistor is connected with the output end of the low-dropout linear voltage regulator, and a second end of the second resistor is connected with a ground end.

6. A negative voltage generating circuit characterized by comprising: The negative voltage generating circuit comprises a charge pump and the low-dropout linear voltage regulator with a bypass mode according to any one of claims 1-5; the power supply end of the charge pump is configured to obtain a stable voltage output by the low-dropout linear voltage regulator in a normal working mode or a power supply voltage output by the low-dropout linear voltage regulator in a bypass mode; the charge pump is configured to output a stable negative voltage under the power supply of the voltage obtained at the power supply end.

7. The negative voltage generating circuit according to claim 6, wherein The charge pump comprises a thirty-sixth PMOS transistor, a thirty-seventh PMOS transistor, a thirty-eighth NMOS transistor, a thirty-ninth NMOS transistor, a second capacitor, a third capacitor, a thirty-second PMOS transistor, a thirty-third PMOS transistor, a thirty-fourth NMOS transistor, a thirty-fifth NMOS transistor, a fifth resistor and a fourth capacitor; a gate of the thirty-sixth PMOS transistor is configured to obtain a first signal, and a gate of the thirty-ninth NMOS transistor is configured to obtain a first inverted signal; a gate of the thirty-seventh PMOS transistor is configured to obtain a second signal, and a gate of the thirty-eighth NMOS transistor is configured to obtain a second inverted signal; a source of the thirty-sixth PMOS transistor and a source of the thirty-seventh PMOS transistor are connected with an output end of the low-dropout linear regulator respectively, a source of the thirty-eighth NMOS transistor and a source of the thirty-ninth NMOS transistor are connected with a ground end respectively, a drain of the thirty-sixth PMOS transistor is connected with a drain of the thirty-eighth NMOS transistor and a first end of the second capacitor respectively, and a drain of the thirty-seventh PMOS transistor is connected with a drain of the thirty-ninth NMOS transistor and a first end of the third capacitor respectively; a second end of the second capacitor is connected with a drain of the thirty-second PMOS transistor, a drain of the thirty-fourth NMOS transistor, a gate of the thirty-third PMOS transistor and a gate of the thirty-fifth NMOS transistor respectively, and a second end of the third capacitor is connected with a drain of the thirty-third PMOS transistor, a drain of the thirty-fifth NMOS transistor, a gate of the thirty-second PMOS transistor and a gate of the thirty-fourth NMOS transistor respectively; a source of the thirty-second PMOS transistor and a source of the thirty-third PMOS transistor are connected with a ground end respectively, a source of the thirty-fourth NMOS transistor and a source of the thirty-fifth NMOS transistor are connected with a first end of the fifth resistor respectively, a second end of the fifth resistor is connected with a first end of the fourth capacitor and configured to output a negative voltage, and a second end of the fourth capacitor is connected with a ground end.

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