A CMOS low voltage high-order temperature compensated voltage reference

Abstract

This invention relates to a CMOS low-voltage high-order temperature-compensated voltage reference. The voltage reference includes: a voltage reference startup circuit, an operational amplifier with startup and bias circuits, a temperature-dependent circuit, and an active load circuit. The voltage reference startup circuit is used to remove the voltage reference from abnormal states caused by the degeneracy point. The operational amplifier with startup and bias circuits enables the temperature-dependent circuit to operate normally. The temperature-dependent circuit generates temperature-dependent current and voltage. The temperature-dependent current and voltage generate a high-order temperature-compensated voltage reference on the active load circuit. This invention can operate at low supply voltages, and the high-order temperature compensation reduces the temperature drift of the voltage reference.

Description

Technical Field

[0001] The invention relates to the field of electronic technology, and in particular to a CMOS low-voltage high-order temperature compensated voltage reference source. Background Art

[0002] A voltage reference is a circuit used in electronic systems to provide a reference voltage that does not change with power supply voltage and temperature. Voltage references play a key role in ensuring accurate circuit operation. Voltage references are widely used in analog-to-digital mixed circuits, communication equipment, measuring instruments and other fields.

[0003] Traditional triode-based bandgap references have the problems of excessive power consumption and high supply voltage, which is not conducive to low-voltage and low-power applications. In contrast, CMOS voltage references have the advantages of lower power consumption and easier integration. With the continuous development of electronic technology, the supply voltage of voltage references is required to be further reduced, and the reference voltage output by the voltage reference is required to have a lower temperature coefficient. Therefore, how to design a CMOS low-voltage and low-temperature-coefficient voltage reference source is becoming a hot spot and difficulty in the research of voltage reference sources. Summary of the invention

[0004] The purpose of the present invention is to provide a CMOS low-voltage high-order temperature compensated voltage reference source to solve the problems raised in the above background technology;

[0005] To achieve the above object, the present invention provides the following technical solution: a CMOS low-voltage high-order temperature-compensated voltage reference source, the voltage reference source comprising: a voltage reference startup circuit, an operational amplifier with a startup circuit and a bias circuit, a temperature positive correlation circuit, and an active load circuit;

[0006] The voltage reference startup circuit is used to make the voltage reference source leave the abnormal state caused by the degeneracy point; the operational amplifier with the startup circuit and the bias circuit makes the temperature positive correlation circuit work normally; the temperature positive correlation circuit generates a current and voltage that are positively correlated with temperature; the voltage and current generated by the temperature positive correlation circuit generate a high-order temperature compensated voltage reference on the active load circuit; the temperature positively correlated voltage generated by the temperature positive correlation circuit is added to the temperature negatively correlated threshold voltage of the active load PMOS transistor of the active load circuit to form a voltage reference; the temperature positively correlated current generated by the temperature positive correlation circuit forms an overdrive voltage on the active load PMOS transistor of the active load circuit, and the overdrive voltage performs high-order temperature compensation on the voltage reference; the output voltage of the voltage reference is a high-order temperature compensated voltage reference formed by adding the temperature positively correlated voltage generated by the temperature positive correlation circuit, the temperature negatively correlated threshold voltage of the active load PMOS transistor of the active load circuit, and the overdrive voltage of the active load PMOS transistor.

[0007] The temperature positive correlation circuit can generate a temperature positively correlated current and a temperature positively correlated voltage; in the absence of a circuit that generates a temperature negatively correlated current and a high-order temperature compensation circuit, the active load circuit uses the temperature positively correlated voltage and the temperature positively correlated current to generate a high-order temperature compensated voltage reference.

[0008] The output voltage V1 generated by the temperature positive correlation circuit is connected to the positive input terminal of the operational amplifier with a startup circuit and a bias circuit; the output voltage V2 generated by the temperature positive correlation circuit is connected to the negative input terminal of the operational amplifier with a startup circuit and a bias circuit; the input voltage V3 generated by the temperature positive correlation circuit is connected to the output terminal of the operational amplifier with a startup circuit and a bias circuit; the output voltage V4 generated by the temperature positive correlation circuit is connected to an input terminal of the active load circuit; the other input terminal of the active load circuit is connected to the output terminal of the operational amplifier with a startup circuit and a bias circuit; the output terminal of the active load circuit is connected to REF; the output terminal of the voltage reference startup circuit is connected to the input voltage V3 of the temperature positive correlation circuit.

[0009] The voltage reference startup circuit includes a PMOS transistor PM1, a PMOS transistor PM2, and an NMOS transistor NM1; the source of the PMOS transistor PM1 is electrically connected to VDD; the gate of the PMOS transistor PM1 is electrically connected to GND; the source of the NMOS transistor NM1 and the drain of the NMOS transistor NM1 are electrically connected to GND; the gate of the NMOS transistor NM1, the gate of the PMOS transistor PM2, and the drain of the PMOS transistor PM1 are electrically connected to each other; the drain of the PMOS transistor PM2 is electrically connected to GND; the source of the PMOS transistor PM2 is connected to the input voltage V3 of the temperature positive correlation circuit.

[0010] The temperature positive correlation circuit includes a PMOS transistor PM3, a PMOS transistor PM4, an NMOS transistor NM2, an NMOS transistor NM3, a resistor R1, and a resistor R2; the source of the PMOS transistor PM3 and the source of the PMOS transistor PM4 are electrically connected to VDD; one end of the resistor R1 is electrically connected to the source of the NMOS transistor NM2; the other end of the resistor R1 is electrically connected to GND; one end of the resistor R2 is electrically connected to the source of the NMOS transistor NM3; the other end of the resistor R2 is electrically connected to GND; the The gate, the drain of the NMOS transistor NM2, and the drain of the PMOS transistor PM3 are electrically connected to each other; the gate of the NMOS transistor NM3, the drain of the NMOS transistor NM3, and the drain of the PMOS transistor PM4 are electrically connected to each other; the gate of the PMOS transistor PM3 and the gate of the PMOS transistor PM4 are electrically connected together; the output voltage V1 is connected to the drain of the NMOS transistor NM3; the output voltage V2 is connected to the drain of the NMOS transistor NM2; the input voltage V3 is connected to the gate of the PMOS transistor PM3; and the output voltage V4 is connected to one end of the resistor R1.

[0011] The operational amplifier with a startup circuit and a bias circuit comprises: a differential operational amplifier, a startup circuit of the operational amplifier, and a bias circuit of the operational amplifier;

[0012] The operational amplifier startup circuit is used to start the operational amplifier bias circuit and the differential operational amplifier; the operational amplifier bias circuit is used to provide bias for the differential operational amplifier; the differential operational amplifier makes the voltage V1 and the voltage V2 equal through negative feedback, so that the temperature positive correlation circuit works normally.

[0013] The bias circuit of the operational amplifier includes a PMOS transistor PM12, a PMOS transistor PM13, an NMOS transistor NM8, an NMOS transistor NM9, and an NMOS transistor NM10; the source of the PMOS transistor PM12 and the source of the PMOS transistor PM13 are electrically connected to VDD; the source of the NMOS transistor NM8 and the source of the NMOS transistor NM10 are electrically connected to GND; the drain of the PMOS transistor PM12, the drain of the NMOS transistor NM8, the gate of the NMOS transistor NM8, and the gate of the NMOS transistor NM9 are electrically connected to each other; the source of the NMOS transistor NM9 is electrically connected to the drain of the NMOS transistor NM10; the gate of the PMOS transistor PM12, the gate of the PMOS transistor PM13, the drain of the PMOS transistor PM13, and the drain of the NMOS transistor NM9 are electrically connected to each other.

[0014] The differential operational amplifier includes a PMOS transistor PM5, a PMOS transistor PM6, a PMOS transistor PM7, a PMOS transistor PM8, a PMOS transistor PM9, an NMOS transistor NM4, an NMOS transistor NM5, an NMOS transistor NM6, and an NMOS transistor NM7; the source of the NMOS transistor NM4, the source of the NMOS transistor NM5, the source of the NMOS transistor NM6, and the source of the NMOS transistor NM7 are electrically connected to GND; the source of the PMOS transistor PM5, the source of the PMOS transistor PM6, and the source of the PMOS transistor PM9 are electrically connected to VDD; the gate of the PMOS transistor PM5, the gate of the PMOS transistor PM5, the gate of the PMOS transistor PM6, and the gate of the PMOS transistor PM7 are electrically connected to GND; the gate of the PMOS transistor PM5, the gate of the PMOS transistor PM6, and the gate of the PMOS transistor PM7 are electrically connected to VDD; the gate of the PMOS transistor PM5, the gate of the PMOS transistor PM6, and the gate of the PMOS transistor PM7 are electrically connected to GND; the gate of the PMOS transistor PM5, the gate of the PMOS transistor PM6, and the gate of the PMOS transistor PM7 are electrically connected to GND; the gate of the PMOS transistor PM5, the gate of the PMOS transistor PM6, and the gate of the PMOS transistor PM7 are electrically connected to GND; the gate of the PMOS transistor PM5, the gate of the PMOS transistor PM7 ... The drain, the drain of NMOS transistor NM4, and the gate of PMOS transistor PM9 are electrically connected to each other; the gate of NMOS transistor NM4, the gate of NMOS transistor NM5, the drain of NMOS transistor NM5, and the drain of PMOS transistor PM7 are electrically connected to each other; the gate of NMOS transistor NM6, the gate of NMOS transistor NM7, the drain of NMOS transistor NM6, and the drain of PMOS transistor PM8 are electrically connected to each other; the drain of PMOS transistor PM6, the source of PMOS transistor PM7, and the source of PMOS transistor PM8 are electrically connected to each other; the gate of PMOS transistor PM6 is electrically connected to the gate of PMOS transistor PM13.

[0015] The startup circuit of the operational amplifier includes a PMOS transistor PM15, a PMOS transistor PM14, and an NMOS transistor NM11; the source of the PMOS transistor PM15 is electrically connected to VDD; the gate of the PMOS transistor PM15 is electrically connected to GND; the source of the NMOS transistor NM11 and the drain of the NMOS transistor NM11 are electrically connected to GND; the gate of the NMOS transistor NM11, the gate of the PMOS transistor PM14, and the drain of the PMOS transistor PM15 are electrically connected to each other; the drain of the PMOS transistor PM14 is electrically connected to GND; the source of the PMOS transistor PM14, the gate of the PMOS transistor PM12, and the gate of the PMOS transistor PM13 are electrically connected to each other.

[0016] The active load circuit includes a PMOS transistor PM10 and a PMOS transistor PM11; the source of the PMOS transistor PM10 is electrically connected to VDD; the drain of the PMOS transistor PM11 is electrically connected to GND; the drain of the PMOS transistor PM10 and the source of the PMOS transistor PM11 are electrically connected to REF; REF is the output end of the voltage reference source.

[0017] When the voltage reference source operates normally, the NMOS transistor NM2 and the NMOS transistor NM3 are in the subthreshold region, the voltage across the resistor R1 is a voltage that is positively correlated with the temperature, the source-drain currents of the PMOS transistors PM3 and PM4 are currents that are positively correlated with the temperature; the source-drain current of the PMOS transistor PM10 proportionally replicates the source-drain current of the PMOS transistor PM3, and the source-drain current of the PMOS transistor PM10 is a current that is positively correlated with the temperature; the overdrive voltage of the PMOS transistor PM11 is determined by the source-drain current of the PMOS transistor PM10; the voltage across the resistor R1 is a voltage that is positively correlated with the temperature, and the source-drain current of the PMOS transistor ...4 is a current that is positively correlated with the temperature. The threshold voltage of the body transistor PM11 is negatively correlated with the temperature, and the two are added to form a voltage reference; the over-drive voltage of the PMOS transistor PM11 performs high-order compensation on the voltage reference; the gate-source voltage of the PMOS transistor PM11 is equal to the sum of the threshold voltage of the PMOS transistor PM11 and the over-drive voltage of the PMOS transistor PM11; the REF voltage is equal to the sum of the gate-source voltage of the PMOS transistor PM11 and the voltage across the resistor R1; the REF voltage is a high-order temperature-compensated voltage reference formed by the sum of the voltage across the resistor R1, the threshold voltage of the PMOS transistor PM11, and the over-drive voltage of the PMOS transistor PM11.

[0018] A voltage V1 of a CMOS low-voltage high-order temperature-compensated voltage reference source, a voltage V1 of a temperature-correlated circuit of the voltage reference source, and a voltage V1 of an operational amplifier with a startup circuit and a bias circuit are the same voltage. A voltage V2 of a CMOS low-voltage high-order temperature-compensated voltage reference source, a voltage V2 of a temperature-correlated circuit of the voltage reference source, and a voltage V2 of an operational amplifier with a startup circuit and a bias circuit are the same voltage. A voltage V3 of a CMOS low-voltage high-order temperature-compensated voltage reference source, a voltage V3 of a temperature-correlated circuit of the voltage reference source, and a voltage V3 of an operational amplifier with a startup circuit and a bias circuit are the same voltage. A voltage V4 of a CMOS low-voltage high-order temperature-compensated voltage reference source and a voltage V4 of a temperature-correlated circuit of the voltage reference source are the same voltage.

[0019] Compared with the prior art, the present invention implements a CMOS low-voltage high-order temperature compensated voltage reference source according to the above technical solution, which is composed of CMOS and resistors and can work under low power supply voltage. The high-order temperature compensation is used to reduce the temperature drift of the voltage reference source. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram of a voltage reference source module for CMOS low-voltage high-order temperature compensation according to the present invention;

[0021] Figure 2A schematic diagram of a CMOS low-voltage high-order temperature compensated voltage reference source according to the present invention;

[0022] Figure 3 A schematic diagram of a temperature positive correlation circuit of a CMOS low voltage high-order temperature compensated voltage reference source of the present invention;

[0023] Figure 4 A schematic diagram of an operational amplifier with a startup circuit and a bias circuit for a CMOS low-voltage high-order temperature-compensated voltage reference source of the present invention;

[0024] Figure 5 A simulation result diagram of a temperature characteristic curve of an output voltage of a CMOS low-voltage high-order temperature-compensated voltage reference source according to the present invention;

[0025] Figure 6 A simulation result diagram of the output voltage of a CMOS low-voltage high-order temperature-compensated voltage reference source according to the present invention changing with the power supply voltage; DETAILED DESCRIPTION

[0026] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] Example 1

[0028] The present embodiment describes a CMOS low voltage high-order temperature compensated voltage reference source. The module composition diagram of the voltage reference source is as follows: Figure 1 The circuit diagram of the voltage reference source is shown in Figure 2 The voltage reference source includes: a voltage reference startup circuit, an operational amplifier with a startup circuit and a bias circuit, a temperature positive correlation circuit, and an active load circuit;

[0029] The voltage reference startup circuit is used to make the voltage reference source leave the abnormal state caused by the degeneracy point; the operational amplifier with the startup circuit and the bias circuit makes the temperature positive correlation circuit work normally; the temperature positive correlation circuit generates a current and voltage that are positively correlated with temperature; the voltage and current generated by the temperature positive correlation circuit generate a high-order temperature compensated voltage reference on the active load circuit; the temperature positively correlated voltage generated by the temperature positive correlation circuit is added to the temperature negatively correlated threshold voltage of the active load PMOS transistor of the active load circuit to form a voltage reference; the temperature positively correlated current generated by the temperature positive correlation circuit forms an overdrive voltage on the active load PMOS transistor of the active load circuit, and the overdrive voltage performs high-order temperature compensation on the voltage reference; the output voltage of the voltage reference is a high-order temperature compensated voltage reference formed by adding the temperature positively correlated voltage generated by the temperature positive correlation circuit, the temperature negatively correlated threshold voltage of the active load PMOS transistor of the active load circuit, and the overdrive voltage of the active load PMOS transistor.

[0030] The temperature positive correlation circuit can generate a temperature positively correlated current and a temperature positively correlated voltage; in the absence of a circuit that generates a temperature negatively correlated current and a high-order temperature compensation circuit, the active load circuit uses the temperature positively correlated voltage and the temperature positively correlated current to generate a high-order temperature compensated voltage reference.

[0031] The output voltage V1 generated by the temperature positive correlation circuit is connected to the positive input terminal of the operational amplifier with a startup circuit and a bias circuit; the output voltage V2 generated by the temperature positive correlation circuit is connected to the negative input terminal of the operational amplifier with a startup circuit and a bias circuit; the input voltage V3 generated by the temperature positive correlation circuit is connected to the output terminal of the operational amplifier with a startup circuit and a bias circuit; the output voltage V4 generated by the temperature positive correlation circuit is connected to an input terminal of the active load circuit; the other input terminal of the active load circuit is connected to the output terminal of the operational amplifier with a startup circuit and a bias circuit; the output terminal of the active load circuit is connected to REF; the output terminal of the voltage reference startup circuit is connected to the input voltage V3 of the temperature positive correlation circuit.

[0032] The voltage reference startup circuit includes a PMOS transistor PM1, a PMOS transistor PM2, and an NMOS transistor NM1; the source of the PMOS transistor PM1 is electrically connected to VDD; the gate of the PMOS transistor PM1 is electrically connected to GND; the source of the NMOS transistor NM1 and the drain of the NMOS transistor NM1 are electrically connected to GND; the gate of the NMOS transistor NM1, the gate of the PMOS transistor PM2, and the drain of the PMOS transistor PM1 are electrically connected to each other; the drain of the PMOS transistor PM2 is electrically connected to GND; the source of the PMOS transistor PM2 is connected to the input voltage V3 of the temperature positive correlation circuit.

[0033] The temperature positive correlation circuit includes a PMOS transistor PM3, a PMOS transistor PM4, an NMOS transistor NM2, an NMOS transistor NM3, a resistor R1, and a resistor R2; the source of the PMOS transistor PM3 and the source of the PMOS transistor PM4 are electrically connected to VDD; one end of the resistor R1 is electrically connected to the source of the NMOS transistor NM2; the other end of the resistor R1 is electrically connected to GND; one end of the resistor R2 is electrically connected to the source of the NMOS transistor NM3; the other end of the resistor R2 is electrically connected to GND; the The gate, the drain of the NMOS transistor NM2, and the drain of the PMOS transistor PM3 are electrically connected to each other; the gate of the NMOS transistor NM3, the drain of the NMOS transistor NM3, and the drain of the PMOS transistor PM4 are electrically connected to each other; the gate of the PMOS transistor PM3 and the gate of the PMOS transistor PM4 are electrically connected together; the output voltage V1 is connected to the drain of the NMOS transistor NM3; the output voltage V2 is connected to the drain of the NMOS transistor NM2; the input voltage V3 is connected to the gate of the PMOS transistor PM3; and the output voltage V4 is connected to one end of the resistor R1.

[0034] The operational amplifier with a startup circuit and a bias circuit comprises: a differential operational amplifier, a startup circuit of the operational amplifier, and a bias circuit of the operational amplifier;

[0035] The operational amplifier startup circuit is used to start the operational amplifier bias circuit and the differential operational amplifier; the operational amplifier bias circuit is used to provide bias for the differential operational amplifier; the differential operational amplifier makes the voltage V1 and the voltage V2 equal through negative feedback, so that the temperature positive correlation circuit works normally.

[0036] The bias circuit of the operational amplifier includes a PMOS transistor PM12, a PMOS transistor PM13, an NMOS transistor NM8, an NMOS transistor NM9, and an NMOS transistor NM10; the source of the PMOS transistor PM12 and the source of the PMOS transistor PM13 are electrically connected to VDD; the source of the NMOS transistor NM8 and the source of the NMOS transistor NM10 are electrically connected to GND; the drain of the PMOS transistor PM12, the drain of the NMOS transistor NM8, the gate of the NMOS transistor NM8, and the gate of the NMOS transistor NM9 are electrically connected to each other; the source of the NMOS transistor NM9 is electrically connected to the drain of the NMOS transistor NM10; the gate of the PMOS transistor PM12, the gate of the PMOS transistor PM13, the drain of the PMOS transistor PM13, and the drain of the NMOS transistor NM9 are electrically connected to each other.

[0037] The differential operational amplifier includes a PMOS transistor PM5, a PMOS transistor PM6, a PMOS transistor PM7, a PMOS transistor PM8, a PMOS transistor PM9, an NMOS transistor NM4, an NMOS transistor NM5, an NMOS transistor NM6, and an NMOS transistor NM7; the source of the NMOS transistor NM4, the source of the NMOS transistor NM5, the source of the NMOS transistor NM6, and the source of the NMOS transistor NM7 are electrically connected to GND; the source of the PMOS transistor PM5, the source of the PMOS transistor PM6, and the source of the PMOS transistor PM9 are electrically connected to VDD; the gate of the PMOS transistor PM5, the gate of the PMOS transistor PM5, the gate of the PMOS transistor PM6, and the gate of the PMOS transistor PM7 are electrically connected to GND; the gate of the PMOS transistor PM5, the gate of the PMOS transistor PM6, and the gate of the PMOS transistor PM7 are electrically connected to VDD; the gate of the PMOS transistor PM5, the gate of the PMOS transistor PM6, and the gate of the PMOS transistor PM7 are electrically connected to GND; the gate of the PMOS transistor PM5, the gate of the PMOS transistor PM6, and the gate of the PMOS transistor PM7 are electrically connected to GND; the gate of the PMOS transistor PM5, the gate of the PMOS transistor PM6, and the gate of the PMOS transistor PM7 are electrically connected to GND; the gate of the PMOS transistor PM5, the gate of the PMOS transistor PM7 ... The drain, the drain of NMOS transistor NM4, and the gate of PMOS transistor PM9 are electrically connected to each other; the gate of NMOS transistor NM4, the gate of NMOS transistor NM5, the drain of NMOS transistor NM5, and the drain of PMOS transistor PM7 are electrically connected to each other; the gate of NMOS transistor NM6, the gate of NMOS transistor NM7, the drain of NMOS transistor NM6, and the drain of PMOS transistor PM8 are electrically connected to each other; the drain of PMOS transistor PM6, the source of PMOS transistor PM7, and the source of PMOS transistor PM8 are electrically connected to each other; the gate of PMOS transistor PM6 is electrically connected to the gate of PMOS transistor PM13.

[0038] The startup circuit of the operational amplifier includes a PMOS transistor PM15, a PMOS transistor PM14, and an NMOS transistor NM11; the source of the PMOS transistor PM15 is electrically connected to VDD; the gate of the PMOS transistor PM15 is electrically connected to GND; the source of the NMOS transistor NM11 and the drain of the NMOS transistor NM11 are electrically connected to GND; the gate of the NMOS transistor NM11, the gate of the PMOS transistor PM14, and the drain of the PMOS transistor PM15 are electrically connected to each other; the drain of the PMOS transistor PM14 is electrically connected to GND; the source of the PMOS transistor PM14, the gate of the PMOS transistor PM12, and the gate of the PMOS transistor PM13 are electrically connected to each other.

[0039] The active load circuit includes a PMOS transistor PM10 and a PMOS transistor PM11; the source of the PMOS transistor PM10 is electrically connected to VDD; the drain of the PMOS transistor PM11 is electrically connected to GND; the drain of the PMOS transistor PM10 and the source of the PMOS transistor PM11 are electrically connected to REF; REF is the output end of the voltage reference source.

[0040] When the voltage reference source operates normally, the NMOS transistor NM2 and the NMOS transistor NM3 are in the subthreshold region, the voltage across the resistor R1 is a voltage that is positively correlated with the temperature, the source-drain currents of the PMOS transistors PM3 and PM4 are currents that are positively correlated with the temperature; the source-drain current of the PMOS transistor PM10 proportionally replicates the source-drain current of the PMOS transistor PM3, and the source-drain current of the PMOS transistor PM10 is a current that is positively correlated with the temperature; the overdrive voltage of the PMOS transistor PM11 is determined by the source-drain current of the PMOS transistor PM10; the voltage across the resistor R1 is a voltage that is positively correlated with the temperature, and the source-drain current of the PMOS transistor ...4 is a current that is positively correlated with the temperature. The threshold voltage of the body transistor PM11 is negatively correlated with the temperature, and the two are added to form a voltage reference; the over-drive voltage of the PMOS transistor PM11 performs high-order compensation on the voltage reference; the gate-source voltage of the PMOS transistor PM11 is equal to the sum of the threshold voltage of the PMOS transistor PM11 and the over-drive voltage of the PMOS transistor PM11; the REF voltage is equal to the sum of the gate-source voltage of the PMOS transistor PM11 and the voltage across the resistor R1; the REF voltage is a high-order temperature-compensated voltage reference formed by the sum of the voltage across the resistor R1, the threshold voltage of the PMOS transistor PM11, and the over-drive voltage of the PMOS transistor PM11.

[0041] A voltage V1 of a CMOS low-voltage high-order temperature-compensated voltage reference source, a voltage V1 of a temperature-correlated circuit of the voltage reference source, and a voltage V1 of an operational amplifier with a startup circuit and a bias circuit are the same voltage. A voltage V2 of a CMOS low-voltage high-order temperature-compensated voltage reference source, a voltage V2 of a temperature-correlated circuit of the voltage reference source, and a voltage V2 of an operational amplifier with a startup circuit and a bias circuit are the same voltage. A voltage V3 of a CMOS low-voltage high-order temperature-compensated voltage reference source, a voltage V3 of a temperature-correlated circuit of the voltage reference source, and a voltage V3 of an operational amplifier with a startup circuit and a bias circuit are the same voltage. A voltage V4 of a CMOS low-voltage high-order temperature-compensated voltage reference source and a voltage V4 of a temperature-correlated circuit of the voltage reference source are the same voltage.

[0042] When the MOS tube is in the subthreshold region, the current flowing through the transistor is

[0043]

[0044] K is the aspect ratio of CMOS, μ is the carrier mobility, C OX is the unit gate oxide capacitance, η is the subthreshold slope factor, V T is the thermal voltage, V GS is the gate-source voltage of CMOS, V TH is the threshold voltage of CMOS.

[0045] The operational amplifier makes the voltages of the drain of NM2 and the drain of NM3 equal, so that the temperature positive correlation circuit works normally.

[0046] V GS (NM2)+V(R1)=V GS (NM3)+V(R2)(2)

[0047] Where V GS (NM2) is the gate-source voltage of NMOS transistor NM2, V GS (NM3) is the gate-source voltage of the NMOS transistor NM3, V(R1) is the voltage across the resistor R1, and V(R2) is the voltage across the resistor R2.

[0048] The difference between the gate-source voltage of NMOS transistor NM2 and the gate-source voltage of NMOS transistor NM3 is

[0049]

[0050] Where K NM3 is the width-to-length ratio of the NMOS transistor NM3, K NM2 is the width-to-length ratio of the NMOS transistor NM2.

[0051] The voltage across resistor R1 is

[0052]

[0053] The current through the PMOS transistor PM10 is

[0054]

[0055] Among them, K PM10 is the width-to-length ratio of the PMOS transistor PM10, K PM3 is the width-to-length ratio of the PMOS transistor PM3.

[0056] At this time, the voltage at the output terminal REF of the voltage source is

[0057]

[0058] The first term is the positive temperature coefficient voltage. NM3 , K NM2 The value of K can change the positive temperature coefficient. The second term is the negative temperature coefficient voltage. The third term is used for high-order temperature compensation. PM10 Change the current I PM10 , thereby changing the intensity of temperature compensation. High-order compensation performs high-order compensation on the voltage generated by the active load circuit, thereby reducing the output voltage change of the voltage reference source caused by temperature.

[0059] The CMOS low-voltage high-order temperature compensated voltage reference source described in this embodiment is composed of CMOS and resistors, can work at a low power supply voltage, and uses high-order temperature compensation to reduce the temperature drift of the voltage reference source.

[0060] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Any simple modification, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention are still within the protection scope of the technical solution of the present invention.

Claims

1. A CMOS low voltage high-order temperature compensated voltage reference source, the voltage reference source comprising: Voltage reference startup circuit, operational amplifier with startup circuit and bias circuit, temperature positive correlation circuit, active load circuit; The voltage reference startup circuit is used to make the voltage reference source leave the abnormal state caused by the degeneracy point; the operational amplifier with the startup circuit and the bias circuit makes the temperature positive correlation circuit work normally; the temperature positive correlation circuit generates a current and voltage that are positively correlated with temperature; the voltage and current generated by the temperature positive correlation circuit generate a high-order temperature compensated voltage reference on the active load circuit; the temperature positively correlated voltage generated by the temperature positive correlation circuit is added to the temperature negatively correlated threshold voltage of the active load PMOS transistor of the active load circuit to form a voltage reference; the temperature positively correlated current generated by the temperature positive correlation circuit forms an overdrive voltage on the active load PMOS transistor of the active load circuit, and the overdrive voltage performs high-order temperature compensation on the voltage reference; the output voltage of the voltage reference is a high-order temperature compensated voltage reference formed by adding the temperature positively correlated voltage generated by the temperature positive correlation circuit, the temperature negatively correlated threshold voltage of the active load PMOS transistor of the active load circuit, and the overdrive voltage of the active load PMOS transistor.

2. A CMOS low voltage high order temperature compensated voltage reference source as claimed in claim 1, characterized in that: The temperature positive correlation circuit can generate a temperature positively correlated current and a temperature positively correlated voltage; in the absence of a circuit that generates a temperature negatively correlated current and a high-order temperature compensation circuit, the active load circuit uses the temperature positively correlated voltage and the temperature positively correlated current to generate a high-order temperature compensated voltage reference.

3. A CMOS low voltage high order temperature compensated voltage reference source as claimed in claim 2, characterized in that: The output voltage V1 generated by the temperature positive correlation circuit is connected to the positive input terminal of the operational amplifier with a startup circuit and a bias circuit; the output voltage V2 generated by the temperature positive correlation circuit is connected to the negative input terminal of the operational amplifier with a startup circuit and a bias circuit; the input voltage V3 generated by the temperature positive correlation circuit is connected to the output terminal of the operational amplifier with a startup circuit and a bias circuit; the output voltage V4 generated by the temperature positive correlation circuit is connected to an input terminal of the active load circuit; the other input terminal of the active load circuit is connected to the output terminal of the operational amplifier with a startup circuit and a bias circuit; the output terminal of the active load circuit is connected to REF; the output terminal of the voltage reference startup circuit is connected to the input voltage V3 of the temperature positive correlation circuit.

4. A CMOS low voltage high order temperature compensated voltage reference source as claimed in claim 3, characterized in that: The voltage reference startup circuit includes a PMOS transistor PM1, a PMOS transistor PM2, and an NMOS transistor NM1; the source of the PMOS transistor PM1 is electrically connected to VDD; the gate of the PMOS transistor PM1 is electrically connected to GND; the source of the NMOS transistor NM1 and the drain of the NMOS transistor NM1 are electrically connected to GND; the gate of the NMOS transistor NM1, the gate of the PMOS transistor PM2, and the drain of the PMOS transistor PM1 are electrically connected to each other; the drain of the PMOS transistor PM2 is electrically connected to GND; the source of the PMOS transistor PM2 is connected to the input voltage V3 of the temperature positive correlation circuit.

5. A CMOS low voltage high order temperature compensated voltage reference source as claimed in claim 4, characterized in that: The temperature positive correlation circuit includes a PMOS transistor PM3, a PMOS transistor PM4, an NMOS transistor NM2, an NMOS transistor NM3, a resistor R1, and a resistor R2; the source of the PMOS transistor PM3 and the source of the PMOS transistor PM4 are electrically connected to VDD; one end of the resistor R1 is electrically connected to the source of the NMOS transistor NM2; the other end of the resistor R1 is electrically connected to GND; one end of the resistor R2 is electrically connected to the source of the NMOS transistor NM3; the other end of the resistor R2 is electrically connected to GND; the The gate, the drain of the NMOS transistor NM2, and the drain of the PMOS transistor PM3 are electrically connected to each other; the gate of the NMOS transistor NM3, the drain of the NMOS transistor NM3, and the drain of the PMOS transistor PM4 are electrically connected to each other; the gate of the PMOS transistor PM3 and the gate of the PMOS transistor PM4 are electrically connected together; the output voltage V1 is connected to the drain of the NMOS transistor NM3; the output voltage V2 is connected to the drain of the NMOS transistor NM2; the input voltage V3 is connected to the gate of the PMOS transistor PM3; and the output voltage V4 is connected to one end of the resistor R1.

6. A CMOS low voltage high order temperature compensated voltage reference source as claimed in claim 5, characterized in that: The operational amplifier with a startup circuit and a bias circuit comprises: a differential operational amplifier, a startup circuit of the operational amplifier, and a bias circuit of the operational amplifier; The operational amplifier startup circuit is used to start the operational amplifier bias circuit and the differential operational amplifier; the operational amplifier bias circuit is used to provide bias for the differential operational amplifier; the differential operational amplifier makes the voltage V1 and the voltage V2 equal through negative feedback, so that the temperature positive correlation circuit works normally.

7. A CMOS low voltage high order temperature compensated voltage reference source as claimed in claim 6, characterized in that: The bias circuit of the operational amplifier includes a PMOS transistor PM12, a PMOS transistor PM13, an NMOS transistor NM8, an NMOS transistor NM9, and an NMOS transistor NM10; the source of the PMOS transistor PM12 and the source of the PMOS transistor PM13 are electrically connected to VDD; the source of the NMOS transistor NM8 and the source of the NMOS transistor NM10 are electrically connected to GND; the drain of the PMOS transistor PM12, the drain of the NMOS transistor NM8, the gate of the NMOS transistor NM8, and the gate of the NMOS transistor NM9 are electrically connected to each other; the source of the NMOS transistor NM9 is electrically connected to the drain of the NMOS transistor NM10; the gate of the PMOS transistor PM12, the gate of the PMOS transistor PM13, the drain of the PMOS transistor PM13, and the drain of the NMOS transistor NM9 are electrically connected to each other.

8. A CMOS low voltage high order temperature compensated voltage reference source as claimed in claim 7, characterized in that: The differential operational amplifier includes a PMOS transistor PM5, a PMOS transistor PM6, a PMOS transistor PM7, a PMOS transistor PM8, a PMOS transistor PM9, an NMOS transistor NM4, an NMOS transistor NM5, an NMOS transistor NM6, and an NMOS transistor NM7; the source of the NMOS transistor NM4, the source of the NMOS transistor NM5, the source of the NMOS transistor NM6, and the source of the NMOS transistor NM7 are electrically connected to GND; the source of the PMOS transistor PM5, the source of the PMOS transistor PM6, and the source of the PMOS transistor PM9 are electrically connected to VDD; the gate of the PMOS transistor PM5, the gate of the PMOS transistor PM5, the gate of the PMOS transistor PM6, and the gate of the PMOS transistor PM7 are electrically connected to GND; the gate of the PMOS transistor PM5, the gate of the PMOS transistor PM6, and the gate of the PMOS transistor PM7 are electrically connected to VDD; the gate of the PMOS transistor PM5, the gate of the PMOS transistor PM6, and the gate of the PMOS transistor PM7 are electrically connected to GND; the gate of the PMOS transistor PM5, the gate of the PMOS transistor PM6, and the gate of the PMOS transistor PM7 are electrically connected to GND; the gate of the PMOS transistor PM5, the gate of the PMOS transistor PM6, and the gate of the PMOS transistor PM7 are electrically connected to GND; the gate of the PMOS transistor PM5, the gate of the PMOS transistor PM7 ... The drain, the drain of NMOS transistor NM4, and the gate of PMOS transistor PM9 are electrically connected to each other; the gate of NMOS transistor NM4, the gate of NMOS transistor NM5, the drain of NMOS transistor NM5, and the drain of PMOS transistor PM7 are electrically connected to each other; the gate of NMOS transistor NM6, the gate of NMOS transistor NM7, the drain of NMOS transistor NM6, and the drain of PMOS transistor PM8 are electrically connected to each other; the drain of PMOS transistor PM6, the source of PMOS transistor PM7, and the source of PMOS transistor PM8 are electrically connected to each other; the gate of PMOS transistor PM6 is electrically connected to the gate of PMOS transistor PM13.

9. A CMOS low voltage high order temperature compensated voltage reference source as claimed in claim 8, characterized in that: The startup circuit of the operational amplifier includes a PMOS transistor PM15, a PMOS transistor PM14, and an NMOS transistor NM11; the source of the PMOS transistor PM15 is electrically connected to VDD; the gate of the PMOS transistor PM15 is electrically connected to GND; the source of the NMOS transistor NM11 and the drain of the NMOS transistor NM11 are electrically connected to GND; the gate of the NMOS transistor NM11, the gate of the PMOS transistor PM14, and the drain of the PMOS transistor PM15 are electrically connected to each other; the drain of the PMOS transistor PM14 is electrically connected to GND; the source of the PMOS transistor PM14, the gate of the PMOS transistor PM12, and the gate of the PMOS transistor PM13 are electrically connected to each other.

10. A CMOS low voltage high order temperature compensated voltage reference source as claimed in claim 9, characterized in that: The active load circuit includes a PMOS transistor PM10 and a PMOS transistor PM11; the source of the PMOS transistor PM10 is electrically connected to VDD; the drain of the PMOS transistor PM11 is electrically connected to GND; the drain of the PMOS transistor PM10 and the source of the PMOS transistor PM11 are electrically connected to REF; REF is the output end of the voltage reference source.

11. A CMOS low voltage high order temperature compensated voltage reference source as claimed in claim 10, characterized in that: When the voltage reference source operates normally, the NMOS transistor NM2 and the NMOS transistor NM3 are in the subthreshold region, the voltage across the resistor R1 is a voltage that is positively correlated with the temperature, the source-drain currents of the PMOS transistors PM3 and PM4 are currents that are positively correlated with the temperature; the source-drain current of the PMOS transistor PM10 proportionally replicates the source-drain current of the PMOS transistor PM3, and the source-drain current of the PMOS transistor PM10 is a current that is positively correlated with the temperature; the overdrive voltage of the PMOS transistor PM11 is determined by the source-drain current of the PMOS transistor PM10; the voltage across the resistor R1 is a voltage that is positively correlated with the temperature, and the source-drain current of the PMOS transistor ...4 is a current that is positively correlated with the temperature. The threshold voltage of the body transistor PM11 is negatively correlated with the temperature, and the two are added to form a voltage reference; the over-drive voltage of the PMOS transistor PM11 performs high-order compensation on the voltage reference; the gate-source voltage of the PMOS transistor PM11 is equal to the sum of the threshold voltage of the PMOS transistor PM11 and the over-drive voltage of the PMOS transistor PM11; the REF voltage is equal to the sum of the gate-source voltage of the PMOS transistor PM11 and the voltage across the resistor R1; the REF voltage is a high-order temperature-compensated voltage reference formed by the sum of the voltage across the resistor R1, the threshold voltage of the PMOS transistor PM11, and the over-drive voltage of the PMOS transistor PM11.

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