Data link processing method and device, equipment, medium and product

Abstract

The invention provides a data link processing method and device, equipment, a medium and a product. The method comprises the following steps: acquiring a plurality of measurement data of a quantum measurement and control instrument; in response to the data writing instruction, determining the data flow direction of each piece of measurement data according to a preset data storage strategy; based on each data flow direction, selecting a target first-in first-out (FIFO) memory used for storing each piece of measurement data from a plurality of FIFO memories and writing the target FIFO memories into the FIFO memories; in response to a data reading instruction, reading corresponding measurement data from each target FIFO memory; performing data construction on each piece of measurement data to obtain a plurality of pieces of target data; and issuing the multiple pieces of target data to the external equipment. According to the data link processing method provided by the invention, a plurality of FIFO memories are used for caching large-batch measurement data, real-time data storage and reading operations are realized, response duration and delay time are reduced, data construction and data issuing processes are further carried out in time, and the data processing speed is effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of data processing technology, and in particular to a data link processing method, device, equipment, medium and product. Background Art

[0002] The data link processing method of traditional quantum measurement and control instruments forms a complete link from top to bottom through the four processes of data acquisition, data standardization, data construction and data transmission. In the data link processing process of traditional quantum measurement and control instruments, a single FIFO (First-In-First-Out) memory is used or no FIFO memory is used to pre-store small batches of data, which has little effect on time delay.

[0003] With the ever-increasing amount of big data, the data link processing method of traditional quantum measurement and control instruments can no longer support large-scale data processing, and there are problems such as slow data processing speed and long response time. Summary of the invention

[0004] The present invention provides a data link processing method, device, equipment, medium and product, which are used to solve the problems of slow data processing speed, long response time and the like existing in the prior art.

[0005] In a first aspect, the present invention provides a data link processing method, comprising: Acquire multiple measurement data of the quantum measurement and control instrument; In response to the data writing instruction, determining the data flow direction of each measurement data according to a preset data storage strategy; Based on the data flow direction of each measurement data, a target FIFO memory for storing each measurement data is selected from a plurality of first-in-first-out FIFO memories, and each measurement data is written into the corresponding target FIFO memory; In response to the data read instruction, reading corresponding measurement data from each target FIFO memory; Perform data construction on each measurement data to obtain multiple target data; The multiple target data are sent to an external device.

[0006] In one embodiment, the multiple FIFO memories include at least a first FIFO memory and a second FIFO memory; when determining the data flow direction of each measurement data according to a preset data storage strategy, the following steps are performed for each measurement data: If the first FIFO memory issues a write request signal, determining that the measurement data flows to the first FIFO memory; If the first FIFO memory sends a full signal and the second FIFO memory sends a write request signal, determining that the measurement data flows to the second FIFO memory; If the first FIFO memory sends a full signal and the second FIFO memory sends a full signal, it is determined that the measurement data does not flow to the first FIFO memory and the second FIFO memory temporarily.

[0007] In one embodiment, reading corresponding measurement data from each target FIFO memory includes: Firstly, reading corresponding measurement data from a target FIFO memory belonging to the first FIFO memory; Then, the corresponding measurement data is read from the target FIFO memory belonging to the second FIFO memory.

[0008] In one embodiment, when data construction is performed on each measurement data to obtain multiple target data, the following steps are performed for each measurement data: The measurement data is split according to a preset number of bits as a period to obtain a plurality of split data; Perform data pipeline processing on each split data to obtain multiple processed data; The target data is obtained by integrating the plurality of processed data.

[0009] In one embodiment, the step of integrating the plurality of processed data to obtain target data includes: According to the position of each processed data in the original measurement data, the plurality of processed data are spliced ​​and integrated to obtain integrated data; The integrated data is spliced ​​again at the end of the integrated data to obtain the target data.

[0010] In one embodiment, when sending the plurality of target data to the external device, the following steps are performed for each target data: In response to a write request signal sent by the third FIFO memory, writing the target data into the third FIFO memory; In response to a data read instruction, reading the target data from the third FIFO memory; Performing standardization processing on the target data to obtain standard data; The standard data is divided into multiple signals and transmitted to external equipment.

[0011] In a second aspect, the present invention further provides a data link processing device, comprising: An acquisition module, used to acquire multiple measurement data of the quantum measurement and control instrument; A determination module, configured to determine, in response to a data write instruction, a data flow direction of each measurement data according to a preset data storage strategy; A data writing module, used for selecting a target FIFO memory for storing each measurement data from a plurality of first-in-first-out FIFO memories based on a data flow direction of each measurement data, and writing each measurement data into a corresponding target FIFO memory; A data reading module, configured to read corresponding measurement data from each target FIFO memory in response to a data reading instruction; A data construction module is used to construct data for each measurement data to obtain multiple target data; The data sending module is used to send the multiple target data to the external device.

[0012] In a third aspect, the present invention provides a device, comprising an electronic device, wherein the electronic device comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the steps of any of the data link processing methods described above are implemented.

[0013] In a fourth aspect, the present invention further provides a medium, comprising a non-transitory computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the steps of any of the data link processing methods described above are implemented.

[0014] In a fifth aspect, the present invention also provides a product, comprising a computer program product, wherein the computer program product comprises a computer program, wherein the computer program can be stored on a non-transitory computer-readable storage medium, and wherein when the computer program is executed by the processor, the steps of any of the data link processing methods described above are implemented.

[0015] The data link processing method, device, equipment, medium and product provided by the present invention can use multiple FIFO memories to cache large quantities of measurement data after the large quantities of measurement data of the quantum measurement and control instrument arrive, and can write each measurement data into the corresponding target FIFO memory in a direction according to the preset data storage strategy, thereby eliminating the need to wait for the completion of other data processing, realizing real-time data storage and reading operations, reducing the response time and delay time, and once the corresponding measurement data is read from the target FIFO memory, the data construction and data sending process can be carried out in time, realizing a complete link from top to bottom, effectively improving the data processing speed, and thus improving the efficiency of data link processing as a whole. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 It is one of the flow charts of the data link processing method provided by the present invention.

[0018] Figure 2 This is the second flow chart of the data link processing method provided by the present invention.

[0019] Figure 3 It is a schematic diagram of the internal structure of the data receiving module provided by the present invention.

[0020] Figure 4 It is a schematic diagram of the internal structure of the data construction module provided by the present invention.

[0021] Figure 5 It is a schematic diagram of the internal structure of the data sending module provided by the present invention.

[0022] Figure 6 It is a structural schematic diagram of the data link processing device provided by the present invention.

[0023] Figure 7 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] The terms "first", "second", etc. in the present invention are used to distinguish similar objects, rather than to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described herein.

[0026] Combine the following Figure 1-Figure 7 The data link processing method, device, equipment, medium and product provided by the present invention are described.

[0027] Combination Figure 1 and Figure 2 , Figure 1 is one of the flow charts of the data link processing method provided by the present invention, Figure 2 This is the second flow chart of the data link processing method provided by the present invention.

[0028] like Figure 1 As shown, the method includes the following: Step 101, obtaining a plurality of measurement data of a quantum measurement and control instrument; Step 102: In response to the data writing instruction, determine the data flow direction of each measurement data according to a preset data storage strategy; Step 103: based on the data flow direction of each measurement data, select a target FIFO memory for storing each measurement data from a plurality of first-in-first-out FIFO memories, and write each measurement data into the corresponding target FIFO memory; Step 104, in response to the data read instruction, reading corresponding measurement data from each target FIFO memory; Step 105: construct data for each measurement data to obtain multiple target data; Step 106: Send the multiple target data to an external device.

[0029] It should be noted that the data link processing method provided in the embodiment of the present invention is implemented based on a parallel processor in a data link processing device, such as a field programmable gate array (FPGA). In order to solve the problems of slow processing speed, long response time and weak concurrency in the prior art for large-scale data processing, the embodiment of the present invention provides an efficient and simple data link processing method for a quantum measurement and control instrument, which can simplify the data link processing process based on the above three outstanding problems, including data reception, data construction and data sending, which are respectively implemented by a data receiving module, a data construction module and a data sending module, which can be referred to Figure 2 Data reception is used for data preprocessing, data construction is used to reconstruct data, and data delivery is used for data standardization. Data reception and data delivery are used to solve the problem of long response time, and data construction solves the problems of slow processing speed and weak concurrency capability.

[0030] The embodiment of the present invention describes the data link processing method by taking a parallel processor as an execution subject as an example.

[0031] Combination Figure 3 , Figure 3 This is the internal structure of the data receiving module provided by the present invention. Figure 3As shown, the data receiving module is internally composed of an arbitrator and multiple FIFO memories. The embodiment of the present invention takes two FIFO memories as an example for illustration, but is not actually limited to two FIFO memories. In order to distinguish, the two FIFO memories are divided into a first FIFO memory and a second FIFO memory, the first FIFO memory is recorded as FIFO1, and the second FIFO memory is recorded as FIFO2. Among them, the arbitrator is used to determine the flow direction of the external data data0, whether it flows to the first FIFO memory through the data data1, or flows to the second FIFO memory through the data data2, and realizes the alternating cache of data through the first FIFO memory and the second FIFO memory, and completes the cross-clock domain conversion of data from the low clock domain to the high clock domain.

[0032] It should be noted that the arbitrator is usually used to coordinate the access requests of multiple devices or processing units to shared resources to ensure the efficient operation of the system and the effective use of resources. Its main function is to decide which device or processing unit obtains the right to use resources at a specific time based on a specific decision algorithm. FIFO memory is a special type of memory that follows the first-in-first-out data access principle. In simple terms, data is stored in the order of arrival and is read out in the same order, similar to a queuing mechanism. This type of memory is usually used in situations where data needs to be processed strictly in time order. During the data link processing process, FIFO memory can effectively buffer data, making the flow of data more orderly and controllable, and avoiding data confusion or loss.

[0033] Specifically, when there is still cache space inside multiple FIFO memories, the multiple FIFO memories will issue a request to write data to the arbitrator to inform the arbitrator that data can be stored currently. The parallel processor generates corresponding data write instructions based on the request to write data issued by the multiple FIFO memories to the arbitrator.

[0034] Furthermore, when multiple measurement data of the quantum measurement and control instrument are ready, the parallel processor responds to the data write instruction and determines the data flow direction of each measurement data according to a preset data storage strategy.

[0035] Among them, the preset data storage strategy is a cyclic mechanism with three current states inside the arbitrator, which determines the data flow direction according to the write request signal (locked state) and the write-full signal (unlocked state) of the FIFO memory. The three current states are: writing data to the first FIFO memory, writing data to the second FIFO memory, and not writing data to the first FIFO memory and the second FIFO memory. According to the principle of "writing to the first FIFO memory first and then writing to the second FIFO memory", when the state is "writing data to the first FIFO memory", the first FIFO memory is filled first and then the data is written to the second FIFO memory; when the state is "writing data to the second FIFO memory", the second FIFO memory is filled first and then the data is written to the first FIFO memory; when the state is "not writing data to the first FIFO memory and the second FIFO memory", wait for subsequent data, and then choose which FIFO memory to write data according to the principle of "writing to the first FIFO memory first and then writing to the second FIFO memory".

[0036] Furthermore, the parallel processor selects a target FIFO memory for storing each measurement data from multiple FIFO memories based on the data flow direction of each measurement data. That is, the target FIFO memory is either the first FIFO memory or the second FIFO memory. Therefore, multiple stock data can be stored according to the principle of "writing to the first FIFO memory first and then writing to the second FIFO memory" to achieve alternating data storage in the two FIFO memories.

[0037] Further, the parallel processor writes each measurement data into a corresponding target FIFO memory.

[0038] Furthermore, after a plurality of measurement data are stored in corresponding target FIFO memories, these target FIFO memories will send a readable signal to the next-level data construction module.

[0039] Combination Figure 4 , Figure 4 It is the internal structure of the data construction module provided by the present invention. Figure 4 As shown, the data construction module includes a controller. The controller is used to generate a data read instruction to read the data data3 of the previous level data receiving module. The data data3 can be considered as reading the corresponding measurement data in the target FIFO memory through the shared signal channel. The arbitrator can select when the first FIFO memory occupies data3 and when the second FIFO memory occupies data3.

[0040] Furthermore, the controller generates a data read instruction, and the parallel processor responds to the data read instruction by reading corresponding measurement data from each target FIFO memory through a common signal channel and transmitting the data to the data construction module for data construction.

[0041] It should be noted that the FIFO memory can realize the cross-clock domain conversion of data from the low clock domain to the high clock domain because the speed of writing to the FIFO memory (i.e., low clock) is different from the speed of reading from the FIFO memory (i.e., high clock). By writing data through the low clock data and then reading data through the high clock, a simple cross-clock domain processing is completed. When the next level completes the data reading and uses the high-frequency clock, the FIFO memory can be used to achieve decoupling from the previous level clock domain, thereby avoiding the problem of clock signal synchronization and ensuring the correctness and stability of the data.

[0042] Furthermore, the parallel processor performs data construction on each measurement data through the data construction module to obtain target data corresponding to each measurement data after the data construction.

[0043] Furthermore, the parallel processor sends the multiple target data to the external device through the data sending module.

[0044] The data link processing method provided by the present invention can use multiple FIFO memories to cache large quantities of measurement data after the large quantities of measurement data of the quantum measurement and control instrument arrive, and can write each measurement data in a direction to the corresponding target FIFO memory according to the preset data storage strategy, thereby eliminating the need to wait for the completion of other data processing, realizing real-time data storage and reading operations, reducing the response time and delay time, and once the corresponding measurement data is read from the target FIFO memory, the data construction and data sending process can be carried out in time, realizing a complete link from top to bottom, effectively improving the data processing speed, and thus improving the efficiency of data link processing as a whole.

[0045] Further, based on step 102, when the data flow direction of each measurement data is determined according to the preset data storage strategy, the following steps are performed for each measurement data: If the first FIFO memory issues a write request signal, determining that the measurement data flows to the first FIFO memory; If the first FIFO memory sends a full signal and the second FIFO memory sends a write request signal, determining that the measurement data flows to the second FIFO memory; If the first FIFO memory sends a full signal and the second FIFO memory sends a full signal, it is determined that the measurement data does not flow to the first FIFO memory and the second FIFO memory temporarily.

[0046] Specifically, the parallel processor determines whether there is still cache space inside the first FIFO memory and the second FIFO memory through the arbitrator.

[0047] Further, if the first FIFO memory sends a write request signal, the arbiter determines that the measurement data flows to the first FIFO memory and informs the parallel processor. Further, the parallel processor determines that the measurement data flows to the first FIFO memory to write the measurement data into the first FIFO memory.

[0048] Furthermore, if the first FIFO memory sends a full signal and the second FIFO memory sends a write request signal, the arbitrator determines that the measurement data flows to the second FIFO memory and informs the parallel processor. Further, the parallel processor determines that the measurement data flows to the second FIFO memory to write the measurement data into the second FIFO memory.

[0049] Further, if the first FIFO memory sends a full signal and the second FIFO memory sends a full signal, the arbitrator determines that the measurement data does not flow to the first FIFO memory and the second FIFO memory temporarily. Further, the parallel processor determines that the measurement data does not flow to the first FIFO memory and the second FIFO memory temporarily to determine whether subsequent data needs to flow to the first FIFO memory or the second FIFO memory.

[0050] In one embodiment, the state "writing data into the first FIFO memory" is numbered as 1, the state "writing data into the second FIFO memory" is numbered as 2, and the state "not writing data into the first FIFO memory and the second FIFO memory" is numbered as 3. The first FIFO memory is recorded as FIFO1, and the second FIFO memory is recorded as FIFO2. The cyclic mechanism consisting of the three states is expressed as follows: .

[0051] The embodiment of the present invention stores measurement data alternately through two FIFO registers, thereby avoiding empty cycles, improving real-time response time, supporting large-volume data storage, and providing high sustainability for data reception, thereby improving operating efficiency and response speed.

[0052] Further, based on step 104, the reading corresponding measurement data from each target FIFO memory includes: Firstly, reading corresponding measurement data from a target FIFO memory belonging to the first FIFO memory; Then, the corresponding measurement data is read from the target FIFO memory belonging to the second FIFO memory.

[0053] Specifically, according to the principle of "reading the first FIFO memory first and then reading the second FIFO memory", the parallel processor first reads the corresponding measurement data from the target FIFO memory belonging to the first FIFO memory, and then reads the corresponding measurement data from the target FIFO memory belonging to the second FIFO memory.

[0054] It can be understood that the parallel processor reads out multiple measurement data stored in the first FIFO memory in sequence according to the first-in-first-out principle of the FIFO memory. Further, the parallel processor reads out multiple measurement data stored in the second FIFO memory in sequence according to the first-in-first-out principle of the FIFO memory.

[0055] The embodiment of the present invention reads the measurement data sequentially according to the principle of "reading the first FIFO memory first and then reading the second FIFO memory", which can ensure that the data is read and processed in the correct order and timing, and avoid data loss or confusion.

[0056] Further, based on step 105, when data construction is performed on each measurement data to obtain multiple target data, the following steps are performed for each measurement data: The measurement data is split according to a preset number of bits as a period to obtain a plurality of split data; Perform data pipeline processing on each split data to obtain multiple processed data; The target data is obtained by integrating the plurality of processed data.

[0057] like Figure 4 As shown, the data construction module also includes an extraction and distribution submodule, a data processing submodule and a splicing and integration submodule. The extraction and distribution submodule is used to split the pre-processing data data3 and form multi-channel distribution data data4, for example, split into four-channel distribution data, including data_1, data_2, data_3 and data_4. The data processing submodule is used to perform data pipeline processing on the multi-channel distribution data data4 respectively to obtain multi-channel processed data data5. The splicing and integration submodule is used to splice the processed multi-channel data data5 and form the spliced ​​and integrated new data data6 to transmit to the next level module, which can realize data reorganization and accelerate the processing process.

[0058] Specifically, the parallel processor splits the measurement data according to a preset bit number as a period to obtain a plurality of split data, which can be considered as splitting one channel of measurement data into a plurality of split data for transmission, wherein the preset bit number is set according to actual conditions.

[0059] In one embodiment, the extraction is divided into 4-bit periods, such as the 1st bit, the 5th bit, the 9th bit... constitute data data_1, the 2nd bit, the 6th bit, the 10th bit... constitute data data_2, the 3rd bit, the 7th bit, the 11th bit... constitute data data_3, the 4th bit, the 8th bit, the 12th bit... constitute data data_4. The extraction process data is transmitted to the corresponding next level of data processing in real time.

[0060] Furthermore, the parallel processor performs data pipeline processing on each split data to obtain multiple processed data.

[0061] It should be noted that each data pipeline process will delay the data by one beat and temporarily store it in a register, and then delay it by one beat and temporarily store it in a register. The two beats of data storage can be used to calculate the data without affecting the continuous input of data 4. The above is essentially a process of realizing pipeline operation. The program processing method is to delay the arrival time of the data and temporarily store the delayed data. The parallel processor can complete the calculation of the delayed data and update the data at the same time. Through this data pipeline processing method, the pipeline processing speed of the data can be further improved, and the simultaneous pipeline processing of multiple distribution channels also improves the data concurrency capability.

[0062] Furthermore, the parallel processor integrates the plurality of processed data to obtain target data.

[0063] The embodiment of the present invention splits the measurement data and forms multi-channel distribution data, so as to realize the simultaneous processing of single-channel data distribution into multiple channels of data, effectively improve the data concurrency capability, and can greatly improve the speed of processing data in a high clock domain. Furthermore, based on the integration of multiple channels of data, complete data can be obtained again, thereby ensuring the integrity of data while improving the data processing speed.

[0064] Furthermore, the integrating the plurality of processed data to obtain target data comprises: According to the position of each processed data in the original measurement data, the plurality of processed data are spliced ​​and integrated to obtain integrated data; The integrated data is spliced ​​again at the end of the integrated data to obtain the target data.

[0065] like Figure 4As shown, the 4 data data5_1, data5_2, data5_3, and data5_4 that have completed the data pipeline processing enter the splicing and integration in real time. The splicing process is carried out in the corresponding positions in the order of splitting. The difference is that each data will be spliced ​​again into the same data after splicing, that is, the bit width of data data6 is twice that of data data3, further improving the transmission bandwidth.

[0066] Specifically, the parallel processor splices and integrates the multiple processed data at corresponding positions according to the positions of each processed data in the original measurement data. It can also be understood as splicing and integrating the multiple processed data at corresponding positions in the split order to obtain integrated data.

[0067] Furthermore, the parallel processor splices the integrated data again at the end of the integrated data to obtain the target data. At this time, the bit width of the target data is twice the bit width of the corresponding original measurement data, which can further improve the transmission bandwidth.

[0068] The embodiment of the present invention splices and integrates multiple data at corresponding positions in the original split order, and can obtain complete data again, thereby ensuring data integrity while improving data processing speed. The same data is further spliced ​​at the end of the integrated data to increase transmission bandwidth, which can significantly improve data transmission speed, thereby efficiently completing data link processing.

[0069] Further, based on step 106, when the plurality of target data are sent to the external device, the following steps are performed for each target data: In response to a write request signal sent by the third FIFO memory, writing the target data into the third FIFO memory; In response to a data read instruction, reading the target data from the third FIFO memory; Performing standardization processing on the target data to obtain standard data; The standard data is divided into multiple signals and transmitted to external equipment.

[0070] Combination Figure 5 , Figure 5 Schematic diagram of the internal structure of the data sending module provided by the present invention. Figure 5 As shown, the data sending module is composed of a third FIFO register and a standardization submodule, wherein the third FIFO register is FIFO3. The third FIFO register is used to cache the previous level data data6. The standardization submodule is used to read data data7 from the third FIFO register, standardize data7, and output a standard data format data8 for easy recognition by the next level.

[0071] Specifically, when there is cache space inside the third FIFO memory, a write request signal is sent to the data construction module. Further, the parallel processor generates a corresponding data write instruction according to the write request signal sent by the third FIFO memory.

[0072] Further, the parallel processor writes the target data into the third FIFO memory in response to the data write instruction.

[0073] Furthermore, the standardization submodule sends out a read signal, and the parallel processor generates a corresponding data read instruction according to the read signal sent out by the standardization submodule.

[0074] Further, the parallel processor reads the target data from the third FIFO memory in response to the data read instruction.

[0075] Furthermore, the parallel processor performs standardization processing on the target data through the standardization submodule to obtain standard data, wherein the standardization processing process includes but is not limited to processing methods such as bit width, timing and difference with unified standards.

[0076] Furthermore, the parallel processor divides the standard data into multiple signals through the standardization submodule and transmits them to the external device, and can be divided into 4 channels to transmit signals to the external device or external chip.

[0077] The embodiment of the present invention again uses the FIFO memory to temporarily store data to construct the completed target data, thereby realizing multi-level register temporary data storage, ensuring uninterrupted data processing, and having strong data pipeline operability. The target data is further standardized to ensure data consistency and accuracy, which is convenient for the next level of identification, and the standard data is divided into multiple signals for transmission to an external device or an external chip. The overall transmission efficiency and speed can be significantly improved when large amounts of data need to be transmitted simultaneously, thereby improving the efficiency of data link processing as a whole.

[0078] The data link processing device provided by the present invention is described below. The data link processing device described below and the data link processing method described above can be referred to each other.

[0079] Reference Figure 6 , Figure 6 It is a structural schematic diagram of the data link processing device provided by the present invention.

[0080] The data link processing device comprises: The acquisition module 610 is used to acquire multiple measurement data of the quantum measurement and control instrument.

[0081] The determination module 620 is used to determine the data flow direction of each measurement data in response to the data writing instruction and according to a preset data storage strategy.

[0082] The data writing module 630 is used to select a target FIFO memory for storing each measurement data from a plurality of first-in-first-out FIFO memories based on the data flow direction of each measurement data, and write each measurement data into the corresponding target FIFO memory.

[0083] The data reading module 640 is used to read corresponding measurement data from each target FIFO memory in response to a data reading instruction.

[0084] The data construction module 650 is used to perform data construction on each measurement data to obtain multiple target data.

[0085] The data sending module 660 is used to send the multiple target data to the external device.

[0086] The data link processing device provided by the present invention can use multiple FIFO memories to cache large quantities of measurement data after the large quantities of measurement data of the quantum measurement and control instrument arrive, and can write each measurement data into the corresponding target FIFO memory in a direction according to the preset data storage strategy, thereby eliminating the need to wait for the completion of other data processing, realizing instant data storage and reading operations, reducing the response time and delay time, and once the corresponding measurement data is read from the target FIFO memory, the data construction and data sending processes can be carried out in time, realizing a complete link from top to bottom, effectively improving the data processing speed, and thus improving the overall efficiency of data link processing.

[0087] Furthermore, the determining module 620 is further configured to: If the first FIFO memory issues a write request signal, determining that the measurement data flows to the first FIFO memory; If the first FIFO memory sends a full signal and the second FIFO memory sends a write request signal, determining that the measurement data flows to the second FIFO memory; If the first FIFO memory sends a full signal and the second FIFO memory sends a full signal, it is determined that the measurement data does not flow to the first FIFO memory and the second FIFO memory temporarily.

[0088] Furthermore, the data reading module 640 is also used for: Firstly, reading corresponding measurement data from a target FIFO memory belonging to the first FIFO memory; Then, the corresponding measurement data is read from the target FIFO memory belonging to the second FIFO memory.

[0089] Furthermore, the data construction module 650 is also used for: The measurement data is split according to a preset number of bits as a period to obtain a plurality of split data; Perform data pipeline processing on each split data to obtain multiple processed data; The target data is obtained by integrating the plurality of processed data.

[0090] Furthermore, the data construction module 650 is also used for: According to the position of each processed data in the original measurement data, the plurality of processed data are spliced ​​and integrated to obtain integrated data; The integrated data is spliced ​​again at the end of the integrated data to obtain the target data.

[0091] Furthermore, the data sending module 660 is also used for: In response to a write request signal sent by the third FIFO memory, writing the target data into the third FIFO memory; In response to a data read instruction, reading the target data from the third FIFO memory; Performing standardization processing on the target data to obtain standard data; The standard data is divided into multiple signals and transmitted to external equipment.

[0092] Figure 7 is a schematic diagram of the structure of the electronic device provided by the present invention, such as Figure 7 As shown, the electronic device may include: a processor 710, a communication interface 720, a memory 730 and a communication bus 740, wherein the processor 710, the communication interface 720 and the memory 730 communicate with each other through the communication bus 740. The processor 710 may call the logic instructions in the memory 730 to execute the data link processing method, which includes: obtaining multiple measurement data of the quantum measurement and control instrument; in response to the data write instruction, determining the data flow direction of each measurement data according to the preset data storage strategy; based on the data flow direction of each measurement data, selecting a target FIFO memory for storing each measurement data from multiple first-in-first-out FIFO memories, and writing each measurement data into the corresponding target FIFO memory; in response to the data read instruction, reading the corresponding measurement data from each target FIFO memory; constructing data for each measurement data to obtain multiple target data; and sending the multiple target data to the external device.

[0093] In addition, the logic instructions in the above-mentioned memory 730 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on this understanding, the technical solution of the present invention can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0094] On the other hand, the present invention also provides a computer program product, which includes a computer program stored on a non-transitory computer-readable storage medium, and the computer program includes program instructions. When the program instructions are executed by a computer, the computer can execute the data link processing method provided by the above embodiments, the method including: obtaining multiple measurement data of a quantum measurement and control instrument; in response to a data write instruction, determining the data flow direction of each measurement data according to a preset data storage strategy; based on the data flow direction of each measurement data, selecting a target FIFO memory for storing each measurement data from multiple first-in-first-out FIFO memories, and writing each measurement data into the corresponding target FIFO memory; in response to a data read instruction, reading the corresponding measurement data from each target FIFO memory; performing data construction on each measurement data to obtain multiple target data; and sending the multiple target data to an external device.

[0095] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to execute the data link processing method provided in the above-mentioned embodiments, the method comprising: obtaining multiple measurement data of a quantum measurement and control instrument; in response to a data write instruction, determining the data flow direction of each measurement data according to a preset data storage strategy; based on the data flow direction of each measurement data, selecting a target FIFO memory for storing each measurement data from multiple first-in-first-out FIFO memories, and writing each measurement data into a corresponding target FIFO memory; in response to a data read instruction, reading the corresponding measurement data from each target FIFO memory; performing data construction on each measurement data to obtain multiple target data; and sending the multiple target data to an external device.

[0096] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment. Those of ordinary skill in the art may understand and implement the present invention without creative effort.

[0097] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0098] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data link processing method, characterized in that: Applications to parallel processors include: Acquire multiple measurement data of the quantum measurement and control instrument; In response to the data writing instruction, determining the data flow direction of each measurement data according to a preset data storage strategy; Based on the data flow direction of each measurement data, a target FIFO memory for storing each measurement data is selected from a plurality of first-in-first-out FIFO memories, and each measurement data is written into the corresponding target FIFO memory; In response to the data read instruction, reading corresponding measurement data from each target FIFO memory; Perform data construction on each measurement data to obtain multiple target data; The multiple target data are sent to an external device.

2. The data link processing method according to claim 1, characterized in that: The multiple FIFO memories include at least a first FIFO memory and a second FIFO memory; when determining the data flow direction of each measurement data according to a preset data storage strategy, performing the following steps for each measurement data: If the first FIFO memory issues a write request signal, determining that the measurement data flows to the first FIFO memory; If the first FIFO memory sends a full signal and the second FIFO memory sends a write request signal, determining that the measurement data flows to the second FIFO memory; If the first FIFO memory sends a full signal and the second FIFO memory sends a full signal, it is determined that the measurement data does not flow to the first FIFO memory and the second FIFO memory temporarily.

3. The data link processing method according to claim 2, characterized in that: The reading corresponding measurement data from each target FIFO memory includes: Firstly, reading corresponding measurement data from a target FIFO memory belonging to the first FIFO memory; Then, the corresponding measurement data is read from the target FIFO memory belonging to the second FIFO memory.

4. The data link processing method according to claim 1, characterized in that: When constructing data for each measurement data to obtain multiple target data, perform the following steps for each measurement data: The measurement data is split according to a preset number of bits as a period to obtain a plurality of split data; Perform data pipeline processing on each split data to obtain multiple processed data; The target data is obtained by integrating the plurality of processed data.

5. The data link processing method according to claim 1, characterized in that: The step of integrating the plurality of processed data to obtain target data comprises: According to the position of each processed data in the original measurement data, the plurality of processed data are spliced ​​and integrated to obtain integrated data; The integrated data is spliced ​​again at the end of the integrated data to obtain the target data.

6. The data link processing method according to claim 1, characterized in that: When sending the plurality of target data to the external device, the following steps are performed for each target data: In response to a write request signal sent by the third FIFO memory, writing the target data into the third FIFO memory; In response to a data read instruction, reading the target data from the third FIFO memory; Performing standardization processing on the target data to obtain standard data; The standard data is divided into multiple signals and transmitted to external equipment.

7. A data link processing device, characterized in that: include: An acquisition module, used to acquire multiple measurement data of the quantum measurement and control instrument; A determination module, configured to determine, in response to a data write instruction, a data flow direction of each measurement data according to a preset data storage strategy; A data writing module, used for selecting a target FIFO memory for storing each measurement data from a plurality of first-in-first-out FIFO memories based on a data flow direction of each measurement data, and writing each measurement data into a corresponding target FIFO memory; A data reading module, configured to read corresponding measurement data from each target FIFO memory in response to a data reading instruction; A data construction module is used to construct data for each measurement data to obtain multiple target data; The data sending module is used to send the multiple target data to the external device.

8. A device, comprising an electronic device, the electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the data link processing method according to any one of claims 1 to 6 are implemented.

9. A medium, comprising a non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the data link processing method according to any one of claims 1 to 6 are implemented.

10. A product, comprising a computer program product, wherein the computer program product comprises a computer program, characterized in that When the computer program is executed by a processor, the steps of the data link processing method according to any one of claims 1 to 6 are implemented.

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