Data processing method and device and storage medium

Abstract

The invention provides a data processing method and device and a storage medium, and the method comprises the steps: obtaining a first message sent by a processor, determining a first read pointer corresponding to a port to which the port number belongs, the first read pointer is used for indicating a first descriptor in a processor sending queue corresponding to the interface type, and the first descriptor comprises a first storage address, a first data length and a first use flag bit; and if yes, reading the first data from the data memory based on the first storage address and the first data length. According to the method and the device, lightweight data receiving and transmitting can be realized, efficient data receiving and transmitting communication can be realized, the memory overhead of data receiving and transmitting is relatively small, the realization is simple, the development cost can be effectively reduced, the method and the device can be applied to a low-load processor, and the application universality is relatively high.

Description

Technical Field

[0001] The present disclosure relates to the field of communication technology, and in particular to a data processing method, device and storage medium. Background Art

[0002] In the related art, the data input and output boards used in the base stations of the fifth generation mobile communication technology are usually data plane development kit technology (Data Plane Development Kit, DPDK), which is used to provide complete memory management and data receiving and sending operations.

[0003] In this way, since DPDK is large and not suitable for low-load processors, problems such as severe CPU idling and high system overhead will occur. Some processors do not support the DPDK development kit, resulting in some low-load processors being unable to achieve good data receiving and sending functions. Summary of the invention

[0004] The present disclosure aims to solve one of the technical problems in the related art at least to some extent.

[0005] To this end, the purpose of the present disclosure is to provide a data processing method, device and processor-readable storage medium.

[0006] An embodiment of the first aspect of the present disclosure proposes a data processing method, which is executed by a programmable logic unit, including: obtaining a first message sent by a processor, wherein the first message includes: a port number and an interface type; determining a first read pointer corresponding to a port to which the port number belongs, wherein the first read pointer is used to indicate a first descriptor in a processor send queue corresponding to the interface type, the first descriptor including: a first storage address, a first data length, and a first usage flag; if the first usage flag indicates that the processor has filled data and data is to be read, reading the first data from the data memory based on the first storage address and the first data length.

[0007] Optionally, in some embodiments of the present disclosure, after reading the first data from the data memory based on the first storage address and the first data length, the method further includes: storing the first data locally, and configuring a first usage flag to indicate that the data has been read.

[0008] Optionally, in some embodiments of the present disclosure, the method further includes: configuring the first read pointer to instruct the processor to send the next first descriptor in the queue.

[0009] Optionally, in some embodiments of the present disclosure, the method also includes: determining a first write pointer, wherein the first write pointer is used to indicate a second descriptor in a processor receive queue, the second descriptor including: a second storage address, a first data length to be filled, and a second usage flag; if the second usage flag indicates that the processor has completed reception and data is to be moved, then the second data is moved to a data memory corresponding to the second storage address, wherein the second data has a corresponding second data length; the first data length to be filled is updated to the second data length, and the second usage flag is configured to indicate that the programmable logic unit has moved the data and the data is to be received.

[0010] Optionally, in some embodiments of the present disclosure, the method further includes: if the second usage flag indicates that the programmable logic unit has moved data and data is to be received, then the second data is not moved to the data memory.

[0011] Optionally, in some embodiments of the present disclosure, the method further includes: configuring the first write pointer to indicate the processor to receive the next second descriptor in the queue.

[0012] Optionally, in some embodiments of the present disclosure, the method further includes: polling and reading at least one first message from a doorbell message queue.

[0013] A second aspect of the present disclosure provides a data processing method, which is executed by a processor and includes: determining a second write pointer, wherein the second write pointer is used to indicate a first descriptor in a processor sending queue corresponding to an interface type, the first descriptor including: a data storage address to be filled, a second data length to be filled, and a first usage flag; if the first usage flag indicates that the processor has not filled data or the data has been read, updating the data storage address to be filled to a first storage address corresponding to the first data in a data memory, wherein the first data has a corresponding first data length; updating the second data length to be filled to the first data length, and configuring the first usage flag to indicate that the processor has filled data and the data is to be read; generating and providing a first message according to the port number and interface type corresponding to the second write pointer, wherein the first message is used to instruct the programmable logic unit to read the first data from the data memory based on the first data length and the first storage address storage.

[0014] Optionally, in some embodiments of the present disclosure, the method further includes: if the first usage flag indicates that the processor has filled the data and the data is to be read, then the storage address of the data to be filled is not updated.

[0015] Optionally, in some embodiments of the present disclosure, the method further includes: configuring a second write pointer to instruct the processor to send the next first descriptor in the queue.

[0016] Optionally, in some embodiments of the present disclosure, the method also includes: determining a second read pointer, wherein the second read pointer is used to indicate a second descriptor in the processor receive queue, the second descriptor including: a second storage address, a first data length to be filled, and a second usage flag; if the second usage flag indicates that the programmable logic unit has moved data and data is to be received, allocating an empty buffer in the data memory for the second storage address; setting the first data length to be filled to 0, and configuring the second usage flag to indicate that the processor has completed reception and data is to be moved.

[0017] Optionally, in some embodiments of the present disclosure, the method further includes: if the second usage flag indicates that the processor has completed receiving and data is to be moved, then no empty buffer is allocated in the data memory for the second storage address.

[0018] Optionally, in some embodiments of the present disclosure, the method further includes: configuring a second read pointer to indicate the processor to receive the next second descriptor in the queue.

[0019] Optionally, in some embodiments of the present disclosure, the method further includes: adding the first message to a doorbell message queue.

[0020] An embodiment of the third aspect of the present disclosure proposes a data processing device, which is executed by a programmable logic unit, including: a first acquisition unit, used to acquire a first message sent by a processor, wherein the first message includes: a port number and an interface type; a first determination unit, used to determine a first read pointer corresponding to a port to which the port number belongs, wherein the first read pointer is used to indicate a first descriptor in a processor send queue corresponding to the interface type, and the first descriptor includes: a first storage address, a first data length, and a first usage flag; a second acquisition unit, used to read the first data from the data memory based on the first storage address and the first data length when the first usage flag indicates that the processor has filled the data and the data is to be read.

[0021] Optionally, in some embodiments of the present disclosure, the device is also used to: after reading the first data from the data memory based on the first storage address and the first data length, store the first data locally, and configure a first usage flag to indicate that the data has been read.

[0022] Optionally, in some embodiments of the present disclosure, the apparatus is further used to: configure a first read pointer to instruct the processor to send the next first descriptor in the queue.

[0023] Optionally, in some embodiments of the present disclosure, the device is also used to: determine a first write pointer, wherein the first write pointer is used to indicate a second descriptor in a processor receive queue, the second descriptor including: a second storage address, a first data length to be filled, and a second usage flag; if the second usage flag indicates that the processor has completed reception and data is to be moved, the second data is moved to a data memory corresponding to the second storage address, wherein the second data has a corresponding second data length; the first data length to be filled is updated to the second data length, and the second usage flag is configured to indicate that the programmable logic unit has moved the data and the data is to be received.

[0024] Optionally, in some embodiments of the present disclosure, the device is further used for: if the second usage flag indicates that the programmable logic unit has moved data and data is to be received, not moving the second data to the data memory.

[0025] Optionally, in some embodiments of the present disclosure, the apparatus is further used to: configure the first write pointer to indicate the processor to receive the next second descriptor in the queue.

[0026] Optionally, in some embodiments of the present disclosure, the device is further used to: poll and read at least one first message from a doorbell message queue.

[0027] An embodiment of the fourth aspect of the present disclosure proposes a data processing device, which is executed by a processor, including: a second determination unit, which is used to determine a second write pointer, wherein the second write pointer is used to indicate a first descriptor in a processor sending queue corresponding to an interface type, and the first descriptor includes: a data storage address to be filled, a second data length to be filled, and a first usage flag; a first update unit, which is used to update the data storage address to be filled to a first storage address corresponding to the first data in a data memory if the first usage flag indicates that the processor has not filled the data or the data has been read, wherein the first data has a corresponding first data length; a second update unit, which is used to update the second data length to be filled to the first data length, and configure the first usage flag to indicate that the processor has filled the data and the data is to be read; a generation unit, which is used to generate and provide a first message according to a port number and an interface type corresponding to the second write pointer, wherein the first message is used to instruct the programmable logic unit to read the first data from the data memory based on the first data length and the first storage address storage.

[0028] Optionally, in some embodiments of the present disclosure, the apparatus is further configured to: if the first usage flag indicates that the processor has filled the data and the data is to be read, then the storage address of the data to be filled is not updated.

[0029] Optionally, in some embodiments of the present disclosure, the apparatus is further used to: configure a second write pointer to instruct the processor to send the next first descriptor in the queue.

[0030] Optionally, in some embodiments of the present disclosure, the device is also used to: determine a second read pointer, wherein the second read pointer is used to indicate a second descriptor in the processor receiving queue, the second descriptor including: a second storage address, a first data length to be filled, and a second usage flag; if the second usage flag indicates that the programmable logic unit has moved data and data is to be received, an empty buffer is allocated in the data memory for the second storage address; the first data length to be filled is set to 0, and the second usage flag is configured to indicate that the processor has completed reception and the data is to be moved.

[0031] Optionally, in some embodiments of the present disclosure, the device is further used for: if the second usage flag indicates that the processor has completed receiving and the data is to be moved, then no empty buffer is allocated in the data memory for the second storage address.

[0032] Optionally, in some embodiments of the present disclosure, the apparatus is further configured to: configure a second read pointer to indicate to the processor to receive a next second descriptor in the queue.

[0033] Optionally, in some embodiments of the present disclosure, the device is further used to: add the first message to a doorbell message queue.

[0034] An embodiment of the fifth aspect of the present disclosure proposes a data processing device, including a memory, a transceiver, and a programmable logic unit: the memory is used to store computer programs; the transceiver is used to send and receive data under the control of a processor; the programmable logic unit is used to read the computer program in the memory and perform the following operations: obtain a first message sent by the processor, wherein the first message includes: a port number and an interface type; determine a first read pointer corresponding to the port to which the port number belongs, wherein the first read pointer is used to indicate a first descriptor in a processor send queue corresponding to the interface type, the first descriptor including: a first storage address, a first data length, and a first usage flag; if the first usage flag indicates that the processor has filled data and data is to be read, read the first data from the data memory based on the first storage address and the first data length.

[0035] Optionally, in some embodiments of the present disclosure, the programmable logic unit is also used to: after reading the first data from the data memory based on the first storage address and the first data length, store the first data locally, and configure a first usage flag to indicate that the data has been read.

[0036] Optionally, in some embodiments of the present disclosure, the programmable logic unit is further used to: configure the first read pointer to instruct the processor to send the next first descriptor in the queue.

[0037] Optionally, in some embodiments of the present disclosure, the programmable logic unit is also used to: determine a first write pointer, wherein the first write pointer is used to indicate a second descriptor in a processor receive queue, the second descriptor including: a second storage address, a first data length to be filled, and a second usage flag; if the second usage flag indicates that the processor has completed reception and data is to be moved, then the second data is moved to a data memory corresponding to the second storage address, wherein the second data has a corresponding second data length; the first data length to be filled is updated to the second data length, and the second usage flag is configured to indicate that the programmable logic unit has moved the data and the data is to be received.

[0038] Optionally, in some embodiments of the present disclosure, the programmable logic unit is further configured to: if the second usage flag indicates that the programmable logic unit has moved data and data is to be received, then not move the second data to the data memory.

[0039] Optionally, in some embodiments of the present disclosure, the programmable logic unit is further used to: configure the first write pointer to indicate the next second descriptor in the processor receiving queue.

[0040] Optionally, in some embodiments of the present disclosure, the programmable logic unit is further used to: poll and read at least one first message from a doorbell message queue.

[0041] The sixth aspect embodiment of the present disclosure proposes a data processing device, including: a memory, a transceiver, and a processor: the memory is used to store a computer program; the transceiver is used to send and receive data under the control of the processor; the processor is used to read the computer program in the memory and perform the following operations: determine a second write pointer, wherein the second write pointer is used to indicate a first descriptor in the processor sending queue corresponding to the interface type, the first descriptor including: a data storage address to be filled, a second data length to be filled, and a first usage flag; if the first usage flag indicates that the processor has not filled the data or the data has been read, the data storage address to be filled is updated to the first storage address corresponding to the first data in the data memory, wherein the first data has a corresponding first data length; the second data length to be filled is updated to the first data length, and the first usage flag is configured to indicate that the processor has filled the data and the data is to be read; generate and provide a first message according to the port number and interface type corresponding to the second write pointer, wherein the first message is used to instruct the programmable logic unit to read the first data from the data memory based on the first data length and the first storage address storage.

[0042] Optionally, in some embodiments of the present disclosure, the processor is further configured to: not update the storage address of the data to be filled if the first usage flag indicates that the processor has filled the data and the data is to be read.

[0043] Optionally, in some embodiments of the present disclosure, the processor is further configured to: configure a second write pointer to instruct the processor to send the next first descriptor in the queue.

[0044] Optionally, in some embodiments of the present disclosure, the processor is also used to: determine a second read pointer, wherein the second read pointer is used to indicate a second descriptor in the processor receiving queue, the second descriptor including: a second storage address, a first data length to be filled, and a second usage flag; if the second usage flag indicates that the programmable logic unit has moved data and data is to be received, an empty buffer is allocated in the data memory for the second storage address; the first data length to be filled is set to 0, and the second usage flag is configured to indicate that the processor has completed reception and the data is to be moved.

[0045] Optionally, in some embodiments of the present disclosure, the processor is further configured to: if the second usage flag indicates that the processor has completed receiving and data is to be moved, then no empty buffer is allocated in the data memory for the second storage address.

[0046] Optionally, in some embodiments of the present disclosure, the processor is further configured to: configure a second read pointer to indicate the processor to receive a next second descriptor in the queue.

[0047] Optionally, in some embodiments of the present disclosure, the processor is further configured to: add the first message to a doorbell message queue.

[0048] The processor-readable storage medium proposed in the seventh aspect embodiment of the present disclosure stores a computer program, and the computer program is used to enable the processor to execute: the data processing method proposed in the first aspect embodiment of the present disclosure, or the data processing method proposed in the second aspect embodiment of the present disclosure.

[0049] The data processing method, device and processor-readable storage medium proposed in the present disclosure obtain a first message sent by a processor, wherein the first message includes: a port number and an interface type, and determine a first read pointer corresponding to the port to which the port number belongs, wherein the first read pointer is used to indicate a first descriptor in a processor send queue corresponding to the interface type, and the first descriptor includes: a first storage address, a first data length and a first use flag. If the first use flag indicates that the processor has filled data and the data is to be read, the first data is read from the data memory based on the first storage address and the first data length, thereby realizing lightweight data transmission and reception, and realizing efficient data transmission and reception communication. The memory overhead of data transmission and reception is small and the implementation is simple, thereby effectively reducing the development cost, and the device can be applied to low-load processors, with a wide range of applications.

[0050] Additional aspects and advantages of the present disclosure will be given in part in the following description and in part will be obvious from the following description or learned through practice of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The above and / or additional aspects and advantages of the present disclosure will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0052] Figure 1 is a flowchart of a data processing method proposed in an embodiment of the present disclosure;

[0053] Figure 2 is a schematic diagram of a descriptor queue in an implementation of the present disclosure;

[0054] Figure 3 is a schematic diagram of the data sending and receiving mechanism flow in an embodiment of the present disclosure;

[0055] Figure 4 is a flowchart of a data processing method proposed in another embodiment of the present disclosure;

[0056] Figure 5 is a flowchart of a data processing method proposed in another embodiment of the present disclosure;

[0057] Figure 6 is a flowchart of a data processing method proposed in another embodiment of the present disclosure;

[0058] Figure 7 is a flowchart of a data processing method proposed in another embodiment of the present disclosure;

[0059] Figure 8 is a schematic diagram of a data transmission process in an embodiment of the present disclosure;

[0060] Fig. 9 is a flowchart of a data processing method proposed in another embodiment of the present disclosure;

[0061] Fig.10 is a schematic diagram of a data receiving process in an embodiment of the present disclosure;

[0062] Fig.11 is a structural diagram of a data processing device proposed in an embodiment of the present disclosure;

[0063] Fig.12 is a structural diagram of a data processing device proposed in another embodiment of the present disclosure

[0064] Fig.13 is a structural schematic diagram of a data processing device proposed in another embodiment of the present disclosure;

[0065] Fig.14It is a structural diagram of a data processing device proposed in another embodiment of the present disclosure. DETAILED DESCRIPTION

[0066] In the embodiments of the present disclosure, the term "and / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent three situations: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0067] The term "plurality" in the embodiments of the present disclosure refers to two or more than two, and other quantifiers are similar thereto.

[0068] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0069] The present disclosure is to solve the problem in the related art that the DPDK is huge and not suitable for low-load processors, resulting in serious idling of the central processor and high system overhead, which leads to some processors not supporting the DPDK development kit and some processors being unable to achieve good data transceiving functions. In view of the situation that chips with limited processor resources cannot use the DPDK technology, a data processing method is proposed. By obtaining a first message sent by a processor, wherein the first message includes: a port number and an interface type, a first read pointer corresponding to the port to which the port number belongs is determined, wherein the first read pointer is used to indicate a first descriptor in a processor sending queue corresponding to the interface type, and the first descriptor includes: a first storage address, a first data length, and a first use flag. If the first use flag indicates that the processor has filled data and the data is to be read, the first data is read from the data memory based on the first storage address and the first data length, so as to achieve lightweight data transceiving and efficient data transceiving and communication, and the memory overhead of data transceiving is small and the implementation is simple, thereby effectively reducing the development cost, and the method can be applied to low-load processors, and has a high degree of application.

[0070] The technical solution provided by the embodiments of the present disclosure can be applicable to a variety of systems, especially 5G systems. For example, the applicable system can be a global system of mobile communication (GSM) system, a code division multiple access (CDMA) system, a wideband code division multiple access (WCDMA) general packet radio service (GPRS) system, a long term evolution (LTE) system, a LTE frequency division duplex (FDD) system, a LTE time division duplex (TDD) system, an advanced long term evolution (LTE-A) system, a universal mobile telecommunication system (UMTS), a world-wide interoperability for microwave access (WiMAX) system, a 5G new radio (NR) system, etc. These various systems include terminal equipment and network equipment. The system may also include a core network part, such as an evolved packet system (EPS), a 5G system (5GS), etc.

[0071] Figure 1 It is a flowchart of a data processing method proposed in an embodiment of the present disclosure.

[0072] It should be noted that the data processing method of this embodiment is executed by a data processing device, which can be implemented by software and / or hardware, and can be configured in a network device. The network device refers to a communication device that can be used to transmit and receive digital signals.

[0073] The network device can be used to convert received air frames to and from Internet Protocol (IP) packets, acting as a router between the wireless terminal device and the rest of the access network, which may include an Internet Protocol (IP) communications network. The network device can also coordinate the management of attributes of the air interface.

[0074] For example, the network device involved in the embodiments of the present disclosure may be a network device (Base Transceiver Station, BTS) in the Global System for Mobile communications (Global System for Mobile communications, GSM) or Code Division Multiple Access (Code Division Multiple Access, CDMA), or a network device (NodeB) in Wide-band Code Division Multiple Access (WCDMA), or an evolutionary network device (evolutional Node B, eNB or e-NodeB) in the long term evolution (long term evolution, LTE) system, a 5G base station (gNB) in the 5G network architecture (next generation system), or a home evolved Node B (Home evolved Node B, HeNB), a relay node, a home base station (femto), a pico base station (pico), etc., which is not limited in the embodiments of the present disclosure. In some network structures, the network device may include a centralized unit (CU) node and a distributed unit (DU) node, and the centralized unit and the distributed unit may also be arranged geographically separately.

[0075] like Figure 1 As shown, the data processing method is executed by a programmable logic unit and includes:

[0076] This embodiment can be applied to a programmable logic unit, wherein the programmable logic unit refers to a programmable logic array. The programmable logic unit can control a direct memory access module (Direct Memory Acess, DMA) to send and receive data, thereby realizing the entry and exit of data in a programmable logic unit board. The programmable logic unit can be a field programmable gate array (Field Programmable Gate Array, FPGA), or can also be applied to any other programmable logic unit, without limitation.

[0077] S101: Acquire a first message sent by a processor, wherein the first message includes: a port number and an interface type.

[0078] Among them, the first message refers to a communication message sent by the processor to instruct the programmable logic unit to read the upper-layer application data to fill the business data in the data memory. The first message can be used to identify the services to which different data queues belong. The first message includes: port number and interface type. The first message can be generated and sent by the processor and added to the doorbell message queue Doorbell. The first message is filled with a 16-bit data message, which is divided into high 8 bits and low 8 bits, wherein the high 8 bits are filled with the interface type and the low 8 bits are filled with the port number.

[0079] The port number may be used to indicate a corresponding read pointer of the programmable logic unit in the processor sending queue.

[0080] The interface type may be used to indicate obtaining a descriptor in a processor send queue.

[0081] The processor is another subject involved in data transmission and reception. The processor may be a central processing unit (CPU), or may be any other processor, and there is no limitation on this.

[0082] The application scenario of the embodiment of the present disclosure can be that the upper-layer application places data in the data memory, the processor places the relevant information of the data storage in the processor sending queue, and the programmable logic unit reads the data from the processor sending queue. At this time, the first message sent by the processor can be obtained first. When obtaining the first message sent by the processor, the processor can generate a corresponding 16-bit data message according to the port number and interface type corresponding to the business to which the upper-layer application data to be sent and received belongs, and according to the port number and interface type, fill the interface type in the high 8 bits of the data message, fill the port number in the low 8 bits of the data message, and use the data message as the first message. Then, the processor can send the first message to the doorbell message queue, and the programmable logic unit can poll and read the first message from the doorbell message queue. One first message can be read at the same time, or multiple first messages can be read at the same time, so as to enable the programmable logic unit to obtain the first message sent by the processor.

[0083] S102: Determine a first read pointer corresponding to the port to which the port number belongs, wherein the first read pointer is used to indicate a first descriptor in a processor send queue corresponding to the interface type, and the first descriptor includes: a first storage address, a first data length, and a first usage flag.

[0084] Among them, the processor sending queue refers to a data queue containing multiple first descriptors for assisting the processor to send data from the upper-layer application to the programmable logic unit. The processor sending queue may contain multiple first descriptors, and each first descriptor is used to describe the storage status of the data in the data memory.

[0085] The first descriptor refers to the data description information in the processor sending queue used to indicate the data storage status in the data memory. The first descriptor includes: a first storage address, a first data length, and a first use flag. The processor sending queue may contain multiple first descriptors, such as Figure 2 As shown, Figure 2 is a schematic diagram of a descriptor queue in the implementation of the present disclosure, wherein each STR_SRIO_BD represents a descriptor, and there may be N descriptors in the queue.

[0086] The first read pointer is used to indicate a first descriptor in the processor sending queue corresponding to the interface type.

[0087] The first storage address refers to the actual storage address of the data sent by the upper-layer application data in the data memory, and the first storage address may be a data storage start address.

[0088] The first data length is the actual data length of the data sent by the upper-layer application data stored in the first storage address in the data memory.

[0089] The first use flag bit refers to a data identifier used to indicate whether data is actually stored in the first storage address. The first use flag bit can have two states: a READY state and a !READY state. The READY state is a state where the processor has filled data and is waiting for the programmable logic unit to read it, and the !READY state is a state where the processor has not filled data or the programmable logic unit has completed reading.

[0090] In the embodiment of the present disclosure, after obtaining the first message sent by the processor as mentioned above, the port number in the first message can be parsed and obtained, and a first read pointer corresponding to the port to which the port number belongs can be determined, the first read pointer is used to indicate a first descriptor in the processor send queue corresponding to the interface type, and then the following are first obtained from the first descriptor: a first storage address, a first data length, and a first usage flag, the first storage address indicating the actual storage address in the data memory of the data sent by the upper-layer application data, the first data length indicating the actual data length of the data sent by the upper-layer application data stored in the first storage address in the data memory, the first usage flag indicating whether data is actually stored in the first storage address, and the programmable logic unit can obtain the data sent by the upper-layer application and stored in the data memory from the data content according to the first storage address, the first data length, and the first usage flag.

[0091] S103: If the first usage flag indicates that the processor has filled the data and the data is to be read, read the first data from the data memory based on the first storage address and the first data length.

[0092] Among them, the first data refers to the data actually stored in the data memory corresponding to the first storage address. The first data may be data sent by an upper-layer application and stored in the data memory. The actual data length of the first data is used as the first data length. The processor can fill the first storage address and the first data length into the first descriptor in the processor sending queue, and the programmable logic unit reads the first data from the data memory according to the first storage address and the first data length in the first descriptor.

[0093] After obtaining the first message sent by the processor and determining the first read pointer corresponding to the port to which the port number belongs, the embodiment of the present disclosure can read the first data from the data memory based on the first storage address and the first data length when the first usage flag indicates that the processor has filled the data and the data is to be read.

[0094] In the disclosed embodiment, the first usage flag bit can be analyzed. If the first usage flag bit is in the READY state, the first usage flag bit indicates that the processor has filled the data and the data is to be read, which means that the processor has filled the first storage address of the first data in the data memory into the first descriptor, and the data has not been read by the programmable logic unit. The programmable logic unit can read the first data from the data memory based on the first storage address and the first data length. The first storage address serves as the starting storage address of the first data in the data memory. The programmable logic unit can read the complete first data from the data memory based on the first data length and the first storage address, thereby enabling the editable logic unit to read the data stored in the data memory by the upper-level application.

[0095] The data processing method proposed in the embodiment of the present disclosure adopts the joint memory management (Ethernet Over RapidIO, EOR) technology to manage the data memory in the case that the chip with limited processor resources cannot use the DPDK technology, and creates multiple queues composed of memories (executed by the processor). The queue contains members composed of descriptors, each member has corresponding member information (data storage address, data length and usage flag bit), and each member points to a piece of data memory. For example, Figure 3 As shown, Figure 3 : is a flow chart of the data receiving and sending mechanism in the embodiment of the present disclosure. The memory information processor (CPU) and the editable logic unit (FPGA) in each queue can access it. Among them, DataPtr represents the data storage address, pointing to the CPU side buffer BUFFER, DataLen represents the data length, and ReadyFlag represents the use flag. The processor and the editable logic unit find the data memory location and data length information by accessing the queue member information of EOR to complete the reading and writing of data, thereby achieving the reading and writing of data by the application layer and the entry and exit of data to the board of the editable logic unit network. Among them, EOR, as a manager, creates multiple queues when the task starts. Each queue consists of multiple addresses pointing to data storage, data length and flags of whether the data is used. Multiple queues are grouped in pairs. For example, Figure 3 The CPU sending queue and CPU receiving queue in the FPGA are used to complete the sending and receiving of one data type. Since each soft core may correspond to multiple data types, each soft core will be bound to one or more groups of queues according to system requirements to ensure the flow of data of all types of services of each soft core between the CPU and FPGA.

[0096] In this embodiment, by obtaining a first message sent by a processor, wherein the first message includes: a port number and an interface type, a first read pointer corresponding to the port to which the port number belongs is determined, wherein the first read pointer is used to indicate a first descriptor in a processor send queue corresponding to the interface type, and the first descriptor includes: a first storage address, a first data length, and a first usage flag. If the first usage flag indicates that the processor has filled data and the data is to be read, the first data is read from the data memory based on the first storage address and the first data length, thereby achieving lightweight data transmission and reception, and achieving efficient data transmission and reception communication. The memory overhead of data transmission and reception is small, and the implementation is simple, thereby effectively reducing the development cost, and can be applied to low-load processors, with a wide range of applications.

[0097] Figure 4 It is a flowchart of a data processing method proposed in another embodiment of the present disclosure.

[0098] like Figure 4As shown, the data processing method comprises:

[0099] S401: Acquire a first message sent by a processor, wherein the first message includes: a port number and an interface type.

[0100] S402: Determine a first read pointer corresponding to the port to which the port number belongs, wherein the first read pointer is used to indicate a first descriptor in a processor send queue corresponding to the interface type, and the first descriptor includes: a first storage address, a first data length, and a first usage flag.

[0101] S403: If the first usage flag indicates that the processor has filled the data and the data is to be read, read the first data from the data memory based on the first storage address and the first data length.

[0102] For the detailed description of S401 to S403 , please refer to the above embodiment, which will not be repeated here.

[0103] S404: Store the first data locally, and configure a first usage flag to indicate that the data has been read.

[0104] In the embodiment of the present disclosure, when the first usage flag indicates that the processor has filled data and data is to be read, after reading the first data from the data memory based on the first storage address and the first data length, the first data can be stored locally and the first usage flag can be configured to indicate that the data has been read.

[0105] In the embodiment of the present disclosure, the direct memory access module DMA can be started by the programmable logic unit to control the DMA to save the first data read from the data memory locally, and change the first usage flag bit from indicating that the processor has filled the data and the data is to be read (READY state) to the first usage flag bit indicating that the data has been read (!READY state).

[0106] S405: Configure a first read pointer to instruct the processor to send the next first descriptor in the queue.

[0107] In the embodiment of the present disclosure, after the first data is stored locally and the first usage flag is configured to indicate that the data has been read, a first read pointer needs to be configured to instruct the processor to send the next first descriptor in the queue, so that the programmable logic unit repeats the above data reading process, so that the programmable logic unit can read the first data stored in the first storage address in all the first descriptors in the queue until the data reading is completed.

[0108] In some other embodiments, if the programmable logic unit determines that the first use flag bit in the first descriptor corresponding to the first read pointer is in the READY state, it means that the processor sending queue is empty, and the programmable logic unit suspends the migration of the current network port.

[0109] S406: poll and read at least one first message from the doorbell message queue.

[0110] In the embodiment of the present disclosure, there is at least one first message in the doorbell message queue that is generated, sent, and added to the doorbell message queue Doorbell by the processor, and one first message indicates a data sending queue. The programmable logic unit can read one first message from the doorbell message queue, and the programmable logic unit can read one first data stored in the data memory indicated by a descriptor in a processor sending queue alone, or the programmable logic unit can read multiple first messages from the doorbell message queue, so that the programmable logic unit can read the first data stored in the data memory indicated by the descriptors in the processor sending queues corresponding to multiple different ports in parallel, and there is no restriction on this.

[0111] In this embodiment, by acquiring a first message sent by a processor, wherein the first message includes: a port number and an interface type, a first read pointer corresponding to the port to which the port number belongs is determined, wherein the first read pointer is used to indicate a first descriptor in a processor send queue corresponding to the interface type, and the first descriptor includes: a first storage address, a first data length, and a first use flag. If the first use flag indicates that the processor has filled data and the data is to be read, the first data is read from a data memory based on the first storage address and the first data length, the first data is stored locally, and the first use flag is configured to indicate that the data has been read, and the first read pointer is configured to indicate the next first descriptor in the processor send queue, and at least one first message is polled and read from a doorbell message queue, thereby realizing the transmission of data of an upper-layer application to a local programmable logic unit based on a lightweight data transceiver method, traversing the processor send queue based on the first read pointer to ensure the integrity of data reading, and since the programmable logic unit polls and reads at least one first message from the doorbell message queue each time, parallel data reading can be realized to ensure data reading efficiency.

[0112] Figure 5 It is a flowchart of a data processing method proposed in another embodiment of the present disclosure.

[0113] like Figure 5 As shown, the data processing method comprises:

[0114] S501: Determine a first write pointer, wherein the first write pointer is used to indicate a second descriptor in a processor receiving queue, and the second descriptor includes: a second storage address, a first length of data to be filled, and a second use flag.

[0115] Among them, the processor receive queue refers to a data queue containing a second descriptor for sending and receiving data between a programmable logic unit and a processor. The processor receive queue may contain multiple second descriptors, and each second descriptor is used to indicate the data storage status of a data memory corresponding to a storage address.

[0116] The first write pointer is used to indicate a second descriptor in the processor receiving queue.

[0117] Among them, the second descriptor refers to the data description information in the processor receiving queue used to indicate the data storage status in the data memory. The second descriptor includes: a second storage address, a first data length to be filled, and a second usage flag. The processor sending queue can contain multiple second descriptors.

[0118] The second storage address is used to indicate a data storage space in the data memory for storing data.

[0119] The first filling data length refers to a to-be-filled variable pre-set in the second descriptor for filling the data length.

[0120] Among them, the second use flag is a data flag bit used to indicate whether the data memory corresponding to the second storage address stores data. The second use flag bit can have two states: READY state and !READY state. The READY state is a state where the programmable logic unit fills the data and moves it to the processor for reception. In other words, the data memory corresponding to the second storage address stores data. The !READY state is a state where the processor receives the data and waits for the programmable logic unit to fill the data. In other words, the data memory corresponding to the second storage address does not store data.

[0121] In the embodiment of the present disclosure, a first write pointer can be determined, the first write pointer indicates a second descriptor in the processor receiving queue, the second descriptor includes: a second storage address, a first length of data to be filled, and a second use flag, the second storage address indicates a data storage space in the data memory that can be used to store data, the first fill data length is used to indicate the data length of the data to be filled in the data memory corresponding to the second storage address, the second use flag indicates whether the data memory corresponding to the second storage address stores data, when the second use flag is in the READY state, the second use flag is the programmable logic unit filling data move completed waiting for the processor to receive the state, that is, the data memory corresponding to the second storage address stores data, when the second use flag is in the READY state, the second use flag is the processor receiving the completion waiting for the programmable logic unit to fill the data state.

[0122] S502: If the second use flag indicates that the processor has completed receiving and the data is to be moved, move the second data to the data memory corresponding to the second storage address, wherein the second data has a corresponding second data length.

[0123] The second data refers to the network data received by the programmable logic unit from the network port of the board. The programmable logic unit can push the second data to the processor, so that the processor pushes the second data to the upper-layer application.

[0124] The second data length refers to the actual data length of the second data.

[0125] In the embodiment of the present disclosure, after determining the first write pointer and acquiring a second descriptor in the processor receive queue indicated by the first write pointer, the second use flag bit may be analyzed and processed.

[0126] In the embodiment of the present disclosure, the second use flag bit can be analyzed and processed. If the second use flag bit is in the READY state, it means that the second use flag bit indicates that the processor has completed receiving and the data is to be moved, and then the programmable logic unit can move the second data received from the board network port to the data memory corresponding to the second storage address.

[0127] S503: Update the first data length to be filled to the second data length, and configure the second use flag to indicate that the programmable logic unit has moved the data and the data is to be received.

[0128] In the embodiment of the present disclosure, when the second usage flag indicates that the processor has completed receiving and the data is to be moved, after the second data is moved to the data memory corresponding to the second storage address, the first data length to be filled can be updated to the second data length, and the second usage flag can be updated from a state indicating that the processor has completed receiving and the data is to be moved to a state indicating that the programmable logic unit has moved the data and the data is to be received, so that the processor can receive data according to the processor receive queue.

[0129] S504: If the second use flag indicates that the programmable logic unit has moved data and data is to be received, the second data is not moved to the data memory.

[0130] In the disclosed embodiment, the second usage flag bit can be analyzed and processed. If the second usage flag bit is in the READY state, it indicates that the programmable logic unit has moved the data and the data is to be received. At this time, data is already stored in the data memory corresponding to the second storage address. The programmable logic unit cannot move the data to the data memory corresponding to the second storage address, and the second data will not be moved to the data memory.

[0131] S505: Configure a first write pointer to instruct the processor to receive the next second descriptor in the queue.

[0132] In the embodiment of the present disclosure, when the second usage flag indicates that the processor has completed receiving and data is to be moved, after the second data is moved to the data memory corresponding to the second storage address, the first write pointer can be configured to indicate the next second descriptor in the processor receive queue, and the above data moving process is repeated, so that the programmable logic unit can complete the data moving process from the processor receive queue to the data memory corresponding to the second data storage address in the second descriptor until the processor receive queue is processed.

[0133] In this embodiment, by determining a first write pointer, wherein the first write pointer is used to indicate a second descriptor in a processor receive queue, the second descriptor includes: a second storage address, a first data length to be filled, and a second usage flag. If the second usage flag indicates that the processor has completed reception and data is to be moved, the second data is moved to a data memory corresponding to the second storage address, wherein the second data has a corresponding second data length, the first data length to be filled is updated to the second data length, and the second usage flag is configured to indicate that the programmable logic unit has moved the data and the data is to be received, so that when the storage address indicated by the processor receive queue descriptor has storage space, the network data from the network port of the programmable logic unit can be moved to the data memory, and orderly data movement can be achieved based on the processor receive queue. The upper-layer application can obtain data from the data memory, thereby achieving effective data transmission between the programmable logic unit and the upper-layer application.

[0134] Figure 6 It is a flowchart of a data processing method proposed in another embodiment of the present disclosure.

[0135] like Figure 6 As shown, the data processing method is executed by a processor and includes:

[0136] S601: Determine a second write pointer, wherein the second write pointer is used to indicate a first descriptor in a processor send queue corresponding to an interface type, the first descriptor comprising: a storage address of data to be filled, a second length of data to be filled, and a first use flag.

[0137] The data storage address to be filled refers to the address variable to be filled into which the processor fills the actual storage address of the upper-layer application data in the data memory.

[0138] The second length of data to be filled refers to a variable of the length of data to be filled, which is used by the processor to fill in the data length of the upper-layer application data stored in the data memory.

[0139] In the implementation of the present disclosure, the second write pointer of the processor in the processor send queue can be determined, and the second write pointer is used to indicate a first descriptor in the processor send queue corresponding to the interface type, and the first descriptor includes: a data storage address to be filled, a second data length to be filled, and a first usage flag. The data storage address to be filled is a to-be-filled address variable into which the processor fills the actual storage address of the upper-layer application data in the data memory, the second data length to be filled is a to-be-filled data length variable into which the processor fills the data length of the upper-layer application data stored in the data memory, and the first usage flag is used to indicate whether the processor has filled the data storage address into the data storage address to be filled.

[0140] S602: If the first usage flag indicates that the processor has not filled the data or the data has been read, the storage address of the data to be filled is updated to a first storage address corresponding to the first data in the data memory, wherein the first data has a corresponding first data length.

[0141] The first data refers to the data pre-sent by the upper layer application and stored in the data memory, and the actual data length of the first data is taken as the first data length.

[0142] After determining the second write pointer and acquiring a first descriptor in the processor send queue corresponding to the interface type indicated by the second write pointer, the embodiment of the present disclosure may analyze the first usage flag bit in the first descriptor.

[0143] In the embodiment of the present disclosure, the first use flag bit in the first descriptor can be analyzed. If the first use flag bit is in the !REDAY state, it means that the processor has not filled the data or the data has been read. Then, the processor can fill the first storage address of the first data that has been stored in the data memory by the upper-layer application into the data storage address to be filled, so as to update the data storage address to be filled to the first storage address corresponding to the first data in the data memory.

[0144] S603: Update the second length of data to be filled to the first data length, and configure a first usage flag to indicate that the processor has filled the data and the data is to be read.

[0145] In the embodiment of the present disclosure, when the first usage flag indicates that the processor has not filled the data or the data has been read, after the storage address of the data to be filled is updated to the first storage address corresponding to the first data in the data memory, the first data length can be filled into the second data length to be filled, thereby updating the second data length to be filled to the first data length, and updating the first usage flag from indicating that the processor has not filled the data or the data has been read to indicating that the processor has filled the data and the data is to be read, so that the programmable data unit can read and move the first data from the data memory based on the first storage address and the first data length.

[0146] S604: Generate and provide a first message according to the port number and interface type corresponding to the second write pointer, wherein the first message is used to instruct the programmable logic unit to read the first data from the data memory based on the first data length and the first storage address storage.

[0147] In the embodiment of the present disclosure, the processor can generate a first message according to the port number and interface type corresponding to the second write pointer, and fill the first message into the doorbell message queue, so that the programmable logic unit can read the first message from the doorbell message queue, and the first message is used to instruct the programmable logic unit to read the first data from the data memory based on the first data length and the first storage address.

[0148] In this embodiment, by determining a second write pointer, wherein the second write pointer is used to indicate a first descriptor in a processor sending queue corresponding to the interface type, the first descriptor includes: a data storage address to be filled, a second data length to be filled, and a first usage flag. If the first usage flag indicates that the processor has not filled the data or the data has been read, the data storage address to be filled is updated to the first storage address corresponding to the first data in the data memory, wherein the first data has a corresponding first data length, the second data length to be filled is updated to the first data length, and the first usage flag is configured to indicate that the processor has filled the data and the data is to be read. According to the port number and interface type corresponding to the second write pointer, a first message is generated and provided, wherein the first message is used to instruct the programmable logic unit to read the first data from the data memory based on the first data length and the first storage address storage, so that the processor can fill the storage address of the data in the data memory into the processor sending queue, and generate a corresponding first message to instruct the programmable logic unit to read the data. The occupancy of the data storage space is judged based on the data usage flag to avoid packet loss during data transmission. The data transmission method is simple to implement and efficient and orderly data transmission is achieved.

[0149] Figure 7 It is a flowchart of a data processing method proposed in another embodiment of the present disclosure.

[0150] like Figure 7 As shown, the data processing method is executed by a processor and includes:

[0151] S701: Determine a second write pointer, wherein the second write pointer is used to indicate a first descriptor in a processor send queue corresponding to an interface type, the first descriptor comprising: a storage address of data to be filled, a second length of data to be filled, and a first use flag.

[0152] S702: If the first usage flag indicates that the processor has not filled the data or the data has been read, the storage address of the data to be filled is updated to a first storage address corresponding to the first data in the data memory, wherein the first data has a corresponding first data length.

[0153] S703: Update the second data length to be filled to the first data length, and configure the first use flag to indicate that the processor has filled the data and the data is to be read.

[0154] S704: Generate and provide a first message according to the port number and interface type corresponding to the second write pointer, wherein the first message is used to instruct the programmable logic unit to read the first data from the data memory based on the first data length and the first storage address storage.

[0155] For the detailed description of S701 and S704 , please refer to the above embodiments, which will not be repeated here.

[0156] S705: Add the first message to the doorbell message queue.

[0157] In the embodiment of the present disclosure, after generating and providing the first message according to the port number and interface type corresponding to the second write pointer, the processor can fill the first message into the doorbell message queue, so that the programmable logic unit can read the first message from the doorbell message queue, and the first message is used to instruct the programmable logic unit to read the first data from the data memory based on the first data length and the first storage address.

[0158] S706: If the first use flag indicates that the processor has filled the data and the data is to be read, the storage address of the data to be filled is not updated.

[0159] In the embodiment of the present disclosure, the first usage flag bit can be analyzed and processed. If the first usage flag bit indicates that the processor has filled the data and the data is to be read, it means that the data storage address has been filled in the first descriptor, and the programmable logic unit has not read the data stored in the data storage address locally, then the processor does not update the data storage address to be filled.

[0160] S707: Configure a second write pointer to instruct the processor to send the next first descriptor in the queue.

[0161] In the embodiment of the present disclosure, when the first usage flag indicates that the processor has not filled the data or the data has been read, the storage address of the data to be filled is updated to the first storage address corresponding to the first data in the data memory, and the second length of the data to be filled is updated to the first data length. After configuring the first usage flag to indicate that the processor has filled the data and the data is to be read, the second write pointer can be configured to indicate the next first descriptor in the processor sending queue, so that the processor can repeat the above data filling processing until the first descriptor in the processor sending queue is processed.

[0162] For example, Figure 8 As shown, Figure 8 It is a schematic diagram of the data sending process in the embodiment of the present disclosure, wherein BD represents the first descriptor in the processor sending queue. When the processor sends data, it can first perform an initialization operation. When the processor is initialized, all the processor sending queues BD are cleared, and the first read pointer controlled by the programmable logic unit and the second write pointer controlled by the CPU both point to BD Index 0 in the queue. All BDs in the processor receiving queue are filled with empty data buffers BUFFER, and the use flag Ready Flag in the descriptor is cleared. The first write pointer controlled by the programmable logic unit and the second read pointer controlled by the processor both point to BD Index 0 in the queue. When the processor sends data, the processor determines when sending that the first use flag in the first descriptor BD indicated by the current second write pointer is in the processor unfilled data or data has been read state, that is! READY state, then the items in the first descriptor BD can be filled (the BUFFER that has been sent needs to be recycled), the first usage flag READY FLAG is set, and finally the second write pointer is increased by 1, so that the second write pointer indicates the next first descriptor in the processor sending queue, until the data is sent, the processor determines that the current second write pointer BD is the processor has filled with data and the data is ready to be read, that is, the READY state, indicating that the processor sending queue BD ring is full and the sending is suspended, and the programmable logic unit can poll the doorbell message queue Doorbell to obtain the first message, or trigger the doorbell message queue Doorbell to send the first message Msg to the programmable logic unit, so that the programmable logic unit reads data according to the first descriptor in the processor sending queue, wherein the first message content is the network port number and interface type.

[0163] Then, the programmable logic unit polls the doorbell message queue Doorbell, obtains the first message from the doorbell message queue Doorbell, obtains the port number and the interface type from the first message, and then determines the first read pointer corresponding to the port number. The first read pointer indicates a first descriptor in the processor sending queue. If the first use flag in the first descriptor is in the READY state, the first use flag indicates that the processor has filled the data and the data is to be read. The processor can read the first data from the data memory based on the first storage address and the first data length in the first descriptor. The processor starts the DMA module to read the corresponding first data to the local, clears the READY state of the first use flag, and finally adds 1 to the first read pointer, and the first read pointer points to the next first descriptor. If the programmable logic unit determines that the current first read pointer BD is in the READY state, it means that the processor sending queue BD ring is completely empty, and the programmable logic unit suspends the data movement of this network port. Then the programmable logic unit polls the doorbell message queue Doorbell again to repeat the above data movement operation.

[0164] Among them, the READY state of the first use flag is the state where the CPU has filled in data and is waiting for FPGA to read. The READY state is the state where the CPU has not filled in data or the FPGA has completed reading. The first message carried by the doorbell message queue Doorbell is a 16-bit data message, which is divided into high 8 bits and low 8 bits. The high 8 bits are filled with the interface type (control, encryption and decryption, business), and the low 8 bits are filled with the port number.

[0165] In this embodiment, by determining a second write pointer, wherein the second write pointer is used to indicate a first descriptor in a processor sending queue corresponding to the interface type, the first descriptor includes: a storage address of data to be filled, a second length of data to be filled, and a first usage flag bit, if the first usage flag bit indicates that the processor has not filled the data or the data has been read, the storage address of the data to be filled is updated to the first storage address corresponding to the first data in the data memory, wherein the first data has a corresponding first data length, the second length of data to be filled is updated to the first data length, and the first usage flag bit is configured to indicate that the processor has filled the data and the data is to be read, and a first message is generated and provided according to the port number and interface type corresponding to the second write pointer, wherein the first message is used to indicate that the programmable logic unit is based on the first A data length and a first storage address are stored to read the first data from the data memory, which can realize lightweight data transmission and reception and efficient data transmission and reception communication. The memory overhead of data transmission and reception is small and the implementation is simple, which can effectively reduce the development cost and can be applied to low-load processors. It has a wide range of applications. By adding the first message to the doorbell message queue, the programmable logic unit can be reminded in time to read and move the data. When the first use flag indicates that the processor has filled the data and the data is to be read, the storage address of the data to be filled is not updated to ensure that the unread data is not overwritten and transmitted, thereby avoiding data loss. The second write pointer is configured to indicate the next first descriptor in the processor sending queue, thereby ensuring the completion of the traversal of the processor sending queue and ensuring the integrity of the data transmission.

[0166] Fig. 9 It is a flowchart of a data processing method proposed in another embodiment of the present disclosure.

[0167] like Fig. 9 As shown, the data processing method is executed by a processor and includes:

[0168] S901: Determine a second read pointer, wherein the second read pointer is used to indicate a second descriptor in a processor receiving queue, and the second descriptor includes: a second storage address, a first length of data to be filled, and a second use flag.

[0169] The second read pointer is used to indicate a second descriptor in the processor receiving queue, and the second descriptor includes: a second storage address, a first length of data to be filled, and a second use flag.

[0170] In the implementation of the present disclosure, a second read pointer can be determined, and the second read pointer indicates a second descriptor in the processor receiving queue. The second descriptor includes: a second storage address, a first data length to be filled, and a second usage flag. The second storage address is a pre-allocated address for storing data in a data memory. The second storage address is allocated a data buffer for storing data in the data memory. The first data length to be filled is a data length variable used to fill the data length. The second usage flag is used to indicate whether data is stored in the data memory buffer corresponding to the second storage address.

[0171] The second use flag can have two states: READY state and !READY state. The READY state is the state where the programmable logic unit is filled with data and the data is moved and waiting for the processor to receive it. The !READY state is the state where the processor has received the data and is waiting for the programmable logic unit to fill it with data.

[0172] S902: If the second usage flag indicates that the programmable logic unit has moved data and data is to be received, an empty buffer is allocated in the data memory for the second storage address.

[0173] In the disclosed embodiment, the second usage flag bit can be analyzed. If the second usage flag bit indicates that the programmable logic unit has moved data and data is to be received, an empty buffer can be allocated in the data memory for the second storage address to facilitate subsequent upper-layer applications to store data in the data memory corresponding to the second storage address.

[0174] S903: Set the length of the first data to be filled to 0, and configure the second use flag to indicate that the processor has completed receiving and the data is to be moved.

[0175] In the embodiment of the present disclosure, when the second usage flag indicates that the programmable logic unit has moved data and data is to be received, after allocating an empty buffer in the data memory for the second storage address, the length of the first data to be filled can be set to 0 accordingly, indicating that there is no data in the data memory corresponding to the second storage address, and the second usage flag is configured to indicate that the processor has completed reception and data is to be moved.

[0176] S904: If the second use flag indicates that the processor has completed receiving and the data is to be moved, no empty buffer is allocated in the data memory for the second storage address.

[0177] In the embodiment of the present disclosure, if the second use flag is in the READY state, it means that the processor has completed receiving and the data is to be moved, and no empty buffer is allocated in the data memory for the second storage address.

[0178] S905: Configure a second read pointer to instruct the processor to receive the next second descriptor in the queue.

[0179] In the embodiment of the present disclosure, after setting the length of the first data to be filled to 0 and configuring the second usage flag to indicate that the processor has completed receiving and the data is to be moved, the second read pointer can be configured to indicate the next second descriptor in the processor receive queue until the processor receive queue is processed.

[0180] In this embodiment, by determining a second read pointer, wherein the second read pointer is used to indicate a second descriptor in a processor receiving queue, the second descriptor includes: a second storage address, a first length of data to be filled, and a second usage flag. If the second usage flag indicates that the programmable logic unit has moved data and the data is to be received, an empty buffer is allocated in the data memory for the second storage address, the first length of data to be filled is set to 0, and the second usage flag is configured to indicate that the processor has completed reception and the data is to be moved. After the programmable logic unit has moved the data, a new buffer can be allocated in the data memory for the second storage address for subsequent data movement and transmission, thereby ensuring that there is corresponding movement and transmission space in the data memory and ensuring smooth subsequent data transmission.

[0181] For example, Fig.10 As shown, Fig.10 It is a schematic diagram of the data receiving process in the embodiment of the present disclosure. Before the programmable logic unit pushes data to the processor, it determines that the second descriptor BD pointed to by the current first write pointer is in the READY state, then the programmable logic unit starts data migration, and after the migration is completed, the second use flag is set to the READY state. Finally, the first write pointer is incremented by 1, so that the first write pointer points to the next second descriptor until the data is sent or the condition is met. The programmable logic unit determines that the second use flag of the second descriptor BD indicated by the current first write pointer is in the READY state, indicating that the processor receiving queue BD ring is full and the sending is suspended. The processor determines that the second use flag of the second descriptor BD indicated by the current second read pointer is in the READY state, allocates an empty buffer BUFFER to replace the full BUFFER, clears the READY state of the second use flag, and finally increments the second read pointer by 1, so that the second read pointer points to the next second descriptor BD. The loop is executed until the second read pointer is satisfied. The processor determines that the second use flag in the second descriptor BD pointed to by the current second read pointer is in the READY state, indicating that the BD ring of the processor receiving queue is full and the processor suspends receiving.

[0182] The READY state is a state where the programmable logic unit is filled with data and the data is moved and the processor is waiting to receive the data. The READY state is a state where the processor is receiving the data and the programmable logic unit is waiting to be filled with data.

[0183] In the disclosed embodiment, in view of the situation that the chip with limited processor resources cannot use the DPDK technology, a new memory management and data transmission and reception mechanism combining EOR and FPGA is adopted. The core principle of EOR technology is to create multiple queues composed of memory (executed by CPU), and each member in the queue points to a piece of data memory. The memory information in each queue can be accessed by CPU and DMA. CPU and DMA find the data memory location and data length information by accessing the queue member information of EOR, and complete the reading and writing of data, thereby achieving the reading and writing of data by the application layer and the entry and exit of data to the network board. It includes two important aspects: memory management and bidirectional data transmission and reception. The first is EOR multi-queue memory management, and the second is the data transmission and reception process between FPGA and CPU.

[0184] In the first process, EOR acts as a manager and creates multiple queues when the task starts. Each queue consists of multiple flags containing addresses pointing to data storage, data length, and whether the data is used. Multiple queues are grouped together to complete the reception and transmission of a data type. Since each soft core may correspond to multiple data types, each soft core will be bound to one or more groups of queues according to system requirements to ensure the flow of data of all types of services of each soft core between the CPU and FPGA.

[0185] In the second process, the CPU reads the member information in the receiving queue, finds the data memory and length information written by the local DMA controlled by the FPGA side, and delivers the data to the application layer to complete the data reception.

[0186] In the third process, the application layer controls the CPU to write data information into the data memory, and updates the address information, length information and usage flag in the sending queue, and sends a message to notify the FPGA to read the data. After the FPGA controls the local DMA to read the data, it will update the corresponding receiving queue node information to complete the data transmission.

[0187] The disclosed embodiment proposes a lightweight data transmission and reception implementation method, which reduces complexity through a customizable protocol stack. At the same time, due to the small memory overhead and simple implementation, it can effectively reduce development costs and be used in low-load servers. The amount of executed code is small, which is closer to the lightweight use requirements of satellite communications, effectively improves the processing performance of network data packets, and is widely used in the development of various network equipment.

[0188] Fig.11 It is a structural diagram of a data processing device proposed in an embodiment of the present disclosure.

[0189] like Fig.11 As shown, the data processing device 110, executed by a programmable logic unit, includes:

[0190] A first acquiring unit 1101 is configured to acquire a first message sent by a processor, wherein the first message includes: a port number and an interface type;

[0191] A first determining unit 1102 is used to determine a first read pointer corresponding to the port to which the port number belongs, wherein the first read pointer is used to indicate a first descriptor in a processor send queue corresponding to the interface type, and the first descriptor includes: a first storage address, a first data length, and a first use flag bit;

[0192] The second acquisition unit 1103 is configured to read first data from the data memory based on the first storage address and the first data length when the first usage flag indicates that the processor has filled the data and the data is to be read.

[0193] In some embodiments of the present disclosure, the device is also used to:

[0194] After reading the first data from the data memory based on the first storage address and the first data length, the first data is stored locally, and a first usage flag is configured to indicate that the data has been read.

[0195] In some embodiments of the present disclosure, the device is also used to:

[0196] The first read pointer is configured to instruct the processor to send the next first descriptor in the queue.

[0197] In some embodiments of the present disclosure, the device is also used to:

[0198] Determine a first write pointer, wherein the first write pointer is used to indicate a second descriptor in the processor receiving queue, and the second descriptor includes: a second storage address, a first length of data to be filled, and a second use flag;

[0199] If the second use flag indicates that the processor has completed receiving and the data is to be moved, then move the second data to the data memory corresponding to the second storage address, wherein the second data has a corresponding second data length;

[0200] The first data length to be filled is updated to the second data length, and the second use flag is configured to indicate that the programmable logic unit has moved the data and the data is to be received.

[0201] In some embodiments of the present disclosure, the device is also used to:

[0202] If the second use flag indicates that the programmable logic unit has moved data and data is to be received, the second data is not moved to the data memory.

[0203] In some embodiments of the present disclosure, the device is also used to:

[0204] The first write pointer is configured to instruct the processor to receive the next second descriptor in the queue.

[0205] In some embodiments of the present disclosure, the device is also used to:

[0206] At least one first message is polled and read from the doorbell message queue.

[0207] In this embodiment, by obtaining a first message sent by a processor, wherein the first message includes: a port number and an interface type, a first read pointer corresponding to the port to which the port number belongs is determined, wherein the first read pointer is used to indicate a first descriptor in a processor send queue corresponding to the interface type, and the first descriptor includes: a first storage address, a first data length, and a first usage flag. If the first usage flag indicates that the processor has filled data and the data is to be read, the first data is read from the data memory based on the first storage address and the first data length, thereby achieving lightweight data transmission and reception, and achieving efficient data transmission and reception communication. The memory overhead of data transmission and reception is small, and the implementation is simple, thereby effectively reducing the development cost, and can be applied to low-load processors, with a wide range of applications.

[0208] Fig.12 It is a structural diagram of a data processing device proposed in an embodiment of the present disclosure.

[0209] like Fig.12 As shown, the data processing device 120, executed by a processor, includes:

[0210] A second determining unit 1201 is used to determine a second write pointer, wherein the second write pointer is used to indicate a first descriptor in a processor send queue corresponding to the interface type, the first descriptor including: a storage address of data to be filled, a second length of data to be filled, and a first use flag;

[0211] A first updating unit 1202 is configured to update the storage address of the data to be filled to a first storage address corresponding to the first data in the data memory if the first use flag indicates that the processor has not filled the data or the data has been read, wherein the first data has a corresponding first data length;

[0212] A second updating unit 1203, configured to update the second to-be-filled data length to the first data length, and configure a first use flag to indicate that the processor has filled the data and the data is to be read;

[0213] The generating unit 1204 is used to generate and provide a first message according to the port number and interface type corresponding to the second write pointer, wherein the first message is used to instruct the programmable logic unit to read the first data from the data memory based on the first data length and the first storage address storage.

[0214] In some embodiments of the present disclosure, the device is also used to:

[0215] If the first use flag indicates that the processor has filled the data and the data is to be read, the storage address of the data to be filled is not updated.

[0216] In some embodiments of the present disclosure, the device is also used to:

[0217] The second write pointer is configured to instruct the processor to send the next first descriptor in the queue.

[0218] In some embodiments of the present disclosure, the device is also used to:

[0219] Determine a second read pointer, wherein the second read pointer is used to indicate a second descriptor in the processor receiving queue, the second descriptor including: a second storage address, a first length of data to be filled, and a second use flag;

[0220] If the second use flag indicates that the programmable logic unit has moved data and data is to be received, allocating an empty buffer in the data memory for the second storage address;

[0221] The length of the first data to be filled is set to 0, and the second use flag is configured to indicate that the processor has completed receiving and the data is to be moved.

[0222] In some embodiments of the present disclosure, the device is also used to:

[0223] If the second use flag indicates that the processor has completed receiving and data is to be moved, no empty buffer is allocated in the data memory for the second storage address.

[0224] In some embodiments of the present disclosure, the device is also used to:

[0225] The second read pointer is configured to instruct the processor to receive the next second descriptor in the queue.

[0226] In some embodiments of the present disclosure, it is characterized in that the device is also used for:

[0227] Add the first message to the doorbell message queue.

[0228] It should be noted that the division of units in the embodiments of the present disclosure is schematic and is only a logical function division. There may be other division methods in actual implementation. In addition, each functional unit in each embodiment of the present disclosure may be integrated into a processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0229] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a processor-readable storage medium.

[0230] Based on such understanding, the technical solution of the present disclosure, or the part that contributes to the prior art, or the whole or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to perform all or part of the steps of the various embodiments of the present disclosure. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc., various media that can store program codes.

[0231] It should be noted here that the above-mentioned device provided in the embodiment of the present disclosure can implement all the method steps implemented in the above-mentioned method embodiment, and can achieve the same technical effect. The parts and beneficial effects of this embodiment that are the same as those in the method embodiment will not be described in detail here.

[0232] In this embodiment, by determining a second write pointer, wherein the second write pointer is used to indicate a first descriptor in a processor sending queue corresponding to the interface type, the first descriptor includes: a storage address of data to be filled, a second data length to be filled, and a first usage flag. If the first usage flag indicates that the processor has not filled the data or the data has been read, the storage address of the data to be filled is updated to the first storage address corresponding to the first data in the data memory, wherein the first data has a corresponding first data length, the second data length to be filled is updated to the first data length, and the first usage flag is configured to indicate that the processor has filled the data and the data is to be read. According to the port number and interface type corresponding to the second write pointer, a first message is generated and provided, wherein the first message is used to instruct the programmable logic unit to read the first data from the data memory based on the first data length and the first storage address storage, thereby realizing lightweight data transmission and reception, realizing efficient data transmission and reception communication, the memory overhead of data transmission and reception is small, and the implementation is simple, thereby effectively reducing the development cost, and can be applied to low-load processors, with a high degree of application.

[0233] Fig.13 It is a structural diagram of a data processing device proposed in another embodiment of the present disclosure.

[0234] See also Fig.13The data processing device 130 includes a memory 1301, a transceiver 1302, a programmable logic unit 1303 and a user interface 1304: the memory 1301 is used to store computer programs; the transceiver 1302 is used to send and receive data under the control of the programmable logic unit 1303; the programmable logic unit 1303 is used to read the computer program in the memory 1301 and perform the following operations:

[0235] Acquire a first message sent by the processor, wherein the first message includes: a port number and an interface type;

[0236] Determine a first read pointer corresponding to the port to which the port number belongs, wherein the first read pointer is used to indicate a first descriptor in a processor send queue corresponding to the interface type, the first descriptor including: a first storage address, a first data length, and a first use flag;

[0237] If the first usage flag indicates that the processor has filled the data and the data is to be read, the first data is read from the data memory based on the first storage address and the first data length.

[0238] Among them, Fig.13 In the embodiment, the bus architecture may include any number of interconnected buses and bridges, specifically one or more processors represented by the programmable logic unit 1303 and various circuits of the memory represented by the memory 1301 are linked together. The bus architecture may also link together various other circuits such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and are therefore not further described herein. The bus interface provides an interface. The transceiver 1302 may be a plurality of components, namely, a transmitter and a receiver, providing a unit for communicating with various other devices on a transmission medium, which may include wireless channels, wired channels, optical cables, and other transmission media. For different user devices, the user interface 1304 may also be an interface capable of externally and internally connecting required devices, and the connected devices include but are not limited to a keypad, a display, a speaker, a microphone, a joystick, and the like.

[0239] The programmable logic unit 1303 is responsible for managing the bus architecture and general processing, and the memory 1301 can store data used by the processor 1303 when performing operations.

[0240] Optionally, the programmable logic unit 1303 may be a CPU (central processing unit), an ASIC (Application Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array) or a CPLD (Complex Programmable Logic Device), and the processor may also adopt a multi-core architecture.

[0241] The processor calls the computer program stored in the memory to execute any method provided by the embodiment of the present disclosure according to the obtained executable instructions. The processor and the memory can also be arranged physically separately.

[0242] In some embodiments of the present disclosure, the programmable logic unit 1303 is further configured to:

[0243] After reading the first data from the data memory based on the first storage address and the first data length, the first data is stored locally, and a first usage flag is configured to indicate that the data has been read.

[0244] In some embodiments of the present disclosure, the programmable logic unit 1303 is further configured to:

[0245] The first read pointer is configured to instruct the processor to send the next first descriptor in the queue.

[0246] In some embodiments of the present disclosure, the programmable logic unit 1303 is further configured to:

[0247] Determine a first write pointer, wherein the first write pointer is used to indicate a second descriptor in the processor receiving queue, and the second descriptor includes: a second storage address, a first length of data to be filled, and a second use flag;

[0248] If the second use flag indicates that the processor has completed receiving and the data is to be moved, then move the second data to the data memory corresponding to the second storage address, wherein the second data has a corresponding second data length;

[0249] The first data length to be filled is updated to the second data length, and the second use flag is configured to indicate that the programmable logic unit has moved the data and the data is to be received.

[0250] In some embodiments of the present disclosure, the programmable logic unit 1303 is further configured to:

[0251] If the second use flag indicates that the programmable logic unit has moved data and data is to be received, the second data is not moved to the data memory.

[0252] In some embodiments of the present disclosure, the programmable logic unit 1303 is further configured to:

[0253] The first write pointer is configured to instruct the processor to receive the next second descriptor in the queue.

[0254] In some embodiments of the present disclosure, the programmable logic unit 1303 is further configured to:

[0255] At least one first message is polled and read from the doorbell message queue.

[0256] In this embodiment, by obtaining a first message sent by a processor, wherein the first message includes: a port number and an interface type, a first read pointer corresponding to the port to which the port number belongs is determined, wherein the first read pointer is used to indicate a first descriptor in a processor send queue corresponding to the interface type, and the first descriptor includes: a first storage address, a first data length, and a first usage flag. If the first usage flag indicates that the processor has filled data and the data is to be read, the first data is read from the data memory based on the first storage address and the first data length, thereby achieving lightweight data transmission and reception, and achieving efficient data transmission and reception communication. The memory overhead of data transmission and reception is small, and the implementation is simple, thereby effectively reducing the development cost, and can be applied to low-load processors, with a wide range of applications.

[0257] Fig.14 It is a structural diagram of a data processing device proposed in another embodiment of the present disclosure.

[0258] See also Fig.14 The data processing device 140 includes a memory 1401, a transceiver 1402, a processor 1403 and a user interface 1404: the memory 1401 is used to store computer programs; the transceiver 1402 is used to send and receive data under the control of the processor 1403; the processor 1403 is used to read the computer program in the memory 1401 and perform the following operations:

[0259] Determine a second write pointer, wherein the second write pointer is used to indicate a first descriptor in a processor send queue corresponding to the interface type, the first descriptor including: a storage address of data to be filled, a second length of data to be filled, and a first use flag;

[0260] If the first use flag indicates that the processor has not filled the data or the data has been read, then updating the storage address of the data to be filled to a first storage address corresponding to the first data in the data memory, wherein the first data has a corresponding first data length;

[0261] Update the second to-be-filled data length to the first data length, and configure the first use flag to indicate that the processor has filled the data and the data is to be read;

[0262] A first message is generated and provided according to the port number and the interface type corresponding to the second write pointer, wherein the first message is used to instruct the programmable logic unit to read the first data from the data memory based on the first data length and the first storage address.

[0263] In some embodiments of the present disclosure, the processor 1403 is further configured to:

[0264] If the first use flag indicates that the processor has filled the data and the data is to be read, the storage address of the data to be filled is not updated.

[0265] In some embodiments of the present disclosure, the processor 1403 is further configured to:

[0266] The second write pointer is configured to instruct the processor to send the next first descriptor in the queue.

[0267] In some embodiments of the present disclosure, the processor 1403 is further configured to:

[0268] Determine a second read pointer, wherein the second read pointer is used to indicate a second descriptor in the processor receiving queue, the second descriptor including: a second storage address, a first length of data to be filled, and a second use flag;

[0269] If the second use flag indicates that the programmable logic unit has moved data and data is to be received, allocating an empty buffer in the data memory for the second storage address;

[0270] The length of the first data to be filled is set to 0, and the second use flag is configured to indicate that the processor has completed receiving and the data is to be moved.

[0271] In some embodiments of the present disclosure, the processor 1403 is further configured to:

[0272] If the second use flag indicates that the processor has completed receiving and data is to be moved, no empty buffer is allocated in the data memory for the second storage address.

[0273] In some embodiments of the present disclosure, the processor 1403 is further configured to:

[0274] The second read pointer is configured to instruct the processor to receive the next second descriptor in the queue.

[0275] In some embodiments of the present disclosure, the processor 1403 is further configured to:

[0276] Add the first message to the doorbell message queue.

[0277] In this embodiment, by determining a second write pointer, wherein the second write pointer is used to indicate a first descriptor in a processor sending queue corresponding to the interface type, the first descriptor includes: a storage address of data to be filled, a second data length to be filled, and a first usage flag. If the first usage flag indicates that the processor has not filled the data or the data has been read, the storage address of the data to be filled is updated to the first storage address corresponding to the first data in the data memory, wherein the first data has a corresponding first data length, the second data length to be filled is updated to the first data length, and the first usage flag is configured to indicate that the processor has filled the data and the data is to be read. According to the port number and interface type corresponding to the second write pointer, a first message is generated and provided, wherein the first message is used to instruct the programmable logic unit to read the first data from the data memory based on the first data length and the first storage address storage, thereby realizing lightweight data transmission and reception, realizing efficient data transmission and reception communication, the memory overhead of data transmission and reception is small, and the implementation is simple, thereby effectively reducing the development cost, and can be applied to low-load processors, with a high degree of application.

[0278] It should be noted here that the above-mentioned device provided in the embodiment of the present disclosure can implement all the method steps implemented in the above-mentioned method embodiment, and can achieve the same technical effect. The parts and beneficial effects of this embodiment that are the same as those in the method embodiment will not be described in detail here.

[0279] In order to implement the above-mentioned embodiment, the embodiment of the present disclosure proposes a processor-readable storage medium, wherein the processor-readable storage medium stores a computer program, and the computer program is used to enable the processor to execute a data processing method.

[0280] Those skilled in the art will appreciate that the embodiments of the present disclosure may be provided as methods, systems, or computer program products. Therefore, the present disclosure may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present disclosure may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) containing computer-usable program code.

[0281] The present disclosure is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present disclosure. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer executable instructions. These computer executable instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0282] These processor executable instructions may also be stored in a processor readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the processor readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0283] These processor-executable instructions may also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0284] Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

[0285] It should be noted that, in the description of the present disclosure, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present disclosure, unless otherwise specified, the meaning of "plurality" is two or more.

[0286] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present disclosure includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present disclosure belong.

[0287] It should be understood that the various parts of the present disclosure can be implemented in hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0288] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0289] In addition, each functional unit in each embodiment of the present disclosure may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0290] The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

[0291] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0292] Although the embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present disclosure. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present disclosure.

Claims

1. A data processing method, characterized in that: The method is executed by a programmable logic unit, and includes: Acquire a first message sent by the processor, wherein the first message includes: a port number and an interface type; Determine a first read pointer corresponding to the port to which the port number belongs, wherein the first read pointer is used to indicate a first descriptor in a processor send queue corresponding to the interface type, and the first descriptor includes: a first storage address, a first data length, and a first use flag; If the first usage flag indicates that the processor has filled the data and the data is to be read, the first data is read from the data memory based on the first storage address and the first data length.

2. The method according to claim 1, characterized in that After reading the first data from the data memory based on the first storage address and the first data length, the method further includes: The first data is stored locally, and the first usage flag is configured to indicate that the data has been read.

3. The method according to claim 2, characterized in that The method further comprises: The first read pointer is configured to indicate the processor to send the next first descriptor in the queue.

4. The method according to claim 1, characterized in that The method further comprises: Determine a first write pointer, wherein the first write pointer is used to indicate a second descriptor in the processor receiving queue, and the second descriptor includes: a second storage address, a first length of data to be filled, and a second use flag; If the second use flag indicates that the processor has completed receiving and data is to be moved, move the second data to the data memory corresponding to the second storage address, wherein the second data has a corresponding second data length; The first data length to be filled is updated to the second data length, and the second usage flag is configured to indicate that the programmable logic unit has moved data and data is to be received.

5. The method according to claim 4, characterized in that The method further comprises: If the second use flag indicates that the programmable logic unit has moved data and data is to be received, the second data is not moved to the data memory.

6. The method according to claim 4, characterized in that The method further comprises: The first write pointer is configured to indicate the next second descriptor in the processor receive queue.

7. The method according to any one of claims 1 to 6, characterized in that: The method further comprises: At least one of the first messages is read from the doorbell message queue in a polling manner.

8. A data processing method, characterized in that: The method is executed by a processor, comprising: Determine a second write pointer, wherein the second write pointer is used to indicate a first descriptor in a processor send queue corresponding to the interface type, the first descriptor including: a data storage address to be filled, a second data length to be filled, and a first use flag; If the first usage flag indicates that the processor has not filled data or the data has been read, then updating the storage address of the data to be filled to a first storage address corresponding to the first data in the data memory, wherein the first data has a corresponding first data length; Update the second to-be-filled data length to the first data length, and configure the first use flag to indicate that the processor has filled the data and the data is to be read; A first message is generated and provided according to the port number corresponding to the second write pointer and the interface type, wherein the first message is used to instruct the programmable logic unit to read the first data from the data memory based on the first data length and the first storage address storage.

9. The method according to claim 8, characterized in that The method further comprises: If the first use flag indicates that the processor has filled the data and the data is to be read, the storage address of the data to be filled is not updated.

10. The method according to claim 9, characterized in that The method further comprises: The second write pointer is configured to instruct the processor to send the next first descriptor in the queue.

11. The method according to claim 8, characterized in that The method further comprises: Determine a second read pointer, wherein the second read pointer is used to indicate a second descriptor in the processor receiving queue, the second descriptor comprising: a second storage address, a first length of data to be filled, and a second use flag; If the second usage flag indicates that the programmable logic unit has moved data and data is to be received, allocating an empty buffer in the data memory for the second storage address; The length of the first data to be filled is set to 0, and the second usage flag is configured to indicate that the processor has completed receiving and the data is to be moved.

12. The method according to claim 11, characterized in that The method further comprises: If the second use flag indicates that the processor has completed receiving and data is to be moved, no empty buffer is allocated in the data memory for the second storage address.

13. The method according to claim 11, characterized in that The method further comprises: The second read pointer is configured to indicate the processor to receive a next second descriptor in the queue.

14. The method according to any one of claims 8 to 13, characterized in that: The method further comprises: The first message is added to the doorbell message queue.

15. A data processing device, characterized in that: The device is executed by a programmable logic unit, and the device includes: A first acquiring unit, configured to acquire a first message sent by the processor, wherein the first message includes: a port number and an interface type; A first determining unit, configured to determine a first read pointer corresponding to the port to which the port number belongs, wherein the first read pointer is used to indicate a first descriptor in a processor send queue corresponding to the interface type, the first descriptor comprising: a first storage address, a first data length, and a first use flag; The second acquisition unit is used to read the first data from the data memory based on the first storage address and the first data length when the first usage flag indicates that the processor has filled the data and the data is to be read.

16. A data processing device, characterized in that: The device is executed by a processor, and includes: A second determining unit is used to determine a second write pointer, wherein the second write pointer is used to indicate a first descriptor in a processor send queue corresponding to the interface type, and the first descriptor includes: a data storage address to be filled, a second data length to be filled, and a first use flag; A first updating unit, configured to update the storage address of the data to be filled to a first storage address corresponding to the first data in the data memory if the first use flag indicates that the processor has not filled the data or the data has been read, wherein the first data has a corresponding first data length; A second updating unit, configured to update the second to-be-filled data length to the first data length, and configure the first use flag to indicate that the processor has filled the data and the data is to be read; A generating unit is used to generate and provide a first message according to a port number corresponding to the second write pointer and the interface type, wherein the first message is used to instruct a programmable logic unit to read the first data from the data memory based on the first data length and the first storage address storage.

17. A data processing device, characterized in that: It includes memory, transceiver, and programmable logic unit: memory is used to store computer programs; a transceiver, for transmitting and receiving data under the control of the programmable logic unit; A programmable logic unit is used to read the computer program in the memory and perform the following operations: Acquire a first message sent by the processor, wherein the first message includes: a port number and an interface type; Determine a first read pointer corresponding to the port to which the port number belongs, wherein the first read pointer is used to indicate a first descriptor in a processor send queue corresponding to the interface type, and the first descriptor includes: a first storage address, a first data length, and a first use flag; If the first usage flag indicates that the processor has filled the data and the data is to be read, the first data is read from the data memory based on the first storage address and the first data length.

18. The device according to claim 17, characterized in that The programmable logic unit is also used for: After reading the first data from the data memory based on the first storage address and the first data length, the first data is stored locally, and the first usage flag is configured to indicate that the data has been read.

19. The device according to claim 18, characterized in that The programmable logic unit is also used for: The first read pointer is configured to indicate the processor to send the next first descriptor in the queue.

20. The device according to claim 17, characterized in that The programmable logic unit is also used for: Determine a first write pointer, wherein the first write pointer is used to indicate a second descriptor in the processor receiving queue, and the second descriptor includes: a second storage address, a first length of data to be filled, and a second use flag; If the second use flag indicates that the processor has completed receiving and data is to be moved, move the second data to the data memory corresponding to the second storage address, wherein the second data has a corresponding second data length; The first data length to be filled is updated to the second data length, and the second usage flag is configured to indicate that the programmable logic unit has moved data and data is to be received.

21. The device according to claim 20, characterized in that The programmable logic unit is also used for: If the second use flag indicates that the programmable logic unit has moved data and data is to be received, the second data is not moved to the data memory.

22. The device according to claim 20, characterized in that The programmable logic unit is also used for: The first write pointer is configured to indicate the next second descriptor in the processor receive queue.

23. The device according to any one of claims 17 to 22, characterized in that The programmable logic unit is also used for: At least one of the first messages is read from the doorbell message queue in a polling manner.

24. A data processing device, characterized in that: It includes memory, transceiver and processor: memory is used to store computer programs; a transceiver, configured to transmit and receive data under the control of the processor; and a processor, configured to read the computer program in the memory and perform the following operations: Determine a second write pointer, wherein the second write pointer is used to indicate a first descriptor in a processor send queue corresponding to the interface type, the first descriptor including: a data storage address to be filled, a second data length to be filled, and a first use flag; If the first usage flag indicates that the processor has not filled data or the data has been read, then updating the storage address of the data to be filled to a first storage address corresponding to the first data in the data memory, wherein the first data has a corresponding first data length; Update the second to-be-filled data length to the first data length, and configure the first use flag to indicate that the processor has filled the data and the data is to be read; A first message is generated and provided according to the port number corresponding to the second write pointer and the interface type, wherein the first message is used to instruct the programmable logic unit to read the first data from the data memory based on the first data length and the first storage address storage.

25. The device according to claim 24, characterized in that The processor is further configured to: If the first use flag indicates that the processor has filled the data and the data is to be read, the storage address of the data to be filled is not updated.

26. The device according to claim 25, characterized in that The processor is further configured to: The second write pointer is configured to instruct the processor to send the next first descriptor in the queue.

27. The device according to claim 24, characterized in that The processor is further configured to: Determine a second read pointer, wherein the second read pointer is used to indicate a second descriptor in the processor receiving queue, the second descriptor comprising: a second storage address, a first length of data to be filled, and a second use flag; If the second usage flag indicates that the programmable logic unit has moved data and data is to be received, allocating an empty buffer in the data memory for the second storage address; The length of the first data to be filled is set to 0, and the second usage flag is configured to indicate that the processor has completed receiving and the data is to be moved.

28. The device according to claim 27, characterized in that The processor is further configured to: If the second use flag indicates that the processor has completed receiving and data is to be moved, no empty buffer is allocated in the data memory for the second storage address.

29. The device according to claim 28, characterized in that The processor is further configured to: The second read pointer is configured to indicate the processor to receive a next second descriptor in the queue.

30. The device according to any one of claims 24 to 29, characterized in that The processor is further configured to: The first message is added to the doorbell message queue.

31. A processor-readable storage medium, characterized in that: The processor-readable storage medium stores a computer program, and the computer program is used to enable the processor to execute the data processing method described in any one of claims 1 to 7, or to enable the processor to execute the data processing method described in any one of claims 8 to 14.

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