Semiconductor test method
By processing the number of instruction cycles of the test vector during the compilation process, and using the SIMD instruction set and multi -threaded processing technology, the ATE device consumes long and low efficiency when processing AFM data, and achieves faster data reduction and more High resource utilization.
Patent Information
- Application Number
- CN202411527518.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-30
- Publication Date
- 2025-01-28
AI Technical Summary
In the prior art, when ATE devices process large amounts of AFM data, analysis and restoration take a long time, inefficient efficiency, and insufficient parallelism between I/O operations and CPU, resulting in a decrease in overall processing speed.
By determining whether the number of instruction cycles in the test vector during the compilation process is fixed, and the non -fixed instructions are recorded as a fixed number; only the storage results are marked as a failed data; The corresponding number of threads are allocated.
The analysis of any fragment offset in the test vector has significantly improved the data reduction speed, reduced the time consumption of AFM data analysis and reduction, and optimized the parallelism of the CPU and IO tasks, and improved the overall resource utilization rate.
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Figure CN119377026A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of integrated circuit automatic testing equipment, and in particular to a semiconductor testing method. Background Art
[0002] In the process of using ATE equipment to perform quality control tests on a batch of memory chips, there are currently multiple designs for AFM (Automatic Fault Memory) data analysis and restoration in the industry, with two main typical layouts:
[0003] 1. Use specialized hardware boards to calculate and restore AFM data, and the test HOST (computer system that controls the test process) interacts with these hardware boards.
[0004] 2. Use a dedicated workstation to perform calculations and restore tasks. The test HOST also needs to interact with the workstation.
[0005] Generally speaking, the processing steps are as follows: a. The test HOST sends the test vectors to the digital board, which stimulates the chip according to these test vectors and starts the test process. The chip's feedback data is compared with the expected response, and any data that does not meet expectations will be recorded in real time and sent to the analysis and restoration device; b. After the test is completed, the test HOST retrieves the processed data from the analysis and restoration device through the interface provided by the SDK (Software Development Kit).
[0006] In general schemes, the number of cycles (instruction cycles) generated after each test vector is executed is not fixed, which means that the length of each part of the data may be different. The number of cycles must be parsed and restored from the beginning each time, and arbitrary fragment restoration is not supported. At the same time, there are performance bottlenecks, especially when the parallelism of I / O (input / output) operations and CPU (central processing unit) is not enough. I / O tasks are usually slower than CPU tasks because it involves the transmission of data, which can lead to a decrease in overall processing speed. When the CPU needs to wait for I / O operations to complete before continuing processing, the CPU utilization rate will decrease, affecting the overall efficiency. Summary of the invention
[0007] The object of the present invention is to provide a semiconductor testing method, which can solve the problem of long analysis and restoration time and low efficiency when ATE equipment processes a large amount of AFM data in the prior art.
[0008] To achieve the above object, the present invention provides a semiconductor testing method, comprising the following steps:
[0009] During compilation, determine whether the number of instruction cycles in the test vector is fixed;
[0010] If there are instructions with non-fixed cycle numbers in the test vector, the instructions with non-fixed cycle numbers are recorded according to a fixed number of times.
[0011] Furthermore, in the semiconductor testing method, the determination of whether the number of instruction cycles in the test vector is fixed includes compiling the original text through a compiler to generate binary data, and loading it to a lower-level hardware board, and then the hardware board executes each instruction one by one in sequence.
[0012] Furthermore, in the semiconductor testing method, when each instruction is executed one by one, an input signal is applied to the chip, and an expected value is set for the obtained output signal.
[0013] Furthermore, in the semiconductor testing method, if the collected output value meets the expected value, the result of the cycle is marked as passed; if not, the result is marked as failed.
[0014] Furthermore, in the semiconductor testing method, only the data marked as failed is stored in the DDR as the test result data.
[0015] Furthermore, in the semiconductor testing method, the test result data includes cycle data, a tag index and a comparison value.
[0016] Furthermore, in the semiconductor testing method, the test results in the DDR are taken out, and the test result data is divided into a plurality of sub-data sets, and a corresponding number of threads are created according to the number of processor cores available in the system, and then tasks are assigned to each thread.
[0017] Furthermore, in the semiconductor testing method, each thread independently performs computing tasks on its own data set, and each thread uses a SIMD instruction set to perform parallel processing on the processed data.
[0018] Compared with the prior art, the present invention has at least the following technical effects:
[0019] A semiconductor testing method provided by the present invention can simplify the analysis of any fragment offset in a test vector by recording instructions with variable cycle numbers according to fixed times, thereby greatly improving the restoration speed and reducing the time consumption of AFM data analysis and restoration. In addition, by storing only data marked as failed results in DDR, the demand for data storage can be reduced and the efficiency of data processing can be improved.
[0020] Furthermore, by using the SIMD instruction set to process the processed data in parallel, more data can be calculated within the same number of instruction cycles, which can reduce the calculation time by multiples and significantly improve the data processing speed. In addition, by creating a number of threads that matches the number of processor cores and performing task allocation, the parallelism of CPU and IO tasks can be optimized, reducing the situation where the CPU waits for IO, thereby improving the overall utilization of system resources. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Figure 1 is a flow chart of a semiconductor testing method according to an embodiment of the present invention;
[0022] Figure 2 A schematic diagram of serial processing of I / O and CPU tasks in one embodiment of the present invention;
[0023] Figure 3 A schematic diagram of a thread pool, I / O and CPU in a semiconductor testing method according to an embodiment of the present invention;
[0024] Figure 4 Schematic diagram of a thread pool in a semiconductor testing method in one embodiment of the present invention processing I / O and CPU tasks in parallel. DETAILED DESCRIPTION
[0025] A semiconductor testing method of the present invention will be described in more detail below in conjunction with a schematic diagram, wherein a preferred embodiment of the present invention is shown, and it should be understood that those skilled in the art may modify the present invention described herein while still achieving the beneficial effects of the present invention. Therefore, the following description should be understood as being widely known to those skilled in the art and not as a limitation of the present invention.
[0026] For the sake of clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not described in detail because they would clutter the invention with unnecessary detail. It should be recognized that in the development of any actual embodiment, a large number of implementation details must be made to achieve the developer's specific goals, such as changing from one embodiment to another according to the limitations of the relevant system or the relevant business. In addition, it should be recognized that such development work may be complex and time-consuming, but it is just a routine task for those skilled in the art.
[0027] The present invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present invention will become more apparent from the following description and claims. It should be noted that the drawings are in very simplified form and in non-precise proportions, and are only used to facilitate and clearly assist in illustrating the purpose of the embodiments of the present invention.
[0028] As mentioned in the background technology, in the prior art, the number of instruction cycles generated after the test vector is executed is not fixed, and the prior art does not support the rapid restoration of any fragment of data, which limits the flexibility of data processing and increases the complexity of data processing and analysis. Figure 2 As shown in Figure 1, due to the slow nature of I / O tasks, the CPU needs to wait for the I / O operation to complete before continuing processing, which reduces CPU utilization and affects overall efficiency.
[0029] In view of this, if Figure 1 As shown, the present invention provides a semiconductor testing method to solve the above problems. Specifically, the method comprises the following steps:
[0030] During compilation, determine whether the number of instruction cycles in the test vector is fixed;
[0031] If there are instructions with non-fixed cycle numbers in the test vector, the instructions with non-fixed cycle numbers are recorded according to a fixed number of times.
[0032] Specifically, in semiconductor testing, a test vector is a set of predefined instructions and data used to test the functionality and performance of a specific chip or circuit. Each instruction may require multiple cycles (or clock cycles) to complete when executed. A cycle refers to the time required to complete a basic operation, such as a simple logic gate operation or data transfer. Among them, some instructions may require a fixed number of cycles when executed (for example, a static instruction may always require one cycle), while other instructions (dynamic instructions) may require a number of cycles that vary depending on the specific circumstances during the test, for example, depending on the size of the data or the complexity of the operation. During the compilation process, the compiler needs to check each instruction and determine whether the number of cycles required for its execution is fixed. This is to accurately track and process the execution of each instruction in subsequent test execution and result analysis.
[0033] In the present embodiment, for those instructions with unfixed cycle numbers, the compiler needs to adopt a strategy to handle them, so that these instructions can be consistently quoted when the test is executed and the result is analyzed. Therefore, the method proposed in the present invention is to uniformly record these unfixed cycle instructions according to a fixed cycle number, thereby simplifying subsequent data processing and analysis process. In this way, the offset of any fragment in the whole test vector can be calculated by parsing the structure of the test vector, without the need to parse the whole test vector from the beginning every time.
[0034] For example, the following Table 1 shows the original text of the example, which has a total of 10 instructions, and the total number of execution cycles is uncertain. Among them, the STATIC instruction indicates that the execution is fixed for 1 cycle, the DYNAMIC instruction indicates that the execution is uncertain, the MARK or LOOP instruction indicates a loop instruction, and the DONE instruction indicates an end instruction.
[0035] Table 1
[0036] Line Number instruction Input signal Expected Value 0 STATIC 1 H 1 DYNAMIC,4 0 L 2 STATIC 1 H 3 label STATIC 0 L 4 DYNAMIC,5 1 H 5 STATIC 0 L 6 DYNAMIC,6 0 H 7 LOOP label, 1 1 H 8 STATIC 0 L 9 DONE 0 L
[0037] In this embodiment, the determination of whether the number of instruction cycles in the test vector is fixed includes compiling the original text through a compiler to generate binary data, and loading it to the lower hardware board, and then the hardware board executes each instruction one by one according to the test vector sequence. When executing each instruction one by one, an input signal is applied to the chip, and an expected value is set for the obtained output signal. If the collected output value meets the expected value, the result of the cycle is marked as pass (Pass); if not, the result is marked as fail (Fail).
[0038] It should be noted that only the data marked as failed is stored in the DDR (dynamic random access memory) as the test result data. Storing only failed data means that the amount of data stored in the DDR will be greatly reduced, which can reduce the storage space occupied and improve the efficiency of data processing. Moreover, focusing only on failed data can locate the problem more quickly. In addition, in the subsequent data analysis and restoration process, since the amount of data to be processed is reduced, the processing time can be significantly reduced, speeding up the entire process.
[0039] The test result data stored in the DDR includes cycle data (expressed as cycle), mark index (expressed as cycle_ext) and comparison value (expressed as compare-values). For example, the following is a possible DDR data list as shown in Table 2:
[0040] Table 2
[0041] cycle cycle_ext compare-values 1 1 0x1 3 3 0x2 5 5 0x1 7 7 0x1 8 7 0x1 9 7 0x2 13 10 0x2
[0042] The cycle data refers to the unique identifier of each test cycle, which is used to track each specific step in the test process; the tag index is used to identify the location of specific instructions or data in the test vector, which is convenient for quickly locating the relevant part of the test vector during analysis; the comparison value represents the comparison between the expected result and the actual result, which is used to determine whether the test is successful. In addition, the comparison value can quickly identify the cause of the test failure, speeding up the problem location and repair process. Therefore, storing and analyzing the test results in this way makes fault diagnosis more accurate and efficient.
[0043] In this embodiment, the instructions in the original text need to be parsed into a compressed node list (CompressNodeList), each compressed node contains cycle_ext (used to indicate the tag index), len (used to indicate the cycle length, which is 1 for non-loop instructions) and cycle (used to indicate the actual number of cycles, which is unknown in the initial state). For example, based on the provided original text, create the following compressed node list:
[0044] [cycle_ext=1,len=1,cycle=? ]
[0045] [cycle_ext=2,len=? ,cycle=? ]
[0046] [cycle_ext=3,len=2,cycle=? ]
[0047] [cycle_ext=5,len=? ,cycle=? ]
[0048] [cycle_ext=6,len=1,cycle=? ]
[0049] [cycle_ext=7,len=? ,cycle=? ]
[0050] [cycle_ext=8,len=3,cycle=? ]
[0051] In this embodiment, the board DDR data is obtained through the network, and these data are loaded into the memory to form a DDR data list. A parsed data list (FailedDataList) is created, which contains cycle data that failed the test, and the data can be queried by the actual number of cycles or the tag index. After taking out the test result data from the DDR, the data set of the test result is divided into multiple sub-data sets according to the number of processor cores available in the system, and a corresponding number of threads are created according to the number of processor cores available in the system, and then tasks are assigned to each thread. Each thread is responsible for processing one or more sub-data sets, that is, each sub-data set is assigned to one or more threads for processing, thereby realizing parallel computing. In this step, each thread independently performs computing tasks on its own data set, and each thread uses the SIMD (Single Instruction Multiple Data, single instruction multiple data stream) instruction set to accelerate the calculation of processing data. Among them, the SIMD instruction set allows a single instruction to perform the same operation on multiple data at the same time. The SIMD instruction set can significantly improve the throughput of data processing, especially when processing a large number of similar calculations, such as graphics processing, signal processing and other fields. Parallel processing reduces the overall computing time, makes the analysis and restoration of test results faster, and improves the overall test efficiency. Therefore, each thread independently performs computing tasks on its own data set. Using the SIMD instruction set within each thread to perform parallel processing on the processed data can reduce the overall computing time, making the analysis and restoration of test results faster, thereby improving the overall test efficiency.
[0052] Specifically, when a single data set is very large, it is difficult to process it efficiently on limited computing resources, so it needs to be divided into multiple smaller sub-datasets. When dividing a data set, it can be done according to rules such as data volume balance (ensuring that each sub-dataset is roughly the same size) and data relevance (keeping logically related data together). Then, according to the number of processor cores available in the system, create a corresponding number of threads. Threads are independent streams of program execution that can process data in parallel. Each thread is assigned one or more sub-datasets for processing. There are two possible allocation methods here: uniform allocation and non-uniform allocation. Uniform allocation: If the number of sub-datasets is equal to the number of threads, each thread processes one sub-dataset; non-uniform allocation: If the number of sub-datasets is more than the number of threads, each thread processes multiple sub-datasets.
[0053] In this embodiment, if Figure 3As shown in the figure, separate I / O task queues (IO work queue) and CPU task queues (CPU work queue) are designed. Each IO work queue has multiple IO tasks, and each CPU work queue has multiple CPU tasks. Create a task thread pool (Thread pool), as shown in the figure. Figure 4 As shown, tasks are obtained and executed in parallel from the I / O or CPU queue through the task thread pool. Each thread works independently and analyzes its assigned sub-data set, so that multiple computing tasks can be performed simultaneously to improve the overall computing efficiency. At the same time, each thread uses the SIMD (Single Instruction Multiple Data) instruction set to accelerate the calculation of data with similar calculation steps and weak correlation between different data sources. Among them, using the SIMD instruction set, threads can process data in parallel, that is, complete operations on multiple data in a single CPU instruction cycle, rather than sequentially.
[0054] In this embodiment, the data in FailedDataList is mapped to the corresponding compression node by marking the index, and the cycle data value of each node is updated to the number of cycles actually executed. For each compression node, the cycle data range that needs to be restored is determined according to its len attribute, and data restoration is performed in the corresponding thread. The compression nodes are grouped, and internal restoration work without cycle data is performed in different threads. For each compression node, the corresponding failure data is extracted from the DDR data according to its len and cycle attributes, and restoration analysis is performed to determine the specific cause of the test failure. Afterwards, the data restoration results of all threads are integrated to form a complete test result report.
[0055] In this embodiment, after completing its own task, each thread synchronizes part of the intermediate results or the final results to the shared storage area; synchronization mechanisms such as mutex locks and semaphores are used to ensure data consistency; the calculation results of all threads are aggregated to form a complete processing result.
[0056] In this embodiment, the algorithm needs to be further optimized according to specific data characteristics and computing requirements, for example, by adjusting the data layout to reduce cache misses, by algorithm pruning to remove unnecessary computing steps, or by adaptively upgrading or downgrading the algorithm to meet data processing requirements of different scales.
[0057] In summary, in a semiconductor testing method provided by an embodiment of the present invention, by recording instructions with variable cycle numbers according to fixed times, the analysis of any fragment offset in the test vector can be simplified, thereby greatly improving the restoration speed and reducing the time consumption of AFM data analysis and restoration. In addition, by only storing data marked as failed results in DDR, the demand for data storage can be reduced and the efficiency of data processing can be improved.
[0058] Furthermore, by using the SIMD instruction set to process the processed data in parallel, more data can be calculated within the same number of instruction cycles, which can reduce the calculation time by multiples and significantly improve the data processing speed. In addition, by creating a number of threads that matches the number of processor cores and performing task allocation, the parallelism of CPU and IO tasks can be optimized, reducing the situation where the CPU waits for IO, thereby improving the overall utilization of system resources.
[0059] The above is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the content of the technical solution of the present invention and still falls within the protection scope of the present invention.
Claims
1. A semiconductor testing method, characterized in that: The following steps are involved: During compilation, determine whether the number of instruction cycles in the test vector is fixed; If there are instructions with non-fixed cycle numbers in the test vector, the instructions with non-fixed cycle numbers are recorded according to a fixed number of times.
2. The semiconductor testing method according to claim 1, characterized in that: The determining whether the number of instruction cycles in the test vector is fixed includes compiling the original text through a compiler to generate binary data, and loading it to a lower hardware board, and then the hardware board executes each instruction one by one in sequence.
3. The semiconductor testing method according to claim 2, characterized in that: As each instruction is executed, input signals are applied to the chip and expected values are set for the resulting output signals.
4. The semiconductor testing method according to claim 3, characterized in that: If the collected output value meets the expected value, the result of the cycle is marked as passed; if not, the result is marked as failed.
5. The semiconductor testing method according to claim 4, characterized in that: Only the data whose results are marked as failed is stored in the DDR as the test result data.
6. The semiconductor testing method according to claim 5, characterized in that: The test result data includes period data, a tag index and a comparison value.
7. The semiconductor testing method according to claim 6, characterized in that: The test results in the DDR are retrieved, and the test result data is divided into a plurality of sub-data sets, and a corresponding number of threads are created according to the number of processor cores available in the system, and then tasks are assigned to each thread.
8. The semiconductor testing method according to claim 7, characterized in that: Each thread independently performs computing tasks on its own data set, and each thread uses the SIMD instruction set to process the processed data in parallel.