Task execution method and device, storage medium and electronic equipment

Abstract

The invention discloses a task execution method and device, a storage medium and electronic equipment, and the method specifically comprises the steps: for each target chip, carrying out the parameter configuration of the parameters of the target chip during the execution of a model training task according to the chip information and the model data of a target model. And executing a model training task through the configured target chip, collecting model training log data, and determining a performance evaluation value of the target chip. And determining an adaptive target chip according to the performance evaluation value of each target chip, and executing the target task through the adaptive target chip. By means of the method, the performance evaluation efficiency of the heterogeneous chips can be effectively improved, the evaluation modes of the heterogeneous chips are more accurate and consistent, the performance difference between the heterogeneous chips is more visual, the optimal adaptive chip determination efficiency is improved, meanwhile, the optimal adaptive chip determination efficiency is improved, and meanwhile the optimal adaptive chip determination efficiency is improved. And more practical theoretical basis and help are provided for selecting more suitable application chips for model training.

Description

Technical Field

[0001] The present invention relates to the field of smart chips, and in particular to a task execution method, device, storage medium and electronic device. Background Art

[0002] With the continuous development and progress of science and technology, smart chips and smart models have become the top priority for the future development of various technical fields. The widespread application and popularization of smart chips equipped with smart models have provided great help and convenience for people's daily life and the design and development of high-tech.

[0003] In today's smart chip field, different chip developers may have different internal structures for the same type of smart chip. For example, for the Graphics Processing Unit (GPU), GPU chips produced by chip developers such as NVIDIA, AMD, and Moore's Law have their own unique structures and usage methods, and different chip structures often determine the chip performance and the degree of adaptation to the model. The training process of the smart model is almost inseparable from the support and support of the smart chip. Therefore, how to choose a more suitable and more powerful chip as the carrier when training the smart model is extremely important in the field of model research and development.

[0004] At present, the performance evaluation of a large number of heterogeneous smart chips (such as H100, A100, MI300, MI250, MTT S4000, etc.) is mostly done by manually configuring parameters according to different chip models and architectures, such as setting different batch sizes, memory allocations, parallel computing strategies, etc. according to the chip structure. This method is extremely time-consuming and labor-intensive, and cannot guarantee the effective alignment of performance data between chips in the end, making the performance gap between smart chips more vague and less accurate, and cannot provide a highly practical selection basis for chip selection during model training.

[0005] Therefore, how to accurately evaluate the chip performance of heterogeneous smart chips efficiently is a crucial issue. Summary of the invention

[0006] This specification provides a task execution method, device, storage medium and electronic device to partially solve the above-mentioned problems existing in the prior art.

[0007] This manual adopts the following technical solutions: This specification provides a task execution method, including: Obtain chip information corresponding to each target chip to be evaluated, wherein each target chip is a chip with the same function, but the internal chip architectures of each target chip are not completely the same; For each target chip, according to the chip information corresponding to the target chip and the model data corresponding to the preset target model, the execution parameters required for the target chip to execute the model training task corresponding to the target model are configured to obtain the configured target chip, and the model training task is executed by the configured target chip to collect the model training log data corresponding to the target chip during the execution of the model training task; For each target chip, determine at least one performance evaluation value corresponding to the target chip according to the model training log data corresponding to the target chip; According to at least one performance evaluation value corresponding to each target chip, an adapted target chip corresponding to the target model is determined from the target chips, and the target task corresponding to the target model is executed by the adapted target chip.

[0008] Optionally, for each target chip, the chip information corresponding to the target chip at least includes a chip model identifier corresponding to the target chip; For each target chip, according to the chip information corresponding to the target chip and the model data corresponding to the preset target model, the execution parameters required for the target chip to execute the model training task corresponding to the target model are configured to obtain the configured target chip, specifically including: Determine, according to the model data corresponding to the target model, a parameter configuration data set corresponding to the target model, wherein the parameter configuration data set is preset with parameter configuration data corresponding to execution parameters required for each target chip to perform a model training task corresponding to the target model; For each target chip, according to the chip model identifier in the chip information corresponding to the target chip, the parameter configuration data corresponding to the target chip is matched from the parameter configuration data set, and the parameter configuration data corresponding to the target chip at least includes a model training framework preset for the target chip, training hyperparameters, container parameters, and model parameter data corresponding to the target model; According to the parameter configuration data corresponding to the target chip, the execution parameters required for the target chip to execute the model training task corresponding to the target model are configured to obtain the configured target chip.

[0009] Optionally, during the execution of the model training task, model training log data corresponding to the target chip is collected, specifically including: For each target chip, during the execution of the model training task by the configured target chip, resource occupancy log data and task execution log data corresponding to the target chip are collected at preset time intervals; for each time point divided according to the time interval, the resource occupancy log data collected at the time point at least includes the chip memory usage rate, CPU occupancy rate, chip power consumption and memory usage rate of the target chip at the time point; the task execution log data collected at the time point at least includes the number of floating-point operations, data processing volume, model training loss and task execution accuracy of the target chip at the time point; The model training log data corresponding to the target chip is determined based on the resource occupancy log data and task execution log data corresponding to the target chip at each time point, as well as the task execution time of the target chip executing the model training task.

[0010] Optionally, determining at least one performance evaluation value corresponding to the target chip according to the model training log data corresponding to the target chip specifically includes: For each target chip, according to the model training log data corresponding to the target chip and the preset performance evaluation rules, the chip performance data corresponding to the target chip is generated, wherein the chip performance data at least includes the chip computing power data, chip throughput and chip acceleration ratio corresponding to the target chip; According to the model training log data and chip performance data corresponding to the target chip, at least one performance evaluation value of the target chip corresponding to each performance evaluation dimension preset for each target chip is determined.

[0011] Optionally, determining an adapted target chip corresponding to the target model from the target chips according to at least one performance evaluation value corresponding to the target chips specifically includes: Generating a comprehensive performance comparison result for each target chip according to at least one performance evaluation value corresponding to each target chip; According to the comprehensive performance comparison result, the adapted target chip corresponding to the target model is determined from the target chips.

[0012] Optionally, according to the comprehensive performance comparison result, determining the adapted target chip corresponding to the target model from the target chips specifically includes: For each target chip, determining a model adaptation degree value between the target chip and the target model according to the comprehensive performance comparison result; At least one adapted target chip corresponding to the target model is determined from the target chips according to the model adaptation degree values ​​corresponding to the target chips.

[0013] Optionally, the method further includes: For each target chip, according to the comprehensive performance comparison result, a performance problem detection is performed on the target chip to obtain a performance problem detection result corresponding to the target chip; Based on the performance problem detection results corresponding to the target chip, performance optimization strategy information for the target chip is generated, and the performance optimization strategy information of the target chip is sent to the terminal device used by the developer corresponding to the target chip, so that the developer corresponding to the target chip can optimize the performance of the target chip according to the performance optimization strategy information of the target chip.

[0014] This specification provides a task execution device, including: An acquisition module, used for acquiring chip information corresponding to each target chip to be evaluated, wherein each target chip is a chip with the same function, but the internal chip architecture of each target chip is not completely the same; A training module is used to configure, for each target chip, execution parameters required for the target chip to execute the model training task corresponding to the target model according to the chip information corresponding to the target chip and the model data corresponding to the preset target model, obtain the configured target chip, and execute the model training task through the configured target chip to collect the model training log data corresponding to the target chip during the execution of the model training task; An evaluation module, configured to determine, for each target chip, at least one performance evaluation value corresponding to the target chip according to the model training log data corresponding to the target chip; The determination module is used to determine the adapted target chip corresponding to the target model from the target chips according to at least one performance evaluation value corresponding to each target chip, and execute the target task corresponding to the target model through the adapted target chip.

[0015] This specification provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the above-mentioned task execution method is implemented.

[0016] This specification provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the above-mentioned task execution method when executing the program.

[0017] At least one of the above technical solutions adopted in this specification can achieve the following beneficial effects: It can be seen from the above method that in the task execution method provided in this specification, for each target chip, according to the chip information corresponding to the target chip and the model data corresponding to the preset target model, the execution parameters required for the target chip to execute the model training task can be configured to obtain the configured target chip. Then, the model training task corresponding to the target model is executed by the configured target chip, and the model training log data corresponding to the target chip is collected during the execution of the model training task. Then, according to the model training log data corresponding to the target chip, at least one performance evaluation value corresponding to the target chip is determined. Finally, according to the at least one performance evaluation value corresponding to each target chip generated, the adapted target chip corresponding to the target model is determined, and the target task corresponding to the target model is executed by the adapted target chip.

[0018] From the above content, it can be seen that the task execution method provided in this specification can configure the parameters corresponding to the target model and the training task for each target chip according to the acquired chip information of each target chip and the preset target model, and obtain each configured target chip. In the process of executing the model training task corresponding to the target model through each target chip, the model training log data corresponding to each target chip is collected, so as to perform performance evaluation on each target chip and determine the adapted target chip corresponding to the target model. The method in this specification can effectively improve the efficiency of performance evaluation for heterogeneous chips, and the evaluation method of each heterogeneous chip in this specification is more accurate and consistent, making the performance gap between each heterogeneous chip more intuitive and more comparable. While improving the efficiency of determining the best adapted chip for the target model, it provides a practical theoretical basis and effective help for chip manufacturers to optimize the performance of their own chips or to select more suitable application carriers for model training. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawings described herein are used to provide a further understanding of this specification and constitute a part of this specification. The illustrative embodiments and descriptions of this specification are used to explain this specification and do not constitute an improper limitation on this specification. In the drawings: Figure 1 A flowchart of a task execution method provided in this specification; Figure 2 This is an overall process framework diagram of a task execution method provided in this specification; Figure 3 A schematic diagram of a task execution device provided in this specification; Figure 4 A method provided in this specification corresponding to Figure 1 Schematic diagram of the structure of an electronic device. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solutions and advantages of this specification more clear, the technical solutions of this specification will be clearly and completely described below in combination with the specific embodiments of this specification and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of this specification, not all of them. Based on the embodiments in this specification, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this specification.

[0021] The technical solutions provided by the embodiments of this specification are described in detail below in conjunction with the accompanying drawings.

[0022] Figure 1 A flowchart of a task execution method provided in this specification includes the following steps: S101: Obtain chip information corresponding to each target chip to be evaluated.

[0023] S102: For each target chip, according to the chip information corresponding to the target chip and the model data corresponding to the preset target model, the execution parameters required for the target chip to execute the model training task corresponding to the target model are configured to obtain the configured target chip, and the model training task is executed by the configured target chip to collect the model training log data corresponding to the target chip during the execution of the model training task.

[0024] At present, with the advancement of science and technology, smart chips and smart models have become an important part of today's technological development, and are widely used in daily life and high-tech research and development. The same type of smart chips has different manufacturers, and the same type of smart chips produced by different manufacturers have unique internal structures. Different chip structures may affect the performance of the chip and the degree of adaptation to different smart models. The training of smart models depends on the support of smart chips, so how to choose a suitable chip as a model carrier is crucial.

[0025] However, the current performance evaluation of heterogeneous smart chips mostly relies on manual configuration of parameters, which is time-consuming and laborious, and it is difficult to ensure effective alignment between the performance data of different chips, resulting in the final determination of chip performance differences being vague and inaccurate, and unable to provide effective assistance for model training as a selection basis. Therefore, how to efficiently determine the target chip that best matches the target model from various heterogeneous smart chips in order to efficiently execute the target task is an urgent problem to be solved.

[0026] To this end, this specification provides a task execution method, wherein the execution subject used by the method provided in this specification can be a terminal device such as a desktop computer, a laptop computer, or a server. In addition, the execution subject of this specification can also be a subject in the form of software, such as a client installed in a terminal device. For the sake of convenience, this specification only takes the terminal device as the execution subject to explain the task execution method provided.

[0027] Based on this, the terminal device using the task execution method provided in this specification can configure parameters for each target chip according to the chip information of each target chip and the model data of the target model. Then, the training task corresponding to the target model is executed by each target chip after parameter configuration, and the model training log data corresponding to each target chip is collected during the training process, so as to perform performance evaluation on each target chip according to the model training log data and determine at least one performance evaluation value. According to the performance evaluation value of each target chip, the adapted target chip corresponding to the target model is determined to execute the target task corresponding to the target model.

[0028] Among them, the specific application scenario of the terminal device using the method in this specification to evaluate chip performance can be determined according to the actual application requirements. For example, in the scenario of chip selection for the target model, the terminal device using the method in this specification can configure the parameters of each target chip to be evaluated according to the chip information of each chip to be evaluated and the model data of the target model, and perform the corresponding model training task through each chip, collect the training data of each target chip during the training process, so as to determine the performance evaluation value corresponding to each chip, and then determine the target chip that is suitable for the target model. The developer of the target model can directly choose to use the suitable target chip determined by the terminal device as the execution chip of the target model, or can select a chip with stronger performance and higher adaptability to the target model as the execution chip of the target model according to the performance evaluation value corresponding to each chip generated by the terminal device.

[0029] For another example, the terminal device using the method in this specification can also be used in the performance evaluation scenario for heterogeneous chips. The terminal device using the method in this specification can configure the chip parameters corresponding to the model training task according to the chip information of each chip to be evaluated and single or multiple model data, and collect the training data corresponding to the chip when the training task is performed by each chip to be evaluated. The performance evaluation value of each chip is determined according to each training data. While the terminal device subsequently determines the best matching chip for the target model, the developers or manufacturers corresponding to each chip can also intuitively see the performance gap between their own chips and chips from other manufacturers based on the performance evaluation values ​​of each chip generated by the terminal device, so as to reasonably adjust and optimize the chip structure or software programming to improve chip performance.

[0030] In this specification, the terminal device can obtain chip information corresponding to each target chip. The chip information corresponding to each target chip can at least include the chip model corresponding to the target chip, taking the Graphics Processing Unit (GPU) as an example, such as H100 and A100 produced by NVIDIA, MI300 and MI250 produced by AMD, and MTT S4000 produced by Moore's Law.

[0031] In addition, the chip information corresponding to the target chip may also include but is not limited to the architecture information corresponding to the target chip (such as NVIDIA Ampere, AMD RDNA 2, etc. of GPU), memory capacity, memory bandwidth, memory bit width, manufacturing process (such as 7nm, 5nm, etc.), number of computing units (CU / SM) and other chip internal structure data. The specific content and data type of the chip information of the target chip are not strictly limited in this specification and can be flexibly acquired and recorded according to actual application requirements.

[0032] In addition, the target chips mentioned in this specification may have the same corresponding functions, but the internal structure of the chip is different from other target chips. For example, they may be chips of the same functional type produced by different manufacturers, such as GPUs manufactured by manufacturers such as NVIDIA, AMD, Moore's Thread, Huawei, and Cambrian, or they may be chips of the same functional type with different internal structures or chip architectures produced by the same manufacturer, such as GPUs of the Ampere architecture produced by NVIDIA (such as A100) and GPUs of the Hopper architecture also produced by NVIDIA (such as H100).

[0033] Then, for each target chip, the terminal device can configure the execution parameters required to execute the model training task corresponding to the target model through the target chip according to the acquired chip information of the target chip and the model data corresponding to the preset target model, thereby obtaining the configured target chip.

[0034] Among them, since the structures of the target chips may be different or not completely the same, even for the same target model, when the corresponding training tasks are performed by chips with different architectures, there will be obvious differences in the parameter configurations of each chip when performing the training tasks, such as the batch size during the execution of the training task, the method and number of concurrent data loading, parallel computing strategy parameters, etc.

[0035] Therefore, regarding the configuration process of the above-mentioned model parameters, the terminal device can first match the model configuration parameter set corresponding to the pre-stored target model from the database according to the model parameter data corresponding to the pre-set target model. The model configuration parameter set corresponding to the target model includes the model parameter configuration data required when all target chips are equipped with the target model, and the source of the model parameter configuration data required for each target chip to be equipped with the target model can be pre-set for the target chip and the target model, or it can be formulated by the target chip developer for the target model.

[0036] Next, the terminal device can determine the parameter configuration data corresponding to the execution parameters required for the target chip to perform the target model training task from the parameter configuration data set corresponding to the target model determined above according to the chip identifier in the chip information corresponding to each target chip, that is, the chip model information of the target chip. Then, the terminal device can configure the model parameters of the target chip according to the parameter configuration data corresponding to the target chip, and the target chip after the configuration is completed can be used to perform the model training tasks corresponding to the subsequent target model. Among them, the parameter configuration data corresponding to each target chip in the parameter configuration data set corresponding to the target model can at least include the preset model training framework (such as TensorFlow, PyTorch, Megatron, etc.) for the target chip, training hyperparameters (such as learning rate, training batch size, etc.), container parameters, server parameters (number of machines, number of cards, etc.), data collection interface settings during training, and model parameter data corresponding to the target model.

[0037] In addition to the above method of determining the parameter configuration data of the target chip according to the chip identifier in the chip information to configure the model parameters of the target chip, in this specification, the terminal device can also directly configure the data corresponding to the model training task of the target model for each target chip based on the chip internal structure data such as similar chip architecture information, memory capacity, memory bandwidth, memory bit width, manufacturing process, number of computing units, and model data corresponding to the target model contained in the chip information, unlike the above method, so as to obtain each configured target chip. The specific implementation method of how to configure the model parameters corresponding to the target model for each target chip is not strictly limited in this specification and can be flexibly set according to the actual application scenario.

[0038] It should also be noted that in this specification, the specific model category and structure of the target model mentioned above are not strictly limited. You can choose to use intelligent models such as Large Language Model (LLM), Deep Residual Network (ResNet), Bidirectional Encoder Representations from Transformers (BERT) as the target model. The specific model selection can be flexibly adjusted according to the actual application scenarios and needs.

[0039] In addition, if the purpose is to compare the performance of multiple heterogeneous chips, when configuring the parameters corresponding to the target model for each target chip in this specification, multiple target models can also be set at the same time, so that each target chip can be trained with different target models in subsequent training tasks, and different training data can be collected to analyze the chip performance strengths and weaknesses and the corresponding adaptation models from multiple angles. When the chip switches and migrates different target model categories, this specification can pre-configure an image (Dockerfile) for each target chip to ensure that each target chip has a corresponding image configuration environment. When switching or migrating different target models or evaluation environments, the model parameter configuration can be completed quickly, effectively saving the time spent on chip performance evaluation and improving performance evaluation efficiency.

[0040] Further, in this specification, for each target chip obtained through the above steps after parameter configuration, the terminal device can execute the model training task corresponding to the target model through the target chip after parameter configuration. At the same time, the terminal device can collect the model training log data corresponding to the target chip during the execution of the model training task, so as to generate the performance evaluation value corresponding to the target chip later.

[0041] Specifically, for each target chip after parameter configuration, the terminal device can collect resource occupancy log data and task execution log data corresponding to the target chip at each collection time point divided by a preset time interval during the process of the target chip executing the model training task corresponding to the target model. The collected resource occupancy log data can at least include resource data such as chip memory usage (such as GPU video memory usage), CPU occupancy, memory usage, and chip power consumption of the target chip at the corresponding time point, while the collected task execution log data can at least include data such as the number of floating-point operations, data processing volume, model training loss, and task execution accuracy of the target chip at that time point. The resource occupancy log data and task execution log data at each time point can reflect the performance of the target chip from a data perspective, and are an important basis for subsequent performance evaluation and selection of adaptive target chips.

[0042] Next, the terminal device may use the resource usage log data, task execution log data, and task execution time of the target chip to complete the model training task corresponding to the target model as the model training log data corresponding to the target chip.

[0043] It should be noted that in this specification, in addition to the periodic collection of resource usage log data and task execution log data as the performance indicator data corresponding to the target chip, the terminal device can also collect model log data of the target model mounted on the target chip during the execution of the training task and task process data of the execution process of the overall training task.

[0044] Among them, the model log data collected by the terminal device for each target chip can be used to reflect the overall adaptability between the target chip and the target model and the workflow of each model level of the target model during the execution of the training task. The task flow data can be used to represent the task execution process and abnormal situations of the target chip equipped with the target model when performing the model training task. If an abnormal problem occurs during the training process, the abnormality can be detected and repaired based on the task flow data.

[0045] In addition, the specific implementation method of the above data collection process is not strictly limited in this specification. Since there are more or less structural differences between the target chips, if the same data collection method is used for each target chip, it is difficult to align the collected data. Therefore, the terminal device in this specification can collect data by extracting key fields and storing corresponding data during the model training task of the target chip equipped with the target model according to the different chip architectures of each target chip and the previously preset model framework.

[0046] Specifically, the terminal device can collect targeted chip resource scripts for resource scheduling commands when executing model training tasks through different target chips, or the terminal device can perform customized collection of indicator field extraction and renaming based on the log data produced by the model framework based on the preset model framework of different target chips, or through other feasible data collection methods to achieve the above data collection process.

[0047] After collecting the model training log data corresponding to each target chip, before performing subsequent chip performance evaluation, in order to ensure the consistency between the data of each target chip, the terminal device can also perform data type standardization processing on the model training log data corresponding to each target chip to obtain the aligned model training log data corresponding to each target chip. The above standardization processing can be simply understood as classifying and aligning the model training log data corresponding to the target chip, so that the model training log data corresponding to each target chip is recorded and stored in the same form.

[0048] S103: For each target chip, determine at least one performance evaluation value corresponding to the target chip according to the model training log data corresponding to the target chip.

[0049] In this specification, for each target chip, the terminal device may generate at least one performance evaluation value for the target chip according to the previously determined model parameter data corresponding to the target chip.

[0050] Specifically, the terminal device can generate chip performance data corresponding to each target chip according to the model training log data corresponding to the target chip and the pre-set performance evaluation rules. The chip performance data corresponding to the target chip can at least include the chip computing power, chip throughput and chip acceleration ratio corresponding to the target chip, which can represent the performance of the chip, and the above-mentioned performance evaluation rules include calculation rules or formulas pre-set for each chip performance data, such as calculating the chip computing power according to the amount of calculation that the target chip can perform per unit time, and calculating the chip acceleration ratio according to the optimized execution time and the unoptimized execution time. This specification does not strictly limit the data categories and specific contents involved in the chip performance data, as well as the calculation methods or rules corresponding to each chip performance data, and can be flexibly set and selected according to actual application requirements.

[0051] Then, the terminal device can generate at least one performance evaluation value corresponding to the target chip based on the determined chip performance data corresponding to the target chip, the previously determined model parameter data corresponding to the target chip, and the preset performance evaluation dimensions for each target chip. For example, assuming that the preset performance evaluation dimensions for each target chip include the chip computing power dimension and the model training task execution time dimension, the terminal device can determine the performance data corresponding to each target chip under the chip computing power dimension and the model training task execution time dimension from the chip performance data and model parameter data corresponding to each target chip determined through the above steps, thereby serving as the corresponding performance evaluation value.

[0052] In addition, in this specification, the terminal device can also directly use the data under all performance evaluation dimensions involved in the data of each target chip as the corresponding performance evaluation value based on the chip performance data and model parameter data corresponding to each target chip, and multiple performance evaluation values ​​of each target chip can be combined into the performance evaluation result corresponding to the target chip. The specific form of the performance evaluation result is not strictly limited in this specification, and it can be in the form of a table for intuitive display, a detailed list of the corresponding data of the target chip under each performance evaluation dimension, or other feasible methods.

[0053] S104: Determine an adapted target chip corresponding to the target model from the target chips according to at least one performance evaluation value corresponding to each target chip, and execute the target task corresponding to the target model through the adapted target chip.

[0054] In this specification, the terminal device can screen out a single or multiple adapted target chips corresponding to the target model from each target chip based on at least one performance evaluation value corresponding to each target chip determined through the above steps, thereby executing the target task corresponding to the target model through the determined adapted target chip.

[0055] Specifically, the terminal device can generate a comprehensive performance comparison result for each target chip based on at least one performance evaluation value or the above-mentioned performance evaluation result consisting of multiple performance evaluation values ​​determined for each target chip. The comprehensive performance comparison result can be used to reflect the numerical difference of each target chip under the same performance evaluation dimension, and can also show the degree of adaptation to the target model and the target model training task.

[0056] Then, for each target chip, the terminal device can determine the model adaptation degree value between the target chip and the target model according to the ranking of each performance data of the target chip in the above-determined comprehensive performance comparison result. Regarding the specific determination process of the model adaptation degree value, it can be a weighted summation based on the ranking corresponding to each performance data in the comprehensive performance comparison result to obtain the comprehensive performance ranking of the target chip for the target model among various target chips, or it can be determined whether the target chip is highly adapted to the target model based on the pre-selected key performance data. The specific implementation method for determining the model adaptation degree value is not strictly limited in this specification and can be flexibly selected according to the actual application scenario and needs.

[0057] It should be noted that this specification does not strictly limit the specific content of the performance indicators and data of each target chip shown in the above-mentioned comprehensive performance comparison results, which may include but not be limited to the following types of indicator data: chip performance indicators (such as end-to-end time, loading time, training time, throughput, computing power, acceleration ratio, etc.), resource usage indicators (such as chip memory usage, CPU, memory occupancy, power consumption, energy efficiency ratio, etc.), functional correctness indicators (such as loss convergence time, model accuracy, training task execution accuracy, etc.), stability indicators (such as training time, effective training time ratio, etc.), etc.

[0058] In addition to determining the model adaptation value based on the comprehensive performance comparison result, in this specification, the terminal device can also determine the model adaptation value between each target chip and the target model based on the model log data collected when collecting chip training data and the comprehensive performance comparison result determined by the above steps. When multiple target models are involved, the terminal device can also generate a corresponding model adaptation value ranking result containing all target chips for each target model, and send it to the terminal device used by the user, to provide theoretical help for users who select execution chips for target models or users who evaluate the performance of multiple heterogeneous chips.

[0059] Furthermore, the terminal device can select the target chip corresponding to the target model from each target chip according to the comprehensive performance comparison result and the model adaptation degree value determined by the above method. Then, the terminal device can execute the target task corresponding to the target model through the determined target chip.

[0060] Among them, the specific type and content of the target task are related to the specific type of the target model. The target task is not specifically limited in this specification. It can be to use another batch of sample data with a larger data volume corresponding to the target model to execute the model training task of the target model through the target chip, so as to obtain the target model with practical working ability after the training converges, or it can be to directly apply the target model that converges after executing the model training task in the above-mentioned way in a normal working environment through the target chip.

[0061] In addition, in this specification, the comprehensive performance comparison results determined by the above steps can also be used to directly compare the chip performance between each target chip. Developers corresponding to each target chip can intuitively understand the data performance of their own chip under each performance evaluation dimension, the performance gap and performance advantage between their own chip and other heterogeneous chips, and the degree of adaptation between their own chip and the target model to which the model training task belongs based on the comprehensive performance comparison results determined by the terminal device, thereby facilitating chip optimization and problem correction.

[0062] In addition, in this specification, the terminal device can also perform performance problem detection on each target chip according to the comprehensive performance comparison results generated by the above steps, and generate performance problem detection results corresponding to each target chip. Then, the terminal device can generate performance optimization strategy information for the target chip according to the performance problem detection results corresponding to each target chip. The performance optimization strategy information can be used to prompt the developer of the target chip of the shortcomings and problems of the current target chip and give suggestions with a certain helpful effect. For example, assuming that the determined comprehensive performance comparison results indicate that the power consumption of a certain target chip is high, but the execution efficiency of the model training task is relatively medium or even low among the target chips, the terminal device can generate performance optimization strategy information similar to "the power consumption of the chip needs to be optimized when working" for the target chip.

[0063] The terminal device can send the performance optimization strategy information corresponding to each target chip to the terminal device used by the corresponding developer, so that the developer can optimize the performance of the target chip according to the received performance optimization strategy information, thereby improving the overall performance and working performance of the target chip.

[0064] In order to facilitate understanding of the overall process of the above task execution method, the following is a summary of the overall process framework diagram of the task execution method. Figure 2 as shown in .

[0065] Figure 2 This is an overall process framework diagram of a task execution method provided in this specification.

[0066] like Figure 2As shown, for each target chip, the terminal device can configure the execution parameters required for the target chip to execute the model training task corresponding to the target model according to the chip information corresponding to the target chip and the model data corresponding to the preset target model, so as to obtain the target chip after the model configuration. Then, the terminal device can execute the model training task corresponding to the target model through the configured target chip, and collect the model training log data corresponding to the target chip during the model training process.

[0067] Then, the terminal device can generate the performance evaluation value corresponding to each target chip according to the model training log data corresponding to each target chip, and generate the comprehensive performance comparison result and model adaptation degree value for each target chip according to the performance evaluation value corresponding to each target chip, so as to determine the adapted target chip corresponding to the target model and execute the target task corresponding to the target model. In addition, the terminal device can also detect the performance problem results and performance optimization strategy information for each target chip according to the comprehensive performance comparison results, so that chip developers can optimize and adjust the chip to improve chip performance.

[0068] From the above content, it can be seen that the task execution method provided in this specification can configure the parameters corresponding to the model training task of the target model for each target chip according to the acquired chip information of each target chip and the preset target model, and obtain each configured target chip. In the process of executing the model training task corresponding to the target model through each target chip, the model training log data corresponding to each target chip is collected, so as to perform performance evaluation on each target chip, and according to the performance evaluation value corresponding to each target chip, the comprehensive performance comparison result for each target chip, the model adaptation ranking result, and the performance optimization strategy information for each target chip are generated. Then, the adapted target chip corresponding to the target model is determined, and the target task is executed by the adapted target chip.

[0069] The methods in this specification can effectively improve the efficiency of performance evaluation for heterogeneous chips, and the evaluation method of each heterogeneous chip in this specification is more accurate and consistent, making the performance gap between heterogeneous chips more intuitive and more comparable. It provides a practical theoretical basis and effective help for chip manufacturers to optimize the performance of their own chips or select more suitable application carriers for model training.

[0070] The above are one or more implementation methods of this specification. Based on the same idea, this specification also provides a corresponding task execution device, such as Figure 3 shown.

[0071] Figure 3 A schematic diagram of a task execution device provided in this specification includes: The acquisition module 301 is used to acquire chip information corresponding to each target chip to be evaluated, wherein each target chip has the same function, but the internal chip architecture of each target chip is not completely the same; The training module 302 is used to configure the execution parameters required for the target chip to execute the model training task corresponding to the target model according to the chip information corresponding to the target chip and the model data corresponding to the preset target model for each target chip, obtain the configured target chip, and execute the model training task through the configured target chip to collect the model training log data corresponding to the target chip during the execution of the model training task; An evaluation module 303 is used to determine, for each target chip, at least one performance evaluation value corresponding to the target chip according to the model training log data corresponding to the target chip; The determination module 304 is used to determine the adapted target chip corresponding to the target model from the target chips according to at least one performance evaluation value corresponding to the target chips, and execute the target task corresponding to the target model through the adapted target chip.

[0072] Optionally, for each target chip, the chip information corresponding to the target chip at least includes a chip model identifier corresponding to the target chip; The training module 302 is specifically used to determine a parameter configuration data set corresponding to the target model based on the model data corresponding to the target model, wherein the parameter configuration data set is preset with parameter configuration data corresponding to the execution parameters required for each target chip to execute the model training task corresponding to the target model; for each target chip, according to the chip model identifier in the chip information corresponding to the target chip, match the parameter configuration data corresponding to the target chip from the parameter configuration data set, wherein the parameter configuration data corresponding to the target chip at least includes a model training framework, training hyperparameters, container parameters preset for the target chip, and model parameter data corresponding to the target model; according to the parameter configuration data corresponding to the target chip, parameter configuration is performed on the execution parameters required for the target chip to execute the model training task corresponding to the target model to obtain the configured target chip.

[0073] Optionally, the training module 302 is specifically used to collect resource usage log data and task execution log data corresponding to each target chip at preset time intervals during the execution of the model training task by the configured target chip. For each time point divided according to the time interval, the resource usage log data collected at the time point at least includes the chip memory usage, CPU usage, chip power consumption and memory usage of the target chip at the time point, and the task execution log data collected at the time point at least includes the number of floating-point operations, data processing volume, model training loss and task execution accuracy of the target chip at the time point. The model training log data corresponding to the target chip is determined based on the resource usage log data and task execution log data corresponding to the target chip at each time point, and the task execution time of the target chip performing the model training task.

[0074] Optionally, the evaluation module 303 is specifically used to generate, for each target chip, chip performance data corresponding to the target chip based on the model training log data corresponding to the target chip and preset performance evaluation rules, the chip performance data including at least chip computing power data, chip throughput and chip acceleration ratio corresponding to the target chip; and determine, based on the model training log data and chip performance data corresponding to the target chip, at least one performance evaluation value corresponding to the target chip and each performance evaluation dimension preset for each target chip.

[0075] Optionally, the determination module 304 is specifically used to generate a comprehensive performance comparison result for each target chip according to at least one performance evaluation value corresponding to each target chip; and determine the adaptation target chip corresponding to the target model from the target chips according to the comprehensive performance comparison result.

[0076] Optionally, the determination module 304 is specifically used to determine, for each target chip, a model adaptation degree value between the target chip and the target model according to the comprehensive performance comparison result; and to determine at least one adapted target chip corresponding to the target model from the target chips according to the model adaptation degree values ​​corresponding to the target chips.

[0077] Optionally, the determination module 304 is specifically used to, for each target chip, perform performance problem detection on the target chip according to the comprehensive performance comparison result, and obtain a performance problem detection result corresponding to the target chip; generate performance optimization strategy information for the target chip according to the performance problem detection result corresponding to the target chip, and send the performance optimization strategy information of the target chip to a terminal device used by a developer corresponding to the target chip, so that the developer corresponding to the target chip can optimize the performance of the target chip according to the performance optimization strategy information of the target chip.

[0078] This specification also provides a computer-readable storage medium, which stores a computer program, which can be used to execute the above Figure 1 Provides the task execution method.

[0079] This manual also provides Figure 4 The one shown corresponds to Figure 1 A schematic diagram of the electronic device. Figure 4 As shown, at the hardware level, the electronic device includes a processor, an internal bus, a network interface, a memory, and a non-volatile memory, and may also include other hardware required for the business. The processor reads the corresponding computer program from the non-volatile memory into the memory and then runs it to achieve the above Figure 1 The task execution method described.

[0080] In the 1990s, it was very clear whether the improvement of a technology was hardware improvement (for example, improvement of the circuit structure of diodes, transistors, switches, etc.) or software improvement (improvement of the method flow). However, with the development of technology, many improvements of the method flow today can be regarded as direct improvements of the hardware circuit structure. Designers almost always obtain the corresponding hardware circuit structure by programming the improved method flow into the hardware circuit. Therefore, it cannot be said that the improvement of a method flow cannot be implemented with hardware entity modules. For example, a programmable logic device (PLD) (such as a field programmable gate array (FPGA)) is such an integrated circuit whose logical function is determined by the user's programming of the device. Designers can "integrate" a digital system on a PLD by programming it themselves, without having to ask chip manufacturers to design and make dedicated integrated circuit chips. Moreover, nowadays, instead of manually making integrated circuit chips, this kind of programming is mostly implemented by "logic compiler" software, which is similar to the software compiler used when developing and writing programs, and the original code before compilation must also be written in a specific programming language, which is called hardware description language (HDL). There is not only one kind of HDL, but many kinds, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, RHDL (Ruby Hardware Description Language), etc. The most commonly used ones are VHDL (Very-High-Speed ​​Integrated Circuit Hardware Description Language) and Verilog. Those skilled in the art should also know that it is only necessary to program the method flow slightly in the above-mentioned hardware description languages ​​and program it into the integrated circuit, and then it is easy to obtain the hardware circuit that implements the logic method flow.

[0081] The controller may be implemented in any suitable manner, for example, the controller may take the form of a microprocessor or processor and a computer-readable medium storing a computer-readable program code (e.g., software or firmware) executable by the (micro)processor, a logic gate, a switch, an application-specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller, examples of which include but are not limited to the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicone Labs C8051F320, and the memory controller may also be implemented as part of the control logic of the memory. It is also known to those skilled in the art that, in addition to implementing the controller in a purely computer-readable program code manner, the controller may be implemented in the form of a logic gate, a switch, an application-specific integrated circuit, a programmable logic controller, and an embedded microcontroller by logically programming the method steps. Therefore, such a controller may be considered as a hardware component, and the devices for implementing various functions included therein may also be considered as structures within the hardware component. Or even, the devices for implementing various functions may be considered as both software modules for implementing the method and structures within the hardware component.

[0082] The systems, devices, modules or units described in the above embodiments may be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, the computer may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0083] For the convenience of description, the above device is described in various units according to their functions. Of course, when implementing this specification, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0084] Those skilled in the art will appreciate that the embodiments of this specification may be provided as methods, systems, or computer program products. Therefore, this specification may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, this specification may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0085] This specification is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of this specification. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0086] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0087] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0088] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0089] The memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0090] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0091] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0092] It should be understood by those skilled in the art that the embodiments of this specification may be provided as methods, systems or computer program products. Therefore, this specification may take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware. Moreover, this specification may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0093] This specification may be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. This specification may also be practiced in distributed computing environments where tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules may be located in local and remote computer storage media, including storage devices.

[0094] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0095] The above description is only an embodiment of the present specification and is not intended to limit the present specification. For those skilled in the art, the present specification may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present specification shall be included in the scope of the claims of the present specification.

Claims

1. A task execution method, characterized in that: include: Obtain chip information corresponding to each target chip to be evaluated, wherein each target chip is a chip with the same function, but the internal chip architectures of each target chip are not completely the same; For each target chip, according to the chip information corresponding to the target chip and the model data corresponding to the preset target model, the execution parameters required for the target chip to execute the model training task corresponding to the target model are configured to obtain the configured target chip, and the model training task is executed by the configured target chip to collect the model training log data corresponding to the target chip during the execution of the model training task; For each target chip, determine at least one performance evaluation value corresponding to the target chip according to the model training log data corresponding to the target chip; According to at least one performance evaluation value corresponding to each target chip, an adapted target chip corresponding to the target model is determined from the target chips, and the target task corresponding to the target model is executed by the adapted target chip.

2. The method according to claim 1, characterized in that For each target chip, the chip information corresponding to the target chip at least includes a chip model identifier corresponding to the target chip; For each target chip, according to the chip information corresponding to the target chip and the model data corresponding to the preset target model, the execution parameters required for the target chip to execute the model training task corresponding to the target model are configured to obtain the configured target chip, specifically including: Determine, according to the model data corresponding to the target model, a parameter configuration data set corresponding to the target model, wherein the parameter configuration data set is preset with parameter configuration data corresponding to execution parameters required for each target chip to perform a model training task corresponding to the target model; For each target chip, according to the chip model identifier in the chip information corresponding to the target chip, the parameter configuration data corresponding to the target chip is matched from the parameter configuration data set, and the parameter configuration data corresponding to the target chip at least includes a model training framework preset for the target chip, training hyperparameters, container parameters, and model parameter data corresponding to the target model; According to the parameter configuration data corresponding to the target chip, the execution parameters required for the target chip to execute the model training task corresponding to the target model are configured to obtain the configured target chip.

3. The method according to claim 1, characterized in that During the execution of the model training task, the model training log data corresponding to the target chip is collected, specifically including: For each target chip, during the execution of the model training task by the configured target chip, resource occupancy log data and task execution log data corresponding to the target chip are collected at preset time intervals; for each time point divided according to the time interval, the resource occupancy log data collected at the time point at least includes the chip memory usage rate, CPU occupancy rate, chip power consumption and memory usage rate of the target chip at the time point; the task execution log data collected at the time point at least includes the number of floating-point operations, data processing volume, model training loss and task execution accuracy of the target chip at the time point; The model training log data corresponding to the target chip is determined based on the resource occupancy log data and task execution log data corresponding to the target chip at each time point, as well as the task execution time of the target chip executing the model training task.

4. The method according to claim 1, characterized in that Determining at least one performance evaluation value corresponding to the target chip according to the model training log data corresponding to the target chip, specifically comprising: For each target chip, according to the model training log data corresponding to the target chip and the preset performance evaluation rules, the chip performance data corresponding to the target chip is generated, wherein the chip performance data at least includes the chip computing power data, chip throughput and chip acceleration ratio corresponding to the target chip; According to the model training log data and chip performance data corresponding to the target chip, at least one performance evaluation value of the target chip corresponding to each performance evaluation dimension preset for each target chip is determined.

5. The method according to claim 1, characterized in that Determining, from the target chips, an adaptation target chip corresponding to the target model according to at least one performance evaluation value corresponding to each target chip, specifically includes: Generating a comprehensive performance comparison result for each target chip according to at least one performance evaluation value corresponding to each target chip; According to the comprehensive performance comparison result, the adapted target chip corresponding to the target model is determined from the target chips.

6. The method according to claim 5, characterized in that According to the comprehensive performance comparison result, determining the adapted target chip corresponding to the target model from the target chips specifically includes: For each target chip, determining a model adaptation degree value between the target chip and the target model according to the comprehensive performance comparison result; At least one adapted target chip corresponding to the target model is determined from the target chips according to the model adaptation degree values ​​corresponding to the target chips.

7. The method according to claim 5, characterized in that The method further comprises: For each target chip, according to the comprehensive performance comparison result, a performance problem detection is performed on the target chip to obtain a performance problem detection result corresponding to the target chip; Based on the performance problem detection results corresponding to the target chip, performance optimization strategy information for the target chip is generated, and the performance optimization strategy information of the target chip is sent to the terminal device used by the developer corresponding to the target chip, so that the developer corresponding to the target chip can optimize the performance of the target chip according to the performance optimization strategy information of the target chip.

8. A task execution device, characterized in that: include: An acquisition module, used for acquiring chip information corresponding to each target chip to be evaluated, wherein each target chip is a chip with the same function, but the internal chip architecture of each target chip is not completely the same; A training module is used to configure, for each target chip, execution parameters required for the target chip to execute the model training task corresponding to the target model according to the chip information corresponding to the target chip and the model data corresponding to the preset target model, obtain the configured target chip, and execute the model training task through the configured target chip to collect the model training log data corresponding to the target chip during the execution of the model training task; An evaluation module, configured to determine, for each target chip, at least one performance evaluation value corresponding to the target chip according to the model training log data corresponding to the target chip; The determination module is used to determine the adapted target chip corresponding to the target model from the target chips according to at least one performance evaluation value corresponding to each target chip, and execute the target task corresponding to the target model through the adapted target chip.

9. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by a processor, the method described in any one of claims 1 to 7 is implemented.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the method described in any one of claims 1 to 7 is implemented.

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