Device based on board-level wired signal extension transmission

Abstract

The invention relates to a device based on board-level wired signal extended transmission, which comprises a processor, a signal isolation module, a first signal transmitting module, a transmission connecting line, a second signal transmitting module and controlled equipment, and is characterized in that the output end of the processor is connected with the input end of the signal isolation module; the output end of the signal isolation module is connected with the input end of the first signal transmitting module, the first signal transmitting module is in communication connection with the second signal transmitting module through the transmission connecting line, the output end of the second signal transmitting module is connected with the controlled equipment, and the feedback end of the controlled equipment is connected with the input end of the first signal transmitting module. The first signal transmitting module is in communication connection with the second signal transmitting module through the transmission connecting line, and the second signal transmitting module is connected with the feedback end of the processor through the signal isolation module. According to the invention, short-distance signals can be converted into differential signals for long-distance transmission, the influence of interference signals on actual signal transmission is avoided, and lossless transmission is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic signal transmission, and in particular to a device based on board-level wired signal extension transmission. Background Art

[0002] It is used for short-distance transmission signals from the main control board CPU (central processing unit), MCU (micro control unit), FPGA (field programmable logic controller), DSP (digital signal processor), ARM processor or other types of processors, such as UART (universal asynchronous receiver and transmitter bus), SPI (single host serial peripheral interface bus), IIC (integrated circuit bus) and single bus or other communication interface extension transmission technology. These signals are digital signals and are usually transmitted internally at the board level of an embedded system. We usually call them board-level transmission communication methods.

[0003] Among the signal transmission methods listed above, SPI has the fastest speed, which can exceed 10M / S. These communication methods can meet the needs of controlling devices to send commands and read back results. However, in actual applications, it is possible that the controlled device connected to a host is not next to the host. For example, in many test scenarios, the controlled device needs to be placed at a longer distance of 10M to 100M or 1000M. In such an application environment, if the design is based on an embedded system, there will be problems with these long-distance transmissions.

[0004] There are many ways to transmit digital signals at the board level, such as UART, whose maximum rate is in the order of Kbps and Mbps. If direct wire transmission is used, the transmission distance is affected by processor performance, transmission cable quality, and cable length. In actual transmission applications, UART communication is affected by factors such as electrical signal attenuation and crosstalk. Therefore, it is necessary to consider the limitation of communication distance and technical adjustment in actual applications. Electrical signal attenuation As the transmission distance increases, the voltage of the UART signal will be attenuated, which may lead to unstable or even lost data transmission.

[0005] In IIC, it is usually used for chip-to-chip transmission. Even for peripheral devices of the main control device, the transmission distance usually cannot exceed 2M. Moreover, in this transmission distance, multiple devices should be avoided in series as much as possible, and a one-to-one connection should be adopted as much as possible. At the same time, the pull-up resistance should be reduced. For example, within the conventional 50cm, a 4.7K resistor can be used for pull-up. If it exceeds 1M, the pull-up resistance can be reduced to 1K or 1.5K. Even so, it is necessary to use better cables, and consider shielding to avoid interference.

[0006] In the SPI bus, the transmission speed is undefined, and the maximum can exceed 10M or up to 100M. SPI works in master-slave mode, usually with one master device and one or more slave devices. Generally, SPI requires 4 wires, but three wires (unidirectional transmission) can also be used, as well as DSPI with dual data lines and QSPI with four data lines.

[0007] All of the above transmission methods are used for the transmission of digital signals. The high level of the output is generally 3.3V, and there are also 5V levels. Under the same conditions, the higher the level, the longer the transmission distance; in addition, the lower the transmission speed, the longer the transmission distance. In the application requirements of higher and higher speeds, the output high-level signal is getting lower and lower, which can make the waveform establishment time of the digital signal faster, thereby achieving a higher speed. However, no matter which of the above transmission methods is used, it is impossible to achieve lossless transmission at a distance of more than 20M. Summary of the invention

[0008] In order to solve the above technical problems, an object of the present invention is to provide a device based on board-level wired signal extension transmission.

[0009] To achieve the above object, the present invention adopts the following technical solution:

[0010] A device based on board-level wired signal extension transmission includes a processor, a signal isolation module, a first signal transmission module, a transmission connection line, a second signal transmission module and a controlled device, wherein the output end of the processor is connected to the input end of the signal isolation module, the output end of the signal isolation module is connected to the input end of the first signal transmission module, the first signal transmission module is communicatively connected to the second signal transmission module via the transmission connection line, the output end of the second signal transmission module is connected to the controlled device, the feedback end of the controlled device is connected to the input end of the first signal transmission module, the first signal transmission module is communicatively connected to the second signal transmission module via the transmission connection line, and the second signal transmission module is connected to the feedback end of the processor via the signal isolation module.

[0011] Preferably, in the device based on board-level wired signal extension transmission, the processor includes but is not limited to CPU, MCU, FPGA, DSP or ARM.

[0012] Preferably, in the device based on board-level wired signal extension transmission, the signal isolation module includes an isolation chip U95, a first pin of the isolation chip U95 is connected to VDD_3V3, and its first pin is grounded through a capacitor C792 and also grounded through a capacitor C790, a second pin of the isolation chip U95 is connected to the SPI_CLK end through a resistor R614, a third pin of the isolation chip U95 is connected to the SPI_MOSI end through a resistor R615, a fourth pin and a fifth pin of the isolation chip U95 are grounded, an eighth pin of the isolation chip U95 is connected to ISO_3V3, and its eighth pin is grounded through a capacitor C789 and also grounded through a capacitor C791, and a seventh pin and a sixth pin of the isolation chip U95 are connected to the first signal transmission module;

[0013] It also includes an isolation chip U96, a first pin of the isolation chip U96 is connected to VDD_3V3, a second pin of the isolation chip U96 is connected to the SPI1_CS terminal through a resistor R612, a third pin of the isolation chip U96 is connected to the UART1_TXD terminal through a resistor R613, a fourth pin and a fifth pin of the isolation chip U96 are grounded, an eighth pin of the isolation chip U96 is connected to ISO_5V, and a seventh pin and a sixth pin of the isolation chip U96 are connected to the first signal transmission module.

[0014] Preferably, in the device based on board-level wired signal extension transmission, the isolation chip U95 and the isolation chip U96 are of model ISO7220.

[0015] Preferably, in the device based on board-level wired signal extension transmission, the first signal transmission module includes a differential transmission chip U93, the first pin of the differential transmission chip U93 is connected to the seventh pin of the isolation chip U95, the seventh pin of the differential transmission chip U93 is connected to the sixth pin of the isolation chip U95, the fourth pin and the twelfth pin of the differential transmission chip U93 are respectively connected to the ISO_3V3 end through resistors R583 and R584, the ninth pin of the differential transmission chip U93 is connected to the seventh pin of the isolation chip U96, the fifteenth pin of the differential transmission chip U93 is connected to the sixth pin of the isolation chip U96, the eighth pin of the differential transmission chip U93 is grounded, and the differential The sixteenth pin of the differential transmitting chip U93 is connected to the ISO_3V3 terminal and is also grounded through the capacitor C793, the second pin and the third pin of the differential transmitting chip U93 are respectively connected to the SPI1_CLK_P terminal and the SPI1_CLK_N terminal, the sixth pin and the fifth pin of the differential transmitting chip U93 are respectively connected to the SPI1_MOSI_P terminal and the SPI1_MOSI_N terminal, the tenth pin and the eleventh pin of the differential transmitting chip U93 are respectively connected to the SPI1_CS_P terminal and the SPI1_C_N terminal, the fourteenth pin and the thirteenth pin of the differential transmitting chip U93 are respectively connected to the UART1_TXD_P terminal and the UART1_TXD_N terminal.

[0016] Preferably, in the device based on board-level wired signal extension transmission, the model of the differential transmission chip U93 is MAX3032E.

[0017] Preferably, in the device based on board-level wired signal extension transmission, the second signal transmission module includes a differential receiving chip U102, the fourth pin, the twelfth pin and the sixteenth pin of the differential receiving chip U102 are connected to the ISO_3V3 terminal and grounded through the capacitor C809, the second pin and the third pin of the differential receiving chip U102 are respectively connected to the SPI1_MISO_P terminal and the SPI1_MISO_N terminal, the sixth pin and the fifth pin of the differential receiving chip U102 are respectively connected to the SPI2_MOSI_P terminal and the SPI2_MOSI_N terminal, and the differential receiving chip The tenth pin and the eleventh pin of the differential receiving chip U102 are connected to the UART1_RXD_P terminal and the UART1_RXD_N terminal respectively, the fourteenth pin and the thirteenth pin of the differential receiving chip U102 are connected to the UART2_RXD_P terminal and the UART2_RXD_N terminal respectively, the first pin and the seventh pin of the differential receiving chip U102 are connected to the second pin and the third pin of the isolation chip U103 respectively, the ninth pin and the fifteenth pin of the differential receiving chip U102 are connected to the second pin and the third pin of the isolation chip U104 respectively, and the eighth pin of the differential receiving chip U102 is grounded.

[0018] Preferably, the device based on board-level wired signal extension transmission is characterized in that: the model of the differential receiving chip U102 is MAX3096E, and the models of the isolation chip U103 and the isolation chip U104 are both ISO7220.

[0019] Preferably, in the device based on board-level wired signal extension transmission, the transmission connection lines use multiple groups of twisted pair cables and shielded layer signal cables, including HR10A series.

[0020] Preferably, in the device based on board-level wired signal extension transmission, the controlled device has a built-in RS422 receiving chip.

[0021] By means of the above scheme, the present invention has at least the following advantages:

[0022] The present invention converts the signal into a differential transmission mode, uses a pair of separate twisted pair cables to transmit a signal, so that the influence of interference signals on the actual transmitted signal can be avoided as much as possible during the transmission process, and converts short-distance signals into differentials for long-distance transmission, so that it can achieve lossless transmission at a distance of 20M.

[0023] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention and implement it according to the contents of the specification, the following is a detailed description of the preferred embodiments of the present invention in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0025] Figure 1 It is a principle block diagram of the present invention;

[0026] Figure 2 is a schematic diagram of the signal isolation module and the first signal transmission module of the present invention;

[0027] Figure 3 is a schematic diagram of the signal isolation module and the second signal transmission module of the present invention;

[0028] Figure 4 is a structural diagram of the transmission connecting line of the present invention;

[0029] Figure 5 It is a schematic diagram of a built-in RS422 receiving chip in a controlled device of the present invention. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0031] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0032] Example

[0033] like Figures 1 to 5 As shown, a device based on board-level wired signal extension transmission includes a processor 1, a signal isolation module 2, a first signal transmission module 3, a transmission connection line 4, a second signal transmission module 5 and a controlled device 6, wherein the output end of the processor 1 is connected to the input end of the signal isolation module 2, the output end of the signal isolation module 2 is connected to the input end of the first signal transmission module 3, the first signal transmission module 3 is communicatively connected to the second signal transmission module 5 through the transmission connection line 4, the output end of the second signal transmission module 5 is connected to the controlled device 6, the feedback end of the controlled device 6 is connected to the input end of the first signal transmission module 3, the first signal transmission module 3 is communicatively connected to the second signal transmission module 5 through the transmission connection line 4, and the second signal transmission module 5 is connected to the feedback end of the processor 1 through the signal isolation module 2.

[0034] The processor 1 described in the present invention includes but is not limited to CPU, MCU, FPGA, DSP or ARM and other devices (hereinafter referred to as the processor) and the UART, SPI, IIC, single bus and other transmission protocols issued are still carried out in accordance with the original inherent protocol transmission method.

[0035] The signal isolation module 2 described in the present invention includes an isolation chip U95, a first pin of the isolation chip U95 is connected to VDD_3V3, and its first pin is grounded through a capacitor C792 and also grounded through a capacitor C790, a second pin of the isolation chip U95 is connected to the SPI_CLK end through a resistor R614, a third pin of the isolation chip U95 is connected to the SPI_MOSI end through a resistor R615, a fourth pin and a fifth pin of the isolation chip U95 are grounded, an eighth pin of the isolation chip U95 is connected to ISO_3V3, and its eighth pin is grounded through a capacitor C789 and also grounded through a capacitor C791, and a seventh pin and a sixth pin of the isolation chip U95 are connected to the first signal transmission module 3;

[0036] It also includes an isolation chip U96, a first pin of the isolation chip U96 is connected to VDD_3V3, a second pin of the isolation chip U96 is connected to the SPI1_CS terminal through a resistor R612, a third pin of the isolation chip U96 is connected to the UART1_TXD terminal through a resistor R613, a fourth pin and a fifth pin of the isolation chip U96 are grounded, an eighth pin of the isolation chip U96 is connected to ISO_5V, and a seventh pin and a sixth pin of the isolation chip U96 are connected to the first signal transmission module 3.

[0037] Among them, the models of the isolation chip U95 and the isolation chip U96 are ISO7220.

[0038] The first signal transmission module 3 in the present invention includes a differential transmission chip U93, a first pin of the differential transmission chip U93 is connected to the seventh pin of the isolation chip U95, a seventh pin of the differential transmission chip U93 is connected to the sixth pin of the isolation chip U95, a fourth pin and a twelfth pin of the differential transmission chip U93 are connected to the ISO_3V3 end through resistors R583 and R584 respectively, a ninth pin of the differential transmission chip U93 is connected to the seventh pin of the isolation chip U96, a fifteenth pin of the differential transmission chip U93 is connected to the sixth pin of the isolation chip U96, an eighth pin of the differential transmission chip U93 is grounded, and a The sixteenth pin is connected to the ISO_3V3 terminal and is also grounded through the capacitor C793. The second pin and the third pin of the differential transmitting chip U93 are respectively connected to the SPI1_CLK_P terminal and the SPI1_CLK_N terminal. The sixth pin and the fifth pin of the differential transmitting chip U93 are respectively connected to the SPI1_MOSI_P terminal and the SPI1_MOSI_N terminal. The tenth pin and the eleventh pin of the differential transmitting chip U93 are respectively connected to the SPI1_CS_P terminal and the SPI1_C_N terminal. The fourteenth pin and the thirteenth pin of the differential transmitting chip U93 are respectively connected to the UART1_TXD_P terminal and the UART1_TXD_N terminal.

[0039] Among them, the model of the differential transmission chip U93 is MAX3032E.

[0040] The second signal transmission module 5 of the present invention includes a differential receiving chip U102, the fourth pin, the twelfth pin and the sixteenth pin of the differential receiving chip U102 are connected to the ISO_3V3 terminal and grounded through the capacitor C809, the second pin and the third pin of the differential receiving chip U102 are respectively connected to the SPI1_MISO_P terminal and the SPI1_MISO_N terminal, the sixth pin and the fifth pin of the differential receiving chip U102 are respectively connected to the SPI2_MOSI_P terminal and the SPI2_MOSI_N terminal, and the tenth pin of the differential receiving chip U102 is connected to the SPI2_MOSI_P terminal and the SPI2_MOSI_N terminal. The fourteenth and thirteenth pins of the differential receiving chip U102 are connected to the UART2_RXD_P and UART2_RXD_N terminals respectively, the first and seventh pins of the differential receiving chip U102 are connected to the second and third pins of the isolation chip U103 respectively, the ninth and fifteenth pins of the differential receiving chip U102 are connected to the second and third pins of the isolation chip U104 respectively, and the eighth pin of the differential receiving chip U102 is grounded.

[0041] The model of the differential receiving chip U102 is MAX3096E, and the models of the isolation chip U103 and the isolation chip U104 are both ISO7220.

[0042] The transmission connection line 4 of the present invention uses multiple sets of twisted pair wires and shielded layer signal wires, including the HR10A series. The following uses HR10A as an example for 4-wire SPI transmission. Two sets of isolated power supplies can be reserved for the controlled device at the same time. The power supply can be used for power supply of the controlled device within a range of 30M. And directly output SPI to the controlled device.

[0043] In the present invention, after the main control processor sends a signal, signal isolation is first performed on the main control board (power isolation is performed at the same time). Signal isolation can improve the accuracy of signal transmission. At the same time, signal isolation can also eliminate the ground potential difference between communication subsystems and improve the signal's anti-interference ability.

[0044] The controlled device 6 described in the present invention has a built-in RS422 receiving chip, which restores the differential signal to a single-ended signal output by the MCU and directly acts on the communication interface of the controlled device; at the same time, the signal that the controlled device needs to feed back to the processor is converted into a differential signal and transmitted back to the processor through the transmission connection line.

[0045] The working principle of the present invention is as follows:

[0046] Only two groups of SPI and one group of UART transmission modes are used as examples for specific application implementation, and actual patents include but are not limited to this example.

[0047] After the output signals of SPI and UART are output by the processor, they are first isolated by the isolation chips (ISO7220) U95 and U96, and then enter the differential transmission chip MAX3032E to be converted into differential signals. The input signals of SPI and UART are converted into single-ended signals by the differential receiving chip MAX3096E and return to the processor through the isolation chip ISO7220.

[0048] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0049] In the description of this application, it should be noted that the terms "vertical", "horizontal", "inside", "outside", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, or the positions or positional relationships in which the product of the application is usually placed when in use. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0050] In addition, the terms "horizontal", "vertical" and the like do not mean that the components are required to be absolutely horizontal or vertical, but can be slightly tilted. For example, "horizontal" only means that its direction is more horizontal than "vertical", and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0051] In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0052] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the technical principles of the present invention, and these improvements and modifications should also be regarded as within the scope of protection of the present invention.

Claims

1. A device based on board-level wired signal extension transmission, comprising a processor (1), characterized in that: The device also comprises a signal isolation module (2), a first signal transmission module (3), a transmission connection line (4), a second signal transmission module (5) and a controlled device (6); the output end of the processor (1) is connected to the input end of the signal isolation module (2); the output end of the signal isolation module (2) is connected to the input end of the first signal transmission module (3); the first signal transmission module (3) is communicatively connected to the second signal transmission module (5) via the transmission connection line (4); the output end of the second signal transmission module (5) is connected to the controlled device (6); the feedback end of the controlled device (6) is connected to the input end of the first signal transmission module (3); the first signal transmission module (3) is communicatively connected to the second signal transmission module (5) via the transmission connection line (4); and the second signal transmission module (5) is connected to the feedback end of the processor (1) via the signal isolation module (2).

2. The device for extending and transmitting board-level wired signals according to claim 1, characterized in that: The processor (1) includes but is not limited to CPU, MCU, FPGA, DSP or ARM.

3. The device for extending and transmitting board-level wired signals according to claim 1, characterized in that: The signal isolation module (2) comprises an isolation chip U95, wherein a first pin of the isolation chip U95 is connected to VDD_3V3, and the first pin is grounded through a capacitor C792 and also grounded through a capacitor C790, a second pin of the isolation chip U95 is connected to an SPI_CLK terminal through a resistor R614, a third pin of the isolation chip U95 is connected to an SPI_MOSI terminal through a resistor R615, a fourth pin and a fifth pin of the isolation chip U95 are grounded, an eighth pin of the isolation chip U95 is connected to ISO_3V3, and the eighth pin is grounded through a capacitor C789 and also grounded through a capacitor C791, and a seventh pin and a sixth pin of the isolation chip U95 are connected to a first signal transmission module (3); It also includes an isolation chip U96, a first pin of the isolation chip U96 is connected to VDD_3V3, a second pin of the isolation chip U96 is connected to the SPI1_CS terminal via a resistor R612, a third pin of the isolation chip U96 is connected to the UART1_TXD terminal via a resistor R613, a fourth pin and a fifth pin of the isolation chip U96 are grounded, an eighth pin of the isolation chip U96 is connected to ISO_5V, and a seventh pin and a sixth pin of the isolation chip U96 are connected to the first signal transmission module (3).

4. The device for extending and transmitting board-level wired signals according to claim 3, characterized in that: The isolation chip U95 and the isolation chip U96 are of model ISO7220.

5. The device for extending and transmitting board-level wired signals according to claim 1, characterized in that: The first signal transmission module (3) comprises a differential transmission chip U93, wherein the first pin of the differential transmission chip U93 is connected to the seventh pin of the isolation chip U95, the seventh pin of the differential transmission chip U93 is connected to the sixth pin of the isolation chip U95, the fourth pin and the twelfth pin of the differential transmission chip U93 are connected to the ISO_3V3 terminal through resistors R583 and R584 respectively, the ninth pin of the differential transmission chip U93 is connected to the seventh pin of the isolation chip U96, the fifteenth pin of the differential transmission chip U93 is connected to the sixth pin of the isolation chip U96, the eighth pin of the differential transmission chip U93 is grounded, and the tenth pin of the differential transmission chip U93 is grounded. The sixth pin is connected to the ISO_3V3 terminal and is also grounded through the capacitor C793. The second pin and the third pin of the differential transmitting chip U93 are respectively connected to the SPI1_CLK_P terminal and the SPI1_CLK_N terminal. The sixth pin and the fifth pin of the differential transmitting chip U93 are respectively connected to the SPI1_MOSI_P terminal and the SPI1_MOSI_N terminal. The tenth pin and the eleventh pin of the differential transmitting chip U93 are respectively connected to the SPI1_CS_P terminal and the SPI1_C_N terminal. The fourteenth pin and the thirteenth pin of the differential transmitting chip U93 are respectively connected to the UART1_TXD_P terminal and the UART1_TXD_N terminal.

6. The device for extending and transmitting board-level wired signals according to claim 5, characterized in that: The model of the differential transmission chip U93 is MAX3032E.

7. The device for extending and transmitting board-level wired signals according to claim 1, characterized in that: The second signal transmission module (5) comprises a differential receiving chip U102, wherein the fourth pin, the twelfth pin and the sixteenth pin of the differential receiving chip U102 are connected to the ISO_3V3 terminal and are grounded through a capacitor C809, the second pin and the third pin of the differential receiving chip U102 are connected to the SPI1_MISO_P terminal and the SPI1_MISO_N terminal respectively, the sixth pin and the fifth pin of the differential receiving chip U102 are connected to the SPI2_MOSI_P terminal and the SPI2_MOSI_N terminal respectively, and the tenth pin and The eleventh pin is connected to the UART1_RXD_P terminal and the UART1_RXD_N terminal respectively, the fourteenth pin and the thirteenth pin of the differential receiving chip U102 are connected to the UART2_RXD_P terminal and the UART2_RXD_N terminal respectively, the first pin and the seventh pin of the differential receiving chip U102 are connected to the second pin and the third pin of the isolation chip U103 respectively, the ninth pin and the fifteenth pin of the differential receiving chip U102 are connected to the second pin and the third pin of the isolation chip U104 respectively, and the eighth pin of the differential receiving chip U102 is grounded.

8. The device for extending and transmitting board-level wired signals according to claim 7, characterized in that: The model of the differential receiving chip U102 is MAX3096E, and the models of the isolation chip U103 and the isolation chip U104 are both ISO7220.

9. The device for extending and transmitting board-level wired signals according to claim 1, characterized in that: The transmission connection line (4) uses multiple groups of twisted pair wires and shielded layer signal wires, including HR10A series.

10. The device for extending and transmitting board-level wired signals according to claim 1, characterized in that: The controlled device (6) is equipped with a built-in RS422 receiving chip.

Images