Airborne computer interrupt interface circuit and method based on hardware monitoring

Abstract

The invention discloses an airborne computer interrupt interface circuit and method based on hardware monitoring. The airborne computer interrupt interface circuit comprises a processor unit, a programmable logic unit and a peripheral equipment unit. An interrupt application signal line, a control signal line, an address bus and a data bus are connected between the processor unit and the programmable logic unit. And an interrupt application signal line, a control signal line, an address bus and a data bus are connected between the programmable logic unit and each peripheral equipment unit. The method has the advantages that failure of the whole computer caused by interface faults is avoided, and data loss and incapability of executing other tasks are avoided.

Description

Technical Field

[0001] The invention relates to an onboard computer, in particular to an onboard computer interrupt interface circuit and method based on hardware monitoring. Background Art

[0002] As an important indicator of airborne computers, real-time performance is directly related to the working performance of airborne computers and even affects the operation of the entire aircraft. For tasks with high real-time requirements, airborne computers use interrupts to process them. The efficient control of the internal processor and multiple peripheral device interrupt interface circuits is particularly important, which determines the performance of the airborne computer. At present, most of them have the following problems: 1. Interface failure, the interrupt application is always valid, and the processor cannot exit the interrupt service, resulting in failure of the airborne computer; 2. Multiple peripheral devices apply at the same time, and the processor cannot perform interrupt services in an orderly manner, resulting in the loss of important data; 3. Frequent entry into the interrupt service causes the processor to be unable to perform other tasks. Therefore, the reliability of the interrupt interface circuit control is directly related to the function and performance of the airborne computer. Summary of the invention

[0003] The purpose of the present invention is to solve the problems in the prior art and to provide a novel onboard computer interrupt interface circuit and method based on hardware monitoring.

[0004] In order to achieve the above-mentioned purpose, the present invention provides a technical solution: an onboard computer interrupt interface circuit based on hardware monitoring, comprising: a processor unit, a programmable logic unit, and a peripheral device unit; wherein the number of the processor unit is 1, the number of the programmable logic unit is 1, and the number of the peripheral device units is greater than 1; an interrupt request signal line, a control signal line, an address bus, and a data bus are connected between the processor unit and the programmable logic unit; an interrupt request signal line, a control signal line, an address bus, and a data bus are connected between the programmable logic unit and each of the peripheral device units.

[0005] In order to achieve the above-mentioned purpose, the present invention mentions another technical solution: a method of an onboard computer interrupt interface circuit based on hardware monitoring, comprising: the processor unit collects interrupt request signals from each of the peripheral device units of the programmable logic unit; the processor unit skips the faulty peripheral device unit, and determines whether the interrupt request signal of the non-faulty peripheral device unit is valid: if the interrupt request signal is valid, the error count of the peripheral device unit is increased by one, and further determines whether the error count of the peripheral device unit exceeds a preset value: if so, the peripheral device unit is set to a fault and exits the interrupt service; if not, the processor unit reads the data of the peripheral device unit and exits the interrupt service; if the interrupt request signal is invalid, exits the interrupt service.

[0006] As a preferred solution of a method for an onboard computer interrupt interface circuit based on hardware monitoring, the programmable logic unit collects the interrupt request signal of each peripheral device unit and determines whether the interrupt request signal of each peripheral device unit is valid: if so, the interrupt request signal is converted into a square wave signal; if not, the interrupt request signal is converted into a low-level signal; wherein the interrupt request signal of the non-faulty peripheral device unit is configured as follows: the interrupt request signal is valid when there is a falling edge.

[0007] Compared with the prior art, the beneficial effects of the present invention are at least that: not only does it avoid the failure of the entire computer due to interface failure, but it also avoids data loss and the inability to perform other tasks. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a schematic diagram of the structure of the present invention. Figure 2 The figure is a flow chart of the interrupt service method of the processor unit of the present invention. Figure 3 The figure is a flow chart of the interrupt control method of the programmable logic unit of the present invention. Implementation

[0009] The present invention is further described in detail below by means of specific embodiments in combination with the accompanying drawings. It should be noted that the description of these embodiments is used to help understand the present invention, but does not constitute a limitation of the present invention. In addition, the technical features involved in each embodiment of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0010] See also Figure 1 , the figure shows an onboard computer interrupt interface circuit based on hardware monitoring. The onboard computer interrupt interface circuit includes: a processor unit, a programmable logic unit, a peripheral device unit, etc. Among them, the number of the processor unit is 1, the number of the programmable logic unit is 1, and the number of the peripheral device unit is greater than 1.

[0011] The processor unit is the control center of the interrupt interface circuit. The processor unit has RAM, watchdog, clock, etc. The processor unit is used to implement interrupt service control, query the application status of peripheral device interrupt signal, complete the data communication and control of peripheral device units that need interrupt service, etc. In one embodiment, the processor unit can be selected from Freescale's MPC5200B.

[0012] The programmable logic unit is used to realize the communication between the interrupt control interface of the processor unit and the peripheral device unit, collect the interrupt request signal of the peripheral device unit, cooperate with the processor unit to select the peripheral device unit that needs to be served, and complete the data communication and control of the peripheral device unit. In one embodiment, the programmable logic unit can use FPGA circuits such as EP1C6F256I8 of Altera. The interrupt signal of the programmable unit is converted from parallel input to serial output.

[0013] The peripheral device unit is a communication interface between the central alarm device and other airborne devices. The peripheral device unit is used to output an interrupt request signal to the programmable logic unit, accept the control of the programmable logic unit, and complete data communication and control. In one embodiment, the peripheral device unit can use DEI1016 or other interrupt interface circuits.

[0014] See also Figure 2 , shown in the figure is a flow chart of the interrupt service method of the processor unit. The interrupt service method of the processor unit includes: collecting interrupt request signals from each of the peripheral device units of the programmable logic unit; skipping the faulty peripheral device unit, and judging whether the interrupt request signal of the non-faulty peripheral device unit is valid: if the interrupt request signal is valid, the error count of the peripheral device unit is increased by one, and further judging whether the error count of the peripheral device unit exceeds the preset value: if so, the peripheral device unit is set as a fault and the interrupt service is exited; if not, the processor unit reads the data of the peripheral device unit and exits the interrupt service. In one embodiment, the preset value can be set to 5. If the interrupt request signal is invalid, the interrupt service is exited.

[0015] See also Figure 3 , the figure shows a flow chart of the interrupt control method of the programmable logic unit. The interrupt control method of the programmable logic unit includes: collecting the interrupt request signal of each of the peripheral device units; judging whether the interrupt request signal of each of the peripheral device units is valid: if so, the programmable logic unit converts the interrupt request signal into a square wave signal; if not, the programmable logic unit converts the interrupt request signal into a low-level signal. Among them, the interrupt request signal of the non-faulty peripheral device unit is configured as follows: the interrupt request signal is valid when there is a falling edge.

[0016] Through application verification, the above circuit and method are compatible with various airborne computer interfaces, work stably and efficiently, and are suitable for solving the control problem of the interrupt control interface between the processor unit of the airborne computer and multiple peripheral device units.

[0017] The above only expresses the implementation mode of the present invention, and its description is relatively specific and detailed, but it cannot be understood as limiting the scope of the invention patent. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be based on the attached claims.

Claims

1. An onboard computer interrupt interface circuit based on hardware monitoring, characterized in that: include: A processor unit, a programmable logic unit, and a peripheral device unit; wherein the number of the processor unit is 1, the number of the programmable logic unit is 1, and the number of the peripheral device units is greater than 1; an interrupt request signal line, a control signal line, an address bus, and a data bus are connected between the processor unit and the programmable logic unit; an interrupt request signal line, a control signal line, an address bus, and a data bus are connected between the programmable logic unit and each of the peripheral device units.

2. The method of the onboard computer interrupt interface circuit based on hardware monitoring as claimed in claim 1, characterized in that: include: The processor unit collects interrupt request signals from each peripheral device unit of the programmable logic unit; the processor unit skips the faulty peripheral device unit and determines whether the interrupt request signal of the non-faulty peripheral device unit is valid: if the interrupt request signal is valid, the error count of the peripheral device unit is increased by one, and further determines whether the error count of the peripheral device unit exceeds a preset value: if so, the peripheral device unit is set as a fault and the interrupt service is exited; if not, the processor unit reads the data of the peripheral device unit and exits the interrupt service; If the interrupt request signal is invalid, exit the interrupt service.

3. The method of interrupting an onboard computer interface circuit based on hardware monitoring according to claim 2, characterized in that: The programmable logic unit collects the interrupt request signal of each of the peripheral device units, and determines whether the interrupt request signal of each of the peripheral device units is valid: if so, the interrupt request signal is converted into a square wave signal; if not, the interrupt request signal is converted into a low-level signal; wherein the interrupt request signal of the non-faulty peripheral device unit is configured as follows: the interrupt request signal is valid when there is a falling edge.

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