GPIO interface circuit and configuration method and configuration device thereof

Abstract

The invention discloses a GPIO (General Purpose Input / Output) interface circuit as well as a configuration method and a configuration device thereof, and belongs to the technical field of circuits. The GPIO interface circuit comprises a connecting pin; the input end of the detection module is connected with the connecting pin, and the output end of the detection module is used for outputting the level at the connecting pin; the configuration state switching module is respectively connected with the connecting pin and the detection module and is used for switching the configuration state of the GPIO interface circuit under the condition that the level at the connecting pin is the first level until the level at the connecting pin is switched from the first level to the second level or to the third level, and the configuration state switching module is used for switching the configuration state of the GPIO interface circuit when the level at the connecting pin is the second level or the third level. The first level is higher than the second level and lower than the third level.

Description

Technical Field

[0001] The present application belongs to the field of circuit technology, and specifically relates to a GPIO interface circuit and a configuration method and a configuration device thereof. Background Art

[0002] General-purpose input / output (GPIO) is a general-purpose digital input / output port. In embedded systems, GPIO is designed as a flexible pin that can be configured as input or output to meet different application requirements. The control device and the controlled device can be connected through the GPIO interface circuit to achieve control and information exchange between the devices.

[0003] In order to achieve accurate transmission of information, the connection pins in the GPIO interface circuit need to accurately output high or low levels. If the level output by the connection pins in the GPIO interface circuit is between low and high levels, it will be judged as an uncertain state, that is, a half-high level. If the connection pins maintain a half-high level, it will affect the reliability of the device where the GPIO interface circuit is located. Summary of the invention

[0004] The purpose of the embodiments of the present application is to provide a GPIO interface circuit and a configuration method and a configuration device thereof, which can solve the problem that if the connection pin maintains a half-high level operation, the reliability of the device where the GPIO interface circuit is located will be affected.

[0005] In a first aspect, an embodiment of the present application provides a GPIO interface circuit, including: a connecting pin; a detection module, an input end of the detection module is connected to the connecting pin, and an output end of the detection module is used to output the level at the connecting pin; a configuration state switching module, the configuration state switching module is respectively connected to the connecting pin and the detection module, and is used to switch the configuration state of the GPIO interface circuit when the level at the connecting pin is a first level, until the level at the connecting pin is switched from the first level to the second level or to the third level, and the first level is a level higher than the second level and lower than the third level.

[0006] In a second aspect, an embodiment of the present application provides a configuration method for a GPIO interface circuit as described in any one of the first aspects, the configuration method comprising: obtaining the level at a connection pin; when the level at the connection pin is a first level, switching the configuration state of the GPIO interface circuit until the level at the connection pin switches from the first level to the second level or to the third level; wherein the first level is a level higher than the second level and lower than the third level.

[0007] In a third aspect, an embodiment of the present application provides a configuration device for a GPIO interface circuit as in any one of the first aspects, the configuration device comprising: an acquisition module for acquiring the level at a connection pin; a switching module for switching the configuration state of the GPIO interface circuit when the level at the connection pin is a first level, until the level at the connection pin switches from the first level to the second level or to the third level; wherein the first level is a level higher than the second level and lower than the third level.

[0008] In a fourth aspect, an embodiment of the present application provides an electronic device, which includes a processor and a memory, wherein the memory stores programs or instructions that can be executed on the processor, and when the programs or instructions are executed by the processor, the steps of the method of the second aspect are implemented.

[0009] In a fifth aspect, an embodiment of the present application provides a readable storage medium, on which a program or instruction is stored, and when the program or instruction is executed by a processor, the steps of the method in the second aspect are implemented.

[0010] In a sixth aspect, an embodiment of the present application provides a chip, the chip including a processor and a communication interface, the communication interface and the processor are coupled, and the processor is used to run programs or instructions to implement the method of the second aspect.

[0011] In a seventh aspect, an embodiment of the present application provides a computer program product, which is stored in a storage medium and is executed by at least one processor to implement the method of the second aspect.

[0012] In an embodiment of the present application, a GPIO interface circuit is proposed, and the GPIO interface circuit includes a connection pin, a detection module, and a configuration state switching module. In this process, the detection module can be used to directly detect whether the level at the connection pin is the first level, that is, to detect whether the level at the connection pin in the GPIO interface circuit is a half-high level, and when the level at the connection pin is the first level, the configuration state of the GPIO interface circuit is switched through the configuration state switching module, so that the level at the connection pin changes to the second level or the third level, thereby getting rid of the influence of the half-high level, thereby improving the reliability of the device where the GPIO interface circuit is located. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a schematic diagram for identifying high level and low level in the related technical solution;

[0014] Figure 2 It is a topological diagram of the first module and the second module in the related technical solution when there is a half-high level;

[0015] Figure 3is a topological schematic diagram of the first switch tube and the second switch tube in the related technical solution when there is a half-high level;

[0016] Figure 4 It is one of the topological schematic diagrams of the GPIO interface circuit provided in some embodiments of the present application;

[0017] Figure 5 This is the second topological schematic diagram of the GPIO interface circuit provided in some embodiments of the present application;

[0018] Figure 6 It is a topological schematic diagram of the GPIO interface circuit in the related technical solution;

[0019] Figure 7 It is one of the flowcharts of the configuration method provided in some embodiments of the present application;

[0020] Figure 8 This is the second flowchart of the configuration method provided in some embodiments of the present application;

[0021] Fig. 9 is a schematic block diagram of a configuration device provided in some embodiments of the present application;

[0022] Fig.10 is a schematic block diagram of an electronic device in an embodiment of the present application;

[0023] Fig.11 It is a schematic diagram of the hardware structure of the electronic device in the embodiment of the present application.

[0024] Attached Figure 2 and Figure 3 Markings:

[0025] 202' is a first module, 204' is a second module, 302' is a first switch tube, and 304' is a second switch tube.

[0026] Attached Figures 4 to 6 Markings:

[0027] PAD connecting pin, R1 first resistor, R2 second resistor, R3 third resistor, R4 fourth resistor, R5 fifth resistor, R6 sixth resistor, R7 seventh resistor, R8 eighth resistor, 402 detection module, 4022 first comparison circuit, 4024 second comparison circuit, 4026 analog-to-digital converter, U AND gate, D1 first comparator, D2 second comparator, 404 configuration state switching module, 4042 output control module, 4044 input control module, 4046 configuration module, 4048 resistance control module, DVDD first power supply. DETAILED DESCRIPTION

[0028] The embodiments of the present application will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be construed as limitations on the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

[0029] The term "first" or "second" in the specification and claims of this application may include one or more of the features explicitly or implicitly. In the description of this application, unless otherwise specified, "plurality" means two or more. In addition, "and / or" in the specification and claims means at least one of the connected objects, and the character " / " generally means that the objects connected before and after are in an "or" relationship.

[0030] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0031] like Figure 1 As shown, the second level is a low level, and the third level is a high level, wherein the recognition range of the high level is greater than or equal to 0.7Vset, and the recognition range of the low level is less than or equal to 0.3Vset, and Vset is a set voltage value. If the level at the connection pin in the GPIO interface circuit is between 0.3Vset and 0.7set, it is in an uncertain state, that is, a half-high level, and there is a probability that it will be recognized as a high level or a low level, which may easily cause signal misjudgment.

[0032] Specifically, Figure 2 As shown, a half-high level appears as the input V of the first module 202' and the second module 204' IN When the two switches in the first module 202' and the second module 204' are turned on, the power supply V DD If the connection is connected to the ground, the large leakage current generated for a long time will cause V OUT The reliability of the terminal is reduced.

[0033] Similarly, if Figure 3 As shown, when a half-high level appears as the input V of the first switch tube 302' and the second switch tube 304' INWhen the first switch tube 302' and the second switch tube 304' are turned on at the same time, the power supply V DD If the connection is connected to the ground, the large leakage current generated for a long time will cause V OUT The reliability of the terminal is reduced.

[0034] In order to reduce the situation where the level output by the connection pins in the GPIO interface circuit is uncertain, an oscilloscope is needed to perform signal inspection. The signal inspection requires reserving test points on the circuit board. The setting of the test points will affect the signal quality of the transmission signal and occupy a large area on the circuit board, affecting the flexibility of the circuit board routing and the configuration efficiency of the GPIO interface circuit.

[0035] The GPIO interface circuit and its configuration method and configuration device provided in the embodiments of the present application are described in detail below through specific embodiments and their application scenarios in conjunction with the accompanying drawings.

[0036] In some embodiments of the present application, Figure 4 and Figure 5 As shown, a GPIO interface circuit is proposed, including: a connecting pin PAD; a detection module 402, the input end of the detection module 402 is connected to the connecting pin PAD, and the output end of the detection module 402 is used to output the level at the connecting pin PAD; a configuration state switching module 404, the configuration state switching module 404 is respectively connected to the connecting pin PAD and the detection module 402, and is used to switch the configuration state of the GPIO interface circuit when the level at the connecting pin PAD is a first level, until the level at the connecting pin PAD is switched from the first level to the second level or to the third level, and the first level is a level higher than the second level and lower than the third level.

[0037] The connecting pin PAD is a pin used to connect the control device and the controlled device. The control device and the controlled device are connected through the pin to realize the input and output of information.

[0038] The configuration state of the GPIO interface circuit can be understood as the working mode of the GPIO interface circuit.

[0039] In an embodiment of the present application, a GPIO interface circuit is proposed, and the GPIO interface circuit includes a connection pin PAD, a detection module 402, and a configuration state switching module 404. In this process, the detection module 402 can be used to directly detect whether the level at the connection pin PAD is the first level, that is, to detect whether the level at the connection pin PAD in the GPIO interface circuit is a half-high level, and when the level at the connection pin PAD is the first level, the configuration state of the GPIO interface circuit is switched by the configuration state switching module 404, so that the level at the connection pin PAD changes to the second level or the third level, thereby getting rid of the influence of the half-high level, thereby improving the reliability of the device where the GPIO interface circuit is located.

[0040] In addition, since the detection module 402 can be used to directly detect whether the level at the connection pin PAD is the first level, there is no need to reserve test points on the circuit board where the GPIO interface circuit is located, and use an oscilloscope to perform signal inspection. Obviously, in this process, the problems caused by the reserved test points can be improved. In addition, the setting of the configuration state switching module 404 can realize the automatic configuration of the GPIO interface circuit, and there is no need to configure the GPIO interface circuit according to the result of the signal inspection by the oscilloscope, thereby improving the configuration efficiency.

[0041] In some embodiments of the present application, the configuration state of the GPIO interface circuit includes a first output state, a second output state, a first input state, a second input state and a third input state, and the configuration state switching module 404 includes: an output control module 4042, the output end of the output control module 4042 is connected to the connection pin PAD; an input control module 4044, the input end of the input control module 4044 is connected to the connection pin PAD; a configuration module 4046, the configuration module 4046 includes a first resistor R1 and a second resistor R2, the first end of the first resistor R1 is used to be connected to the first power supply DVDD, the second end of the first resistor R1 is connected to the connection pin PAD, the first end of the second resistor R2 is connected to the connection pin PAD, and the second end of the second resistor R2 is used to ground VSS; a resistance control module 4048, respectively connected to the first resistor R1 and the second resistor R2. A resistor R1 is connected to a second resistor R2; wherein, in a first output state, the output control module 4042 outputs a third level via the connection pin PAD; in a second output state, the output control module 4042 outputs a second level via the connection pin PAD; in a first input state, the input control module 4044 inputs a signal via the connection pin PAD, and the resistance control module 4048 controls the first resistor R1 to be switched in and the second resistor R2 to be switched out; in a second input state, the input control module 4044 inputs a signal via the connection pin PAD, and the resistance control module 4048 controls the first resistor R1 to be switched out and the second resistor R2 to be switched in; in a third input state, the input control module 4044 inputs a signal via the connection pin PAD, and the resistance control module 4048 controls the first resistor R1 and the second resistor R2 to be switched out.

[0042] In this embodiment, the GPIO interface circuit is an input or output circuit, which has an input mode and an output mode, wherein the input mode includes a first input state, a second input state and a third input state, and the output mode includes a first output state and a second output state. In the input mode, information collection can be realized, and in the output mode, control of the controlled device can be realized.

[0043] The configuration state switching module 404 includes an output control module 4042, an input control module 4044, a configuration module 4046, and a resistance control module 4048. The settings of the output control module 4042 and the input control module 4044 can directly control whether the GPIO interface circuit operates in the output mode or the input mode, and the resistance control module 4048 can control the switching in and out of the first resistor R1 and the second resistor R2, so that the GPIO interface circuit can switch between the first input state, the second input state, and the third input state.

[0044] When the output control module 4042 is enabled, the GPIO interface circuit is controlled to operate in output mode. After the output control module 4042 is enabled, it is also used to select the configuration state of the GPIO interface circuit to be the first output state or the second output state.

[0045] Among them, when the input control module 4044 is enabled, the mode of controlling the operation of the GPIO interface circuit is the input mode. After the input control module 4044 is enabled, it is also used to select the configuration state of the GPIO interface circuit as the first input state, the second input state or the third input state.

[0046] The resistance control module 4048 is used to control one or both of the first resistor R1 and / or the second resistor R2 to switch into the GPIO interface circuit, thereby realizing switching among the first input state, the second input state and the third input state.

[0047] The output control module 4042 has a first input terminal A. In the first output state or the second output state, the output control module 4042 outputs the third level or the second level when a signal is input to the first input terminal A.

[0048] Specifically, in the first output state, if a signal is input to the first input terminal A, the output control module 4042 outputs a third level through the connecting pin PAD.

[0049] Specifically, in the second output state, if a signal is input to the first input terminal A, the output control module 4042 outputs a second level through the connecting pin PAD.

[0050] The input control module 4044 has a first input terminal Y, and the resistance control module 4048 has a first control terminal PE and a second control terminal PS, wherein the first control terminal PE is used to control the switching in and out of the first resistor R1, and the second control terminal PS is used to control the switching in and out of the second resistor R2.

[0051] Specifically, in the first input state, the input control module 4044 responds to the signal input by the first input terminal Y, and inputs the signal through the connection pin PAD, and the resistance control module 4048 responds to the signal input by the first control terminal PE and the second control terminal PS, and controls the first resistor R1 to be switched in and the second resistor R2 to be switched out. Among them, controlling the first resistor R1 to be switched in can be understood as connecting the first resistor R1 between the first power supply and the connection pin PAD, and similarly, switching out the second resistor R2 can be understood as removing the second resistor R2 from the connection pin PAD and the ground. In this state, only the first resistor R1 is connected in series in the GPIO interface circuit, and the second resistor R2 is not connected in the GPIO interface circuit. This input state can be understood as an input pull-up state.

[0052] In the second input state, the input control module 4044 responds to the signal input by the first input terminal Y, inputs the signal through the connection pin PAD, and the resistance control module 4048 responds to the signal input by the first control terminal PE and the second control terminal PS, and controls the first resistor R1 to be cut out and the second resistor R2 to be cut in. Among them, controlling the first resistor R1 to be cut out can be understood as removing the first resistor R1 from between the first power supply and the connection pin PAD, and similarly, the second resistor R2 to be cut in can be understood as connecting the second resistor R2 between the connection pin PAD and the ground. In this state, only the second resistor R2 is connected in series in the GPIO interface circuit, and the first resistor R1 is not connected in the GPIO interface circuit. This input state can be understood as an input pull-down state.

[0053] In the third input state, the input control module 4044 responds to the signal input by the first input terminal Y, inputs the signal through the connection pin PAD, and the resistance control module 4048 responds to the signal input by the first control terminal PE and the second control terminal PS, and controls the first resistor R1 and the second resistor R2 to be cut out. Among them, controlling the first resistor R1 to be cut out can be understood as removing the first resistor R1 from between the first power supply and the connection pin PAD, and similarly, cutting out the second resistor R2 can be understood as removing the second resistor R2 from between the connection pin PAD and the ground. In this state, the first resistor R1 and the second resistor R2 are not connected to the GPIO interface circuit, and this input state can be understood as an input floating state.

[0054] In this embodiment, the output control module 4042, the input control module 4044 and the resistance control module 4048 are used to automatically adjust the configuration state of the GPIO interface circuit, and the correct configuration state of the GPIO interface circuit is selected for the actual working conditions, so that the level at the connection pin PAD is switched from the first level to the second level, thereby eliminating the impact of large leakage current.

[0055] In some embodiments of the present application, the detection module 402 includes: a first comparison circuit 4022, the input end of the first comparison circuit 4022 is connected to the connection pin PAD, when the level at the connection pin PAD is lower than the third level, the first comparison circuit 4022 outputs a high level signal, when the level at the connection pin PAD is equal to or higher than the third level, the first comparison circuit 4022 outputs a low level signal; a second comparison circuit 4024, the input end of the second comparison circuit 4024 is connected to the connection pin PAD, when the level at the connection pin PAD is low When the level at the connection pin PAD is higher than the second level, the second comparison circuit 4024 outputs a high level signal; and an AND gate U, wherein the first input terminal of the AND gate U is connected to the output terminal of the first comparison circuit 4022, and the second input terminal of the AND gate U is connected to the output terminal of the second comparison circuit 4024; wherein, when the output terminal of the first comparison circuit 4022 and the output terminal of the second comparison circuit 4024 simultaneously output high level signals, the level at the connection pin PAD is the first level.

[0056] In this embodiment, as can be seen from the above, the detection module 402 is used to detect the level at the connection pin PAD, so as to determine whether the level at the connection pin PAD is in an uncertain state based on the level at the connection pin PAD, and the uncertain state is determined by comparing the level at the connection pin PAD with the third level and the second level respectively.

[0057] Based on this, the detection module 402 includes a first comparison circuit 4022 and a second comparison circuit 4024, wherein the first comparison circuit 4022 is used to determine whether the level at the connection pin PAD is lower than the third level, and the second comparison circuit 4024 is used to determine whether the level at the connection pin PAD is higher than the second level, and then the comparison results of the first comparison circuit 4022 and the second comparison circuit 4024 are respectively input into the two input terminals of the AND gate U, and the AND gate U is used to determine whether the level at the connection pin PAD is the first level.

[0058] In this process, the hardware circuit can be used to directly determine whether the level at the connection pin PAD is the first level, without running a software program to determine. Therefore, if the level at the connection pin PAD is the first level, the above situation can be detected in time, so that the configuration state of the GPIO interface circuit can be switched in time, thereby ensuring the reliability of the GPIO interface circuit.

[0059] In some embodiments, the recognition ranges of the second level and the third level can be selected according to actual use requirements.

[0060] In some embodiments, the recognition range of the third level is greater than or equal to 0.7 DVDD, and the recognition range of the second level is less than or equal to 0.3 DVDD, wherein DVDD is the output voltage of the first power supply.

[0061] If the level at the connection pin PAD is 0.9DVDD, 0.9DVDD is greater than 0.7DVDD. At this time, the first comparison circuit 4022 outputs a low level signal, the second comparison circuit 4024 outputs a high level signal, and when the AND gate U inputs a low level signal and a high level signal at the same time, the output terminal B outputs a low level signal.

[0062] If the level at the connection pin PAD is 0.2DVDD, 0.2DVDD is less than 0.7DVDD. At this time, the first comparison circuit 4022 outputs a high level signal, 0.2DVDD is less than 0.3DVDD, and the second comparison circuit 4024 outputs a low level signal. When the AND gate U inputs a low level signal and a high level signal, the output terminal B outputs a low level signal.

[0063] If the level at the connection pin PAD is 0.5DVDD, 0.5DVDD is less than 0.7DVDD. At this time, the first comparison circuit 4022 outputs a high level signal, 0.5DVDD is greater than 0.3DVDD, and the second comparison circuit 4024 outputs a high level signal. When the AND gate U inputs a high level signal at the same time, the output terminal B outputs a high level signal. At this time, the level at the connection pin PAD is considered to be the first level.

[0064] In some embodiments of the present application, the first comparison circuit 4022 includes: a third resistor R3, a first end of the third resistor R3 is connected to the connecting pin PAD; a fourth resistor R4, a first end of the fourth resistor R4 is connected to the second end of the third resistor R3, and the second end of the fourth resistor R4 is grounded; a first comparator D1, a negative phase input end of the first comparator D1 is connected to the first end of the fourth resistor R4, and a positive phase input end of the first comparator D1 is used to input a voltage signal corresponding to the third level; and / or the second comparison circuit 4024 includes: a fifth resistor R5, a first end of the fifth resistor R5 is connected to the connecting pin PAD; a sixth resistor R6, a first end of the sixth resistor R6 is connected to the second end of the fifth resistor R5, and the second end of the sixth resistor R6 is grounded; a second comparator D2, a positive phase input end of the second comparator D2 is connected to the first end of the sixth resistor R6, and a negative phase input end of the second comparator D2 is used to input a voltage signal corresponding to the second level.

[0065] In this embodiment, a voltage divider circuit formed by a third resistor R3 and a fourth resistor R4 is used to collect the level at the connection pin PAD in the form of a voltage and input it to the negative input terminal of the first comparator D1. At the same time, a voltage signal corresponding to the third level is input to the positive input terminal of the first comparator D1. At this time, the first comparator D1 can compare the voltage corresponding to the level at the connection pin PAD with the voltage signal corresponding to the third level. If the voltage corresponding to the level at the connection pin PAD is lower than the voltage signal corresponding to the third level, the first comparator D1 outputs a high level signal.

[0066] Similarly, the voltage divider circuit formed by the fifth resistor R5 and the sixth resistor R6 is used to collect the level at the connection pin PAD in the form of voltage and input it to the positive input terminal of the second comparator D2. At the same time, the negative input terminal of the second comparator D2 inputs the voltage signal corresponding to the second level. At this time, the second comparator D2 can compare the voltage corresponding to the level at the connection pin PAD with the voltage signal corresponding to the second level. If the voltage corresponding to the level at the connection pin PAD is higher than the voltage signal corresponding to the second level, the second comparator D2 outputs a high level signal.

[0067] In this process, the comparison result between the level at the connection pin PAD, the second level and the third level is directly determined by using the third resistor R3, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, the first comparator D1 and the second comparator D2, without running a software program to determine, thereby ensuring the reliability of the GPIO interface circuit.

[0068] Exemplarily, the voltage signal corresponding to the third level is represented by VREF1, where VREF1=0.7DVDD, and the voltage signal corresponding to the second level is represented by VREF2, where VREF2=0.3DVDD.

[0069] Among them, VREF1 and VREF2 can be generated by a circuit in the control device, or by an external power supply, which will not be described in detail here.

[0070] In some embodiments of the present application, the detection module 402 includes: an analog-to-digital converter 4026, the input end of the analog-to-digital converter 4026 is connected to the connection pin PAD, and the output end of the analog-to-digital converter 4026 is used to output the level at the connection pin PAD.

[0071] In this embodiment, a detection circuit is provided in the analog-to-digital converter 4026, which can detect analog signals, and the analog-to-digital converter 4026 is used to detect analog voltage signals, convert them into digital signals, and store them in a register. The accuracy of the analog-to-digital converter 4026 in detecting voltage signals is limited by the number of detection bits of the analog-to-digital converter 4026, wherein the number of detection bits is generally above 8 bits, and the higher the number of bits, the higher the detection accuracy of the analog-to-digital converter 4026.

[0072] Based on this, when the input end of the analog-to-digital converter 4026 is connected to the connecting pin PAD, the level at the connecting pin PAD can be directly detected and output. Obviously, fewer components can be used to realize the detection of the level at the connecting pin PAD, thereby reducing the cost of the GPIO interface circuit.

[0073] In some embodiments of the present application, the analog-to-digital converter 4026 also has a power supply end. When the voltage input to the power supply end is less than the output voltage of the first power supply, the detection module 402 also includes: a seventh resistor R7, which is connected in series between the input end of the analog-to-digital converter 4026 and the connecting pin PAD, and the first end of the seventh resistor R7 is connected to the connecting pin PAD; an eighth resistor R8, the first end of the eighth resistor R8 is connected to the second end of the seventh resistor R7, and the second end of the eighth resistor R8 is grounded; wherein, the output voltage of the first power supply at the voltage divided value of the eighth resistor R8 is less than or equal to the voltage input to the power supply end.

[0074] In this embodiment, the seventh resistor R7 and the eighth resistor R8 are provided so as to form a voltage divider circuit, thereby reducing the voltage input to the analog-to-digital converter 4026, thereby ensuring the detection accuracy of the level at the connection pin PAD.

[0075] Specifically, when the output voltage of the first power supply is DVDD, the voltage division value of the output voltage of the first power supply at the eighth resistor R8 is:

[0076] VREF3=R81×DVDD / (R71+R81)

[0077] Among them, VREF3 is the maximum value of the voltage input to the power supply end, R71 is the resistance value of the seventh resistor R7, R81 is the resistance value of the eighth resistor R8, and DVDD is the output voltage of the first power supply.

[0078] Specifically, if Vpad represents the level at the connection pin PAD, a data (data) is obtained by conversion by the analog-to-digital converter 4026, wherein the expression formula of Vpad is:

[0079] Vadc=R81×Vpad / (R71+R81)

[0080] Wherein, Vadc is the voltage at the input terminal of the analog-to-digital converter 4026.

[0081] After obtaining a data, the level at the connection pin PAD can be obtained through data restoration, and its expression is:

[0082] Vpad=(R71+R81)data / R81

[0083] Figure 6 is a topological diagram of a GPIO interface circuit in a related technical solution, such as Figure 6 As shown, the GPIO interface circuit proposed in the present application is newly added with a detection circuit compared with the GPIO interface circuit proposed in the related technical solution, thereby realizing the detection of the level at the connection pin PAD.

[0084] In some embodiments of the present application, Figure 7 As shown, a configuration method is proposed for a GPIO interface circuit as described above, and the configuration method includes:

[0085] Step 702, obtaining the level at the connection pin.

[0086] Step 704 , when the level at the connection pin is the first level, switch the configuration state of the GPIO interface circuit until the level at the connection pin is switched from the first level to the second level or to the third level.

[0087] The first level is a level higher than the second level and lower than the third level.

[0088] In this embodiment, the level at the connection pin can be obtained and compared with the first level. If the level at the connection pin is the first level, the configuration state of the GPIO interface circuit is switched to get rid of the influence of the half-high level, thereby improving the reliability of the device where the GPIO interface circuit is located.

[0089] Since it is possible to directly detect whether the level at the connection pin PAD is the first level, there is no need to reserve test points on the circuit board where the GPIO interface circuit is located and use an oscilloscope to perform signal inspection. Obviously, in this process, the problems caused by the reserved test points can be improved. In addition, the automatic configuration of the GPIO interface circuit can be realized, and there is no need to configure the GPIO interface circuit according to the result of the signal inspection by the oscilloscope, thereby improving the configuration efficiency.

[0090] In some embodiments of the present application, when the level at the connection pin is a first level, the configuration state of the GPIO interface circuit is switched until the level at the connection pin is switched from the first level to the second level or to the third level, specifically including: when the level at the connection pin is the first level, a first configuration state sequence is acquired, the first configuration state sequence is a sequence determined according to the first output state, the second output state, the first input state, the second input state and the third input state; based on the first configuration state sequence, the configuration state of the GPIO interface circuit is switched until the level at the connection pin is switched from the first level to the second level or to the third level; wherein, in the first output state, the output control module outputs the third level through the connection pin; in the second output state, the output control module outputs the second level through the connection pin; in the first input state, the input control module inputs a signal through the connection pin, and the resistance control module controls the first resistor to be switched in and the second resistor to be switched out; in the second input state, the input control module inputs a signal through the connection pin, and the resistance control module controls the first resistor to be switched out and the second resistor to be switched in; in the third input state, the input control module inputs a signal through the connection pin, and the resistance control module controls the first resistor to be switched out and the second resistor to be switched in.

[0091] In this embodiment, the configuration state of the GPIO interface circuit includes a first output state, a second output state, a first input state, a second input state and a third input state. After determining the first output state, the second output state, the first input state, the second input state and the third input state, a first configuration state sequence can be constructed in the order of the first output state, the second output state, the first input state, the second input state and the third input state, and the configuration state of the GPIO interface circuit is switched according to the first configuration state sequence until the level at the connection pin is switched from the first level to the second level. In this process, the configuration state of the GPIO interface circuit can be switched according to the pre-constructed first configuration state sequence, thereby realizing automatic matching of the configuration state of the GPIO interface circuit and improving configuration efficiency.

[0092] Specifically, in the process of switching the configuration state of the GPIO interface circuit according to the first configuration state sequence, the states can be switched one by one, so as to find the correct configuration state.

[0093] In some embodiments of the present application, the first configuration state sequence is a first input state, a second input state, a third input state, a first output state, and a second output state.

[0094] In some embodiments of the present application, the GPIO interface circuit can be set in a master device or a slave device, wherein the master device can be understood as a control device and the slave device can be understood as a controlled device. The configuration status between the master device and the slave device is shown in Table 1.

[0095] Table 1

[0096]

[0097] Among them, √ indicates a state of no leakage, and × indicates a state of leakage.

[0098] In this embodiment, the configuration state of the GPIO interface circuit may be switched based on the configuration state shown in Table 1 until the level at the connection pin is switched from the first level to the second level or to the third level.

[0099] In some embodiments of the present application, Figure 8 As shown, the configuration method includes:

[0100] Step 802, detecting the state of the current signal.

[0101] Among them, the state of the current signal is also the state of the output end of the AND gate.

[0102] Step 804, whether the state of the output terminal of the AND gate is 1, if the judgment result is yes, execute step 806, if the judgment result is no, execute step 808.

[0103] Among them, the state of the output end of the AND gate is 1, which can be understood as that high-level signals are input to the two input ends of the AND gate at the same time. At this time, the output end of the AND gate outputs a high-level signal.

[0104] Step 806, start to traverse the five configuration states of GPIO in sequence.

[0105] Among them, the five configuration states of GPIO are the first output state, the second output state, the first input state, the second input state and the third input state in this application.

[0106] Step 808: Determine that the configuration status is correct.

[0107] The correct configuration state is the configuration state of the GPIO interface circuit after the level at the connection pin is switched from the first level to the second level.

[0108] The configuration method provided in the embodiment of the present application can be executed by a subject to configure a device. In the embodiment of the present application, the configuration device provided in the embodiment of the present application is described by taking a configuration device executing the configuration method as an example.

[0109] In some embodiments of the present application, Fig. 9 As shown, a configuration device 900 is proposed, which is used for a GPIO interface circuit as any one of the above items, and the configuration device 900 includes: an acquisition module 902, which is used to obtain the level at the connection pin; a switching module 904, which is used to switch the configuration state of the GPIO interface circuit when the level at the connection pin is a first level, until the level at the connection pin is switched from the first level to the second level or to the third level; wherein the first level is a level higher than the second level and lower than the third level.

[0110] In this embodiment, the level at the connection pin can be obtained and compared with the first level. If the level at the connection pin is the first level, the configuration state of the GPIO interface circuit is switched.

[0111] This can get rid of the influence brought by the half-high level, thereby improving the reliability of the device where the GPIO interface circuit is located.

[0112] Since it is possible to directly detect whether the level at the connection pin PAD is the first level, there is no need to reserve test points on the circuit board where the GPIO interface circuit is located and use an oscilloscope to perform signal inspection. Obviously, in this process, the problems caused by the reserved test points can be improved. In addition, the automatic configuration of the GPIO interface circuit can be realized, and there is no need to configure the GPIO interface circuit according to the result of the signal inspection by the oscilloscope, thereby improving the configuration efficiency.

[0113] In some embodiments of the present application, the switching module 904 is specifically used to: when the level at the connection pin is the first level, obtain a first configuration state sequence, the first configuration state sequence is a sequence determined according to the first output state, the second output state, the first input state, the second input state and the third input state; switch the configuration state of the GPIO interface circuit based on the first configuration state sequence until the level at the connection pin is switched from the first level to the second level or to the third level; wherein, in the first output state, the output control module outputs the third level through the connection pin; in the second output state, the output control module outputs the second level through the connection pin; in the first input state, the input control module inputs a signal through the connection pin, and the resistance control module controls the first resistor to be cut in and the second resistor to be cut out; in the second input state, the input control module inputs a signal through the connection pin, and the resistance control module controls the first resistor to be cut out and the second resistor to be cut in; in the third input state, the input control module inputs a signal through the connection pin, and the resistance control module controls the first resistor to be cut out and the second resistor to be cut in.

[0114] The configuration device in the embodiment of the present application can be an electronic device, or a component in the electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal, or it can be other devices other than a terminal. Exemplarily, the electronic device can be a mobile phone, a tablet computer, a laptop computer, a PDA, a vehicle-mounted electronic device, a mobile Internet device (Mobile Internet Device, MID), an augmented reality (augmented reality, AR) / virtual reality (virtual reality, VR) device, a robot, a wearable device, an ultra-mobile personal computer (ultra-mobile personal computer, UMPC), a netbook or a personal digital assistant (personal digital assistant, PDA), etc., and can also be a server, a network attached storage (Network Attached Storage, NAS), a personal computer (personal computer, PC), a television (television, TV), a teller machine or a self-service machine, etc., which is not specifically limited in the embodiment of the present application.

[0115] The configuration device in the embodiment of the present application may be a device having an operating system. The operating system may be an Android operating system, an IOS operating system, or other possible operating systems, which are not specifically limited in the embodiment of the present application.

[0116] The configuration device provided in the embodiment of the present application can achieve Figure 7 The various processes implemented by the configuration method embodiment can achieve the same technical effect. To avoid repetition, they will not be described here.

[0117] like Fig.10 As shown, an embodiment of the present application also provides an electronic device 1000, including a processor 1002 and a memory 1004, wherein the memory 1004 stores programs or instructions that can be executed on the processor 1002, and when the program or instructions are executed by the processor 1002, the various steps of the above-mentioned configuration method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, they are not described here.

[0118] It should be noted that the electronic devices in the embodiments of the present application include the above-mentioned mobile electronic devices and non-mobile electronic devices.

[0119] Fig.11 A schematic diagram of the hardware structure of an electronic device to implement an embodiment of the present application.

[0120] like Fig.11As shown, the electronic device 1100 includes but is not limited to: a radio frequency unit 1101, a network module 1102, an audio output unit 1103, an input unit 1104, a sensor 1105, a display unit 1106, a user input unit 1107, an interface unit 1108, a memory 1109, and a processor 1110 and other components.

[0121] Those skilled in the art will appreciate that the electronic device 1100 may also include a power source (such as a battery) for supplying power to each component, and the power source may be logically connected to the processor 1110 through a power management system, thereby implementing functions such as managing charging, discharging, and power consumption management through the power management system. Fig.11 The electronic device structure shown in the figure does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently, which will not be described in detail here.

[0122] In some embodiments of the present application, the processor 1110 is used to obtain the level at the connection pin; when the level at the connection pin is a first level, switch the configuration state of the GPIO interface circuit until the level at the connection pin switches from the first level to the second level or to the third level; wherein the first level is a level higher than the second level and lower than the third level.

[0123] In some embodiments of the present application, the processor 1110 is specifically used to obtain a first configuration state sequence when the level at the connection pin is a first level, and the first configuration state sequence is a sequence determined according to the first output state, the second output state, the first input state, the second input state and the third input state; switch the configuration state of the GPIO interface circuit based on the first configuration state sequence until the level at the connection pin is switched from the first level to the second level or to the third level; wherein, in the first output state, the output control module outputs the third level through the connection pin; in the second output state, the output control module outputs the second level through the connection pin; in the first input state, the input control module inputs a signal through the connection pin, and the resistance control module controls the first resistor to be cut in and the second resistor to be cut out; in the second input state, the input control module inputs a signal through the connection pin, and the resistance control module controls the first resistor to be cut out and the second resistor to be cut in; in the third input state, the input control module inputs a signal through the connection pin, and the resistance control module controls the first resistor to be cut out and the second resistor to be cut in.

[0124] In this embodiment, the level at the connection pin can be obtained and compared with the first level. If the level at the connection pin is the first level, the configuration state of the GPIO interface circuit is switched to get rid of the influence of the half-high level, thereby improving the reliability of the device where the GPIO interface circuit is located.

[0125] Since it is possible to directly detect whether the level at the connection pin PAD is the first level, there is no need to reserve test points on the circuit board where the GPIO interface circuit is located and use an oscilloscope to perform signal inspection. Obviously, in this process, the problems caused by the reserved test points can be improved. In addition, the automatic configuration of the GPIO interface circuit can be realized, and there is no need to configure the GPIO interface circuit according to the result of the signal inspection by the oscilloscope, thereby improving the configuration efficiency.

[0126] It should be understood that in the embodiment of the present application, the input unit 1104 may include a graphics processor (Graphics Processing Unit, GPU) 11041 and a microphone 11042, and the graphics processor 11041 processes the image data of the static picture or video obtained by the image capture device (such as a camera) in the video capture mode or the image capture mode. The display unit 1106 may include a display panel 11061, and the display panel 11061 may be configured in the form of a liquid crystal display, an organic light emitting diode, etc. The user input unit 1107 includes a touch panel 11071 and at least one of other input devices 11072. The touch panel 11071 is also called a touch screen. The touch panel 11071 may include two parts: a touch detection device and a touch controller. Other input devices 11072 may include, but are not limited to, a physical keyboard, function keys (such as volume control keys, switch keys, etc.), a trackball, a mouse, and a joystick, which will not be repeated here.

[0127] The memory 1109 can be used to store software programs and various data. The memory 1109 may mainly include a first storage area for storing programs or instructions and a second storage area for storing data, wherein the first storage area may store an operating system, an application program or instructions required for at least one function (such as a sound playback function, an image playback function, etc.), etc. In addition, the memory 1109 may include a volatile memory or a non-volatile memory, or the memory 1109 may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDRSDRAM), an enhanced synchronous dynamic random access memory (ESDRAM), a synchronous link dynamic random access memory (SLDRAM) and a direct memory bus random access memory (DRRAM). The memory 1109 in the embodiment of the present application includes but is not limited to these and any other suitable types of memory.

[0128] The processor 1110 may include one or more processing units; optionally, the processor 1110 integrates an application processor and a modem processor, wherein the application processor mainly processes operations related to an operating system, a user interface, and application programs, and the modem processor mainly processes wireless communication signals, such as a baseband processor. It is understandable that the modem processor may not be integrated into the processor 1110.

[0129] An embodiment of the present application also provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the various processes of the above-mentioned configuration method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0130] The processor is the processor in the electronic device in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory ROM, a random access memory RAM, a magnetic disk or an optical disk.

[0131] An embodiment of the present application further provides a chip, which includes a processor and a communication interface, the communication interface and the processor are coupled, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned configuration method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0132] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0133] An embodiment of the present application provides a computer program product, which is stored in a storage medium. The program product is executed by at least one processor to implement the various processes of the configuration method embodiment described above, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0134] It should be noted that, in this article, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "including one" do not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0135] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the embodiments of the present application are essentially or partly contributed to the prior art can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, a disk, an optical disk), and includes a number of instructions for a terminal (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods of each embodiment of the present application.

[0136] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A GPIO interface circuit, characterized in that: include: Connect the pins; A detection module, wherein an input end of the detection module is connected to the connection pin, and an output end of the detection module is used to output the level at the connection pin; A configuration state switching module, the configuration state switching module is respectively connected to the connection pin and the detection module, and is used to switch the configuration state of the GPIO interface circuit when the level at the connection pin is a first level, until the level at the connection pin is switched from the first level to a second level or to a third level, and the first level is a level higher than the second level and lower than the third level.

2. The GPIO interface circuit according to claim 1, characterized in that: The configuration state of the GPIO interface circuit includes a first output state, a second output state, a first input state, a second input state and a third input state, and the configuration state switching module includes: An output control module, wherein an output end of the output control module is connected to the connection pin; An input control module, wherein an input end of the input control module is connected to the connection pin; a configuration module, the configuration module comprising a first resistor and a second resistor, the first end of the first resistor being connected to the first power source, the second end of the first resistor being connected to the connection pin, the first end of the second resistor being connected to the connection pin, and the second end of the second resistor being grounded; a resistance control module, connected to the first resistor and the second resistor respectively; Wherein, in the first output state, the output control module outputs the third level through the connecting pin; in the second output state, the output control module outputs the second level through the connecting pin; in the first input state, the input control module inputs a signal through the connecting pin, and the resistance control module controls the first resistor to be cut in and the second resistor to be cut out; in the second input state, the input control module inputs a signal through the connecting pin, and the resistance control module controls the first resistor to be cut out and the second resistor to be cut in; in the third input state, the input control module inputs a signal through the connecting pin, and the resistance control module controls the first resistor and the second resistor to be cut out.

3. The GPIO interface circuit according to claim 1, characterized in that: The detection module comprises: a first comparison circuit, wherein an input end of the first comparison circuit is connected to the connection pin, and when the level at the connection pin is lower than the third level, the first comparison circuit outputs a high level signal, and when the level at the connection pin is equal to or higher than the third level, the first comparison circuit outputs a low level signal; a second comparison circuit, wherein an input end of the second comparison circuit is connected to the connection pin, and when the level at the connection pin is lower than or equal to the second level, the second comparison circuit outputs a low level signal, and when the level at the connection pin is higher than the second level, the second comparison circuit outputs a high level signal; An AND gate, wherein a first input terminal of the AND gate is connected to an output terminal of the first comparison circuit, and a second input terminal of the AND gate is connected to an output terminal of the second comparison circuit; Wherein, when the output end of the first comparison circuit and the output end of the second comparison circuit simultaneously output the high level signal, the level at the connection pin is the first level.

4. The GPIO interface circuit according to claim 3, characterized in that: The first comparison circuit comprises: a third resistor, a first end of the third resistor being connected to the connecting pin; a fourth resistor, wherein a first end of the fourth resistor is connected to a second end of the third resistor, and a second end of the fourth resistor is grounded; A first comparator, wherein a negative phase input terminal of the first comparator is connected to a first end of the fourth resistor, and a positive phase input terminal of the first comparator is used to input a voltage signal corresponding to the third level; and / or The second comparison circuit comprises: a fifth resistor, a first end of the fifth resistor being connected to the connecting pin; a sixth resistor, wherein a first end of the sixth resistor is connected to a second end of the fifth resistor, and a second end of the sixth resistor is grounded; A second comparator, wherein a positive phase input terminal of the second comparator is connected to the first end of the sixth resistor, and a negative phase input terminal of the second comparator is used to input a voltage signal corresponding to the second level.

5. The GPIO interface circuit according to claim 1, characterized in that: The detection module comprises: An analog-to-digital converter, wherein the input end of the analog-to-digital converter is connected to the connecting pin, and the output end of the analog-to-digital converter is used to output the electrical level at the connecting pin.

6. The GPIO interface circuit according to claim 5, characterized in that: The analog-to-digital converter further has a power supply end. When the voltage input to the power supply end is less than the output voltage of the first power supply, the detection module further includes: a seventh resistor, connected in series between the input end of the analog-to-digital converter and the connecting pin, wherein a first end of the seventh resistor is connected to the connecting pin; an eighth resistor, a first end of the eighth resistor being connected to the second end of the seventh resistor, and a second end of the eighth resistor being grounded; The output voltage of the first power supply has a voltage divided value at the eighth resistor that is less than or equal to the voltage input to the power supply end.

7. A configuration method for the GPIO interface circuit according to any one of claims 1 to 6, characterized in that: The configuration method comprises: Get the level at the connection pin; When the level at the connection pin is the first level, switching the configuration state of the GPIO interface circuit until the level at the connection pin is switched from the first level to the second level or to the third level; The first level is a level higher than the second level and lower than the third level.

8. The configuration method according to claim 7, characterized in that: When the level at the connection pin is the first level, switching the configuration state of the GPIO interface circuit until the level at the connection pin is switched from the first level to the second level or to the third level, specifically includes: When the level at the connection pin is the first level, acquiring a first configuration state sequence, where the first configuration state sequence is a sequence determined according to a first output state, a second output state, a first input state, a second input state, and a third input state; Switching the configuration state of the GPIO interface circuit based on the first configuration state sequence until the level at the connection pin is switched from the first level to the second level or to the third level; Among them, in the first output state, the output control module outputs the third level through the connecting pin; in the second output state, the output control module outputs the second level through the connecting pin; in the first input state, the input control module inputs a signal through the connecting pin, and the resistance control module controls the first resistor to be cut in and the second resistor to be cut out; in the second input state, the input control module inputs a signal through the connecting pin, and the resistance control module controls the first resistor to be cut out and the second resistor to be cut in; in the third input state, the input control module inputs a signal through the connecting pin, and the resistance control module controls the first resistor to be cut out and the second resistor to be cut in.

9. A configuration device for the GPIO interface circuit according to any one of claims 1 to 6, characterized in that: The configuration device comprises: An acquisition module is used to obtain the level at the connection pin; a switching module, configured to switch the configuration state of the GPIO interface circuit when the level at the connection pin is the first level, until the level at the connection pin is switched from the first level to the second level or to the third level; The first level is a level higher than the second level and lower than the third level.

10. The configuration device according to claim 9, characterized in that: The switching module is specifically used for: When the level at the connection pin is the first level, acquiring a first configuration state sequence, where the first configuration state sequence is a sequence determined according to a first output state, a second output state, a first input state, a second input state, and a third input state; Switching the configuration state of the GPIO interface circuit based on the first configuration state sequence until the level at the connection pin is switched from the first level to the second level or to the third level; Among them, in the first output state, the output control module outputs the third level through the connecting pin; in the second output state, the output control module outputs the second level through the connecting pin; in the first input state, the input control module inputs a signal through the connecting pin, and the resistance control module controls the first resistor to be cut in and the second resistor to be cut out; in the second input state, the input control module inputs a signal through the connecting pin, and the resistance control module controls the first resistor to be cut out and the second resistor to be cut in; in the third input state, the input control module inputs a signal through the connecting pin, and the resistance control module controls the first resistor to be cut out and the second resistor to be cut in.

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