Cross-FPGA time sequence budget constraint method and device, equipment and medium

Abstract

The invention discloses a cross-FPGA (Field Programmable Gate Array) time sequence budget constraint method, device, equipment and medium, and relates to the technical field of electronic design automation, the method comprises the following steps: constructing a cross-FPGA time sequence diagram according to a read user netlist, extracting a to-be-analyzed path segment in each FPGA, and respectively obtaining at least one corresponding longest path according to the type of the path segment; and in a time sequence report of the cross-FPGA time sequence diagram, obtaining time sequence report content corresponding to each longest path, calculating a time sequence budget value of each to-be-analyzed path segment for each matched longest path, and adding a time sequence budget constraint for each to-be-analyzed path segment. The time sequence budget value is calculated according to the longest path corresponding to each to-be-analyzed path segment in the cross-FPGA time sequence diagram, and the time sequence budget constraint is added to each to-be-analyzed path segment, so that the influence of the time sequence path at the segmentation boundary is considered in the cross-FPGA design, accurate time sequence budget and constraint are performed, and the stability and reliability of the design are improved.

Description

Technical Field

[0001] The present invention relates to the field of electronic design automation technology, and in particular to a method, device, equipment and medium for timing budget constraints across FPGAs. Background Art

[0002] In integrated circuit design, design timing must be checked at each stage, especially timing analysis at the design boundary across FPGA (Field-Programmable Gate Array) to ensure that the designed circuit can meet the predetermined timing requirements.

[0003] In existing FPGA design technology, STA (static timing analysis) is used to analyze all possible paths of the circuit to ensure that the circuit operates reliably within the specified timing constraints. STA focuses on the compliance of the internal timing relationship of the FPGA. By defining timing constraints and performing iterative optimization in the synthesis, layout, and routing stages of the design, it can quickly and comprehensively analyze the timing path and identify timing violations. However, after the user design is split into different FPGAs, signal delay problems may occur at the split boundaries, which cannot meet the design's timing requirements for the signal, reducing the stability and reliability of the design. Summary of the invention

[0004] The present invention provides a cross-FPGA timing budget constraint method to solve the problem of reduced stability and reliability of the design caused by signal timing problems at segmentation boundaries in cross-FPGA design.

[0005] According to an aspect of an embodiment of the present invention, a method for constraining a timing budget across FPGAs is provided, comprising:

[0006] Read the user netlist, and construct a cross-FPGA timing diagram based on the user netlist, wherein the cross-FPGA timing diagram includes multiple FPGAs with marked input and output ports, and describes the flow path of the clock or data signal in each device in each FPGA through connecting lines; in the cross-FPGA timing diagram, extract the path segments to be analyzed in each FPGA, and obtain at least one longest path corresponding to each path segment to be analyzed according to the segment type of the path segment to be analyzed; in the timing report of the cross-FPGA timing diagram, obtain the timing report content corresponding to each longest path, and calculate the timing budget value of each path segment to be analyzed for each matching longest path according to the timing report content; and add timing budget constraints to each path segment to be analyzed according to the calculated timing budget values.

[0007] According to another aspect of an embodiment of the present invention, a cross-FPGA timing budget constraint device is also provided, including:

[0008] A cross-FPGA timing diagram construction module is used to read the user netlist and construct a cross-FPGA timing diagram based on the user netlist;

[0009] The longest path acquisition module is used to extract the path segments to be analyzed in each FPGA in the cross-FPGA timing diagram, and obtain at least one longest path corresponding to each path segment to be analyzed according to the segment type of the path segment to be analyzed;

[0010] A timing budget value calculation module is used to obtain the timing report content corresponding to each longest path in the timing report of the cross-FPGA timing diagram, and calculate the timing budget value of each longest path matched for each path segment to be analyzed according to the timing report content;

[0011] The timing budget constraint adding module is used to add a timing budget constraint to each path segment to be analyzed according to each calculated timing budget value.

[0012] According to another aspect of an embodiment of the present invention, an electronic device is provided, the electronic device comprising:

[0013] at least one processor; and

[0014] a memory communicatively connected to the at least one processor; wherein,

[0015] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the cross-FPGA timing budget constraint method described in any embodiment of the present invention.

[0016] According to another aspect of an embodiment of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the cross-FPGA timing budget constraint method described in any embodiment of the present invention when executed.

[0017] According to another aspect of an embodiment of the present invention, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps of the method described in any embodiment of the present invention are implemented.

[0018] The technical solution of the embodiment of the present invention reads the user netlist, constructs a cross-FPGA timing diagram according to the user netlist, extracts the path segments to be analyzed in each FPGA, and obtains at least one corresponding longest path according to the segment type; in the timing report of the cross-FPGA timing diagram, obtains the timing report content corresponding to each longest path, calculates the timing budget value corresponding to each longest path, and adds a timing budget constraint to each path segment to be analyzed. By calculating the timing budget value of each path segment to be analyzed according to the longest path of each path segment to be analyzed in the cross-FPGA timing diagram, and adding a timing budget constraint to each path segment to be analyzed, the influence of the timing path at the segmentation boundary is considered in the cross-FPGA design, and accurate timing budget and constraints are performed, thereby improving the stability and reliability of the design.

[0019] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 is a flowchart of a cross-FPGA timing budget constraint method provided according to Embodiment 1 of the present invention;

[0022] Figure 2 is a schematic diagram of a timing budget calculation method applicable to an embodiment of the present invention;

[0023] Figure 3 It is an FPGA timing diagram applicable to the embodiment of the present invention;

[0024] Figure 4 This is a single longest path acquisition flow chart applicable to the embodiment of the present invention;

[0025] Figure 5 It is a timing budget constraint output flow chart applicable to the embodiment of the present invention;

[0026] Figure 6 is an example diagram of a timing path report applicable to an embodiment of the present invention;

[0027] Figure 7 is an example diagram of a timing report applicable to an embodiment of the present invention;

[0028] Figure 8 This is a schematic diagram of the structure of a cross-FPGA timing budget constraint device provided according to Embodiment 2 of the present invention;

[0029] Fig. 9 It is a schematic diagram of the structure of an electronic device for implementing the cross-FPGA timing budget constraint method of an embodiment of the present invention. DETAILED DESCRIPTION

[0030] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0031] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0032] Embodiment 1

[0033] Figure 1 This is a flowchart of a cross-FPGA timing budget constraint method provided in the first embodiment of the present invention. This embodiment can be applied to the case where the timing budget value of each path segment is calculated and the corresponding timing budget constraint is added to it in the cross-FPGA design. The method can be executed by a cross-FPGA timing budget constraint device. The cross-FPGA timing budget constraint device can be implemented in the form of hardware and / or software and can generally be configured in an electronic device. Figure 1 As shown, the method includes:

[0034] S110, reading the user netlist, and constructing a cross-FPGA timing diagram according to the user netlist.

[0035] Among them, the cross-FPGA timing diagram contains multiple FPGAs with labeled input and output ports, and describes the flow path of the clock or data signal in each device in each FPGA through connecting lines.

[0036] In an embodiment of the present invention, a user netlist refers to a description of the logical connection and structural information of a circuit in an FPGA design, such as modules, pins, network cables, ports, and clocks. A cross-FPGA timing diagram refers to a description of the timing relationship when a signal propagates between different FPGA chips, reflecting the propagation delay of the signal between different FPGAs. Among them, a cross-FPGA timing diagram includes multiple FPGAs, and the input and output ports for data to enter or leave the FPGA are marked in the diagram. The wires connecting different logic units in the circuit are represented by connecting lines in the diagram, describing the flow path of the clock or data signal in each device in each FPGA, such as the path from the source point (such as an input port or a trigger) to the end point (such as an output port or a trigger).

[0037] S120. Extract the path segments to be analyzed in each FPGA in the cross-FPGA timing diagram, and obtain at least one longest path corresponding to each path segment to be analyzed according to the segment type of the path segment to be analyzed.

[0038] In an embodiment of the present invention, the path segment to be analyzed refers to a signal path that needs to be checked to ensure that they meet the timing requirements. The segment type refers to the category to which the signal path belongs based on the propagation node and logic type, and may specifically include: a pure combinational logic path and a non-pure combinational logic path. Among them, a pure combinational logic path refers to a path that does not involve any clock-triggered triggers, and only includes combinational logic gates and wires. The propagation of the signal only depends on the delay of the logic gates and the delay of the wires; a non-pure combinational logic path refers to a path that contains at least one clock-triggered trigger, and the propagation of the signal depends on the delay of the logic gates, the delay of the wires, and the internal delay of the clock-triggered trigger. The longest path refers to the path with the largest delay among all possible signal propagation paths, which determines the longest time required for the data signal to propagate from one point to another.

[0039] Specifically, the longest path can be understood as a path constructed by taking the starting point or end point of the path segment to be analyzed as the starting point, traversing forward or backward to the previous driving point or the next loading point, and based on the traversed previous driving point or the next loading point, and the path segment to be analyzed.

[0040] Among them, the previous driving point can be understood as the data output end of a trigger closest to the path segment to be analyzed or the input port of the FPGA, and the latter loading point can be understood as the data input end of a trigger closest to the path segment to be analyzed or the output port of the FPGA.

[0041] S130. In the timing report of the cross-FPGA timing diagram, obtain the timing report content corresponding to each longest path, and calculate the timing budget value of each path segment to be analyzed for each matching longest path according to the timing report content.

[0042] In the embodiment of the present invention, the timing report refers to a report that provides information about key timing parameters such as signal propagation delay, clock delay, setup time and hold time in the circuit. The timing budget value refers to the maximum allowable delay value set for the signal propagation path segment in order to meet specific timing requirements. Accordingly, the timing budget value of the path segment can be calculated through the signal propagation delay, clock delay, wire delay, setup time and hold time of the path segment in the timing report, that is, for a pure combinational logic path, the timing budget value = propagation delay of all logic gates + delay of all wires; for a non-pure combinational logic path, the timing budget value = clock delay + setup time + propagation delay + hold time.

[0043] Generally speaking, after the developer completes the software development based on multiple FPGAs and obtains the corresponding cross-FPGA timing diagram, the development software can adaptively generate a matching timing report based on the cross-FPGA timing diagram and various configuration parameters. In addition, in response to the path start point and path end point input by the user that match path A, the timing report content that matches path A can be extracted from the timing report.

[0044] Furthermore, since the path segment a to be analyzed must be located on a longest path b, combined with the timing report content matching the longest path b, the timing budget value of the path segment a to be analyzed on the longest path b can be calculated accordingly, that is, the timing budget value of each path segment to be analyzed for each matching longest path is calculated. S140, adding a timing budget constraint to each path segment to be analyzed according to the calculated timing budget values.

[0045] In the embodiment of the present invention, the timing budget constraint refers to a series of restriction conditions set on the timing parameters in the circuit according to the calculated timing budget value in order to ensure that the circuit can work normally within a specified clock cycle.

[0046] Specifically, the user netlist is read and a cross-FPGA timing diagram is constructed. The path segments to be analyzed in each FPGA are extracted and divided into pure combinational logic paths and non-pure combinational logic paths. At least one longest path corresponding to each path of each type is obtained respectively. The timing report corresponding to each longest path is obtained and the timing budget value of each path segment to be analyzed for each matching longest path is calculated according to the parameters recorded in the report, and timing budget constraints are added for it. By considering the influence of the timing path at the segmentation boundary, the timing budget value is accurately calculated and the timing budget constraints are added to ensure accurate timing control and management of the cross-FPGA design.

[0047] The technical solution of the embodiment of the present invention reads the user netlist, constructs a cross-FPGA timing diagram according to the user netlist, extracts the path segments to be analyzed in each FPGA, and obtains at least one corresponding longest path according to the segment type; in the timing report of the cross-FPGA timing diagram, obtains the timing report content corresponding to each longest path, and calculates the timing budget value of each path segment to be analyzed for each matching longest path, and adds a timing budget constraint to each path segment to be analyzed. By calculating the timing budget value of each path segment to be analyzed according to the longest path corresponding to each path segment to be analyzed in the cross-FPGA timing diagram, and adding a timing budget constraint to each path segment to be analyzed, the influence of the timing path at the segmentation boundary is considered in the cross-FPGA design, and accurate timing budget and constraints are performed, thereby improving the stability and reliability of the design.

[0048] Optionally, in an embodiment of the present invention, in a cross-FPGA timing diagram, extracting a path segment to be analyzed in each FPGA includes:

[0049] In the cross-FPGA timing diagram, identify at least one cross-FPGA flow path;

[0050] Segment each cross-FPGA flow path according to the FPGA to which it belongs to obtain multiple path segments, and filter out the path segment where the clock or data signal directly flows into the trigger device in the FPGA from the multiple path segments;

[0051] The path segments falling into each FPGA are respectively determined as the path segments to be analyzed in each FPGA.

[0052] In an embodiment of the present invention, the cross-FPGA flow path refers to the path of a signal (data or clock) from a starting FPGA chip, through 0, 1 or more FPGA chips, to a terminating FPGA chip, including the propagation of the signal inside the FPGA and the transmission path of the signal between at least two FPGAs.

[0053] Specifically, in the cross-FPGA timing diagram, at least two FPGAs are included, at least one cross-FPGA flow path in the cross-FPGA timing diagram is identified, and the cross-FPGA flow path is segmented according to the FPGA to which it belongs to obtain multiple path segments. Since the clock or data signal that directly flows into the trigger device in the FPGA comes from a source outside the FPGA, such as a clock generator on the board or an external interface. For these signals, they are artificially set, and their parameter indicators have a certain stability, and the path segments where these signals are located do not belong to the setting range of the timing budget constraints at the segmentation boundary in the cross-FPGA design. Therefore, the path segments where the clock or data signal directly flows into the trigger device in the FPGA are filtered out from the multiple path segments. The filtered path segments inside each FPGA are respectively determined as the path segments to be analyzed in each FPGA, which are used for subsequent timing budget value calculation and adding timing budget constraints to the path segments to be analyzed.

[0054] Furthermore, the path segments obtained by segmenting each cross-FPGA flow path according to the FPGA to which it belongs can be understood as the portion of each cross-FPGA flow path located inside each FPGA. For example, a path segment flowing from an input port in a set FPGA to a data input end of a set trigger in the FPGA, a path segment flowing from an input port in the set FPGA to an output port in the FPGA through a lookup table, and a path segment flowing from a data output end of a set trigger in a set FPGA (non-last FPGA) to an output port in the FPGA.

[0055] Optionally, in the embodiment of the present invention, obtaining at least one longest path corresponding to each path segment to be analyzed according to the segment type of the path segment to be analyzed includes:

[0056] If the segment type of the first path segment to be analyzed currently being processed is a trigger-to-port type, obtaining a first port in the target path segment to be analyzed;

[0057] In each first cross-FPGA flow path including the first path segment to be analyzed, performing a backward search starting from the first port;

[0058] According to the first loading point searched in each first cross-FPGA flow path, at least one longest path corresponding to the first path segment to be analyzed is formed; wherein the first loading point includes a data input end of a trigger or an output port of the FPGA.

[0059] In an embodiment of the present invention, the first path segment to be analyzed refers to a path segment whose segment type is a trigger to port type, that is, a complete path for a data signal starting from the data output terminal of the trigger inside the FPGA, passing through the combinational logic, and finally reaching the output port of the FPGA. The first port refers to a port in the first path segment to be analyzed. The first cross-FPGA flow path refers to the flow path of the FPGA including the first path segment to be analyzed. The first loading point refers to the data input terminal of the trigger or the output port of the FPGA. The data input terminal is the port where the trigger receives data, and the output port of the FPGA is used to transmit the result of the internal logic processing to the external environment of the cross-FPGA design as a whole.

[0060] Specifically, the path segment to be analyzed whose segment type is a trigger to port type is taken as the first path segment to be analyzed, and the port in the first path segment to be analyzed is taken as the first port. In each FPGA flow path containing the first path segment to be analyzed, a backward search is performed starting from the first port until the first loading point including the data input end of the trigger or the output port of the FPGA is found, and the path from the trigger to the first loading point is taken as the longest path corresponding to the first path segment to be analyzed. The above process is repeated and the obtained longest paths are deduplicated until all the longest paths corresponding to all the first path segments to be analyzed are found.

[0061] Optionally, in the embodiment of the present invention, obtaining at least one longest path corresponding to each path segment to be analyzed according to the segment type of the path segment to be analyzed includes:

[0062] If the segment type of the second path segment to be analyzed currently being processed is a port-to-trigger type, obtaining a second port in the second path segment to be analyzed;

[0063] In each second cross-FPGA flow path including the second path segment to be analyzed, forward search is performed starting from the second port;

[0064] At least one longest path corresponding to the second path segment to be analyzed is formed according to the first driving point searched in each second cross-FPGA flow path; wherein the first driving point includes a data output end of a trigger or an input port of the FPGA.

[0065] In an embodiment of the present invention, the second path segment to be analyzed refers to a path segment whose segment type is a port to trigger type, that is, a signal path starting from the input port of the FPGA and ending at the data input terminal of a trigger inside the FPGA. The second port refers to a port in the second path segment to be analyzed. The second cross-FPGA flow path refers to the flow path of the FPGA including the second path segment to be analyzed. The first driving point refers to the data output terminal of the trigger or the input port of the FPGA. The data output terminal of the trigger is the port for the trigger to output data, which can be connected to other logic units inside the FPGA. The input port of the FPGA is the interface for external signals to enter the overall cross-FPGA design.

[0066] Specifically, the path segment to be analyzed whose segment type is currently processed and is a port-to-trigger type is used as the second path segment to be analyzed, and the port in the second path segment to be analyzed is used as the second port. In each FPGA flow path containing the second path segment to be analyzed, a forward search is performed starting from the second port until the first driving point including the data output end of the trigger or the input port of the FPGA is found, and the path from the first driving point to the trigger is used as the longest path corresponding to the second path segment to be analyzed. The above process is repeated and the obtained longest paths are deduplicated until all the longest paths corresponding to all the second path segments to be analyzed are found.

[0067] Optionally, in the embodiment of the present invention, obtaining at least one longest path corresponding to each path segment to be analyzed according to the segment type of the path segment to be analyzed includes:

[0068] If the segment type of the third path segment to be analyzed currently being processed is a port-to-port type, obtaining a start port and an end port in the target path segment to be analyzed;

[0069] In each third cross-FPGA flow path including the third path segment to be analyzed, forward search is performed starting from the start port, and backward search is performed starting from the end port;

[0070] According to the second driving point searched based on the starting port in each third cross-FPGA flow path, and the second loading point searched based on the end port, at least one longest path corresponding to the third path segment to be analyzed is formed;

[0071] The second driving point includes a data output terminal of the trigger or an input port of the FPGA, and the second loading point includes a data input terminal of the trigger or an output port of the FPGA.

[0072] In an embodiment of the present invention, the third path segment to be analyzed refers to a path segment of a port-to-port type, that is, a signal path starting from an input port of the FPGA and ending directly at another output port. This path segment does not involve the trigger inside the FPGA, only the combinational logic is involved in the transmission of the signal, and the transmission delay of the signal is determined by the combinational logic and the connection between them. The third cross-FPGA flow path refers to the flow path of the FPGA where the third path segment to be analyzed is located. The second driving point refers to the data output end of the trigger or the input port of the FPGA, and the second loading point refers to the data input end of the trigger or the output port of the FPGA.

[0073] Specifically, the path segment to be analyzed whose segment type is port-to-port type is used as the third path segment to be analyzed, and the starting port and the end port in the third path segment to be analyzed are obtained. In each FPGA flow path containing the third path segment to be analyzed, a forward search is performed starting from the starting port until a second driving point including the data output end of the trigger or the input port of the FPGA is found, and a backward search is performed starting from the end port until a second loading point including the data input end of the trigger or the output port of the FPGA is found, and the path from the second driving point to the second loading point is used as the longest path corresponding to the third path segment to be analyzed. The above process is repeated and the obtained longest paths are deduplicated until all the longest paths corresponding to all third path segments to be analyzed are found.

[0074] Optionally, in an embodiment of the present invention, calculating the timing budget value of each to-be-analyzed path segment for each matched longest path according to the timing report content includes:

[0075] Obtain the target path segment to be analyzed currently being processed, and a target longest path matching the target path segment to be analyzed, and extract the path start point and path end point from the target path segment to be analyzed;

[0076] In the target timing report content matching the target longest path, a first incremental propagation delay at the starting point of the path and a second incremental propagation delay at the end point of the path are respectively obtained;

[0077] Calculate the logical delay of the target path segment to be analyzed for the target longest path according to the first incremental propagation delay and the second incremental propagation delay;

[0078] In the target timing report content, obtain the data arrival time and clock arrival time corresponding to the longest path of the target;

[0079] According to the data arrival time and the clock arrival time, the total time margin of the longest path to the target is calculated;

[0080] Calculate the time margin allocation value of the target path segment to be analyzed for the target longest path according to the logic delay of the target path segment to be analyzed for the target longest path, the target longest path, and the total time margin value;

[0081] According to the calculated logic delay and time margin allocation value, the timing budget value of the target path segment to be analyzed for the target longest path is calculated.

[0082] In an embodiment of the present invention, the target longest path refers to the longest signal path in the design of the target path segment to be analyzed currently being processed. The first incremental propagation delay refers to the time node when the signal transmitted via the target longest path is transmitted to the path starting point of the target path segment to be analyzed. The second incremental propagation delay refers to the time node when the signal is transmitted to the path end point of the target path segment to be analyzed. The logical delay refers to the delay value of the signal passing through the FPGA in the target path segment to be analyzed. Accordingly, the logical delay of the target path segment to be analyzed can be calculated by the following formula: logical delay = second incremental propagation delay - first incremental propagation delay.

[0083] The total time margin value refers to the total delay time allowed on the signal transmission path of the longest target path in order to meet all timing requirements. If the total time margin value is positive or zero, it means that the signal has enough time to reach the destination within the clock cycle; if it is negative, it means that there is a timing violation and the signal cannot reach the destination within the clock cycle.

[0084] As mentioned above, each target longest path has a corresponding timing report content, in which the clock arrival time and data arrival time of the target longest path are recorded.

[0085] Accordingly, the total time margin value can be calculated by the following formula: Total time margin value = clock arrival time - data arrival time. Among them, the clock arrival time and the data arrival time refer to the time when the clock signal and the data signal arrive at the end of the longest path of the target, respectively. Accordingly, the clock arrival time can be understood as the propagation delay of the clock signal on the longest path of the target, and the data arrival time can be understood as the propagation delay of the data signal on the longest path of the target.

[0086] The time margin allocation value refers to the time margin allocated to each part of the signal path in order to meet specific timing requirements to ensure that the signal on the critical path can arrive in time. The time margin allocation value matched with the path segment to be analyzed is related to the logic delay of the target path segment to be analyzed, the target longest path and the total time margin value. Accordingly, the time margin allocation value of the target path segment to be analyzed can be calculated by the following formula: Time margin allocation value = [Logical delay of the target path segment to be analyzed / (Data arrival time of the target longest path-Total delay when the data propagates to the starting point of the target longest path-Total delay between FPGAs of the target longest path)] × Total time margin value. Among them, the total delay between FPGAs of the target longest path can be understood as the delay that the target longest path needs to go through when crossing different FPGAs. The total delay between FPGAs can be the number of FPGAs that the target longest path needs to pass through (or enter) * the inherent delay when passing through each FPGA.

[0087] The timing budget value refers to the timing parameter limits set for each part of the circuit at the beginning of the design, which is used to ensure that the final design meets the timing requirements. Accordingly, the timing budget value of the target path segment to be analyzed for the target longest path can be calculated by the following formula: Timing budget value = time margin allocation value of the target path segment to be analyzed for the target longest path + logic delay of the target path segment to be analyzed for the target longest path.

[0088] Through the above settings, the timing budget value of each path segment to be analyzed for each longest path matched can be calculated conveniently and accurately. Based on the calculation results, appropriate timing budget constraints can be added to each path segment to be analyzed to meet cross-FPGA design requirements.

[0089] Optionally, in an embodiment of the present invention, adding a timing budget constraint to each path segment to be analyzed according to each calculated timing budget value includes:

[0090] Among the timing budget values ​​of the longest paths matched by the path segments to be analyzed, the maximum timing budget value is obtained as the timing budget constraint of the path segments to be analyzed.

[0091] Specifically, the maximum timing budget value is obtained from the timing budget values ​​of the longest paths matched in each path segment to be analyzed, and used as the timing budget constraint of each path segment to be analyzed, and thus the corresponding timing budget constraint is added to each path segment to be analyzed. This allows the impact of the timing path at the segmentation boundary to be considered in cross-FPGA design, and accurate timing budgeting and constraints are performed, which improves the stability and reliability of the design.

[0092] Specific application scenarios

[0093] After the user design is segmented into different FPGAs, if no proper timing constraint processing is performed at the segmentation boundary, a large delay will be introduced when the signal is transmitted between FPGAs through the connection and the time division multiplexing (TDM) module, resulting in signal transmission delay. If the timing paths at these boundaries are not constrained, in the subsequent place and route (PR) stage, even if the constraints input by the user are read, the clock frequency specified by the user cannot be achieved, and the user's needs cannot be met, which reduces the stability and reliability of the design. In order to ensure that the transmission of signals between FPGAs meets the timing requirements, the present invention proposes a timing budget constraint method across FPGAs, which fully considers the timing budget problem at the segmentation boundary in the static timing analysis of the cross-FPGA design, and improves the stability and reliability of the design through reasonable design and constraints.

[0094] The technical solution adopted by the present invention may specifically be:

[0095] 1. Obtain the path segments to be analyzed on each FPGA according to the timing diagram

[0096] The segmented netlist of the original design is read in and a timing diagram is constructed. The path segments to be analyzed on each FPGA are obtained based on the segmented design. The path segments to be analyzed can be divided into: reg->port, port->reg, and port->port, i.e., trigger to port, port to trigger, and port to port.

[0097] 2. Calculate the longest path through each path segment to be analyzed

[0098] In the construction of cross-FPGA timing paths, the same path segment to be analyzed may pass through multiple timing paths. The longest paths passing through each path segment to be analyzed are calculated and obtained. When the longest path with the maximum timing budget value can meet the timing constraint requirements, the other path conditions will also meet the timing constraint requirements.

[0099] 3. Calculate one or more timing budget values ​​for each path segment to be analyzed based on the longest path passing through each path segment to be analyzed

[0100] The calculation is quite different from that when the timing path is inside a single FPGA. The timing budget acting on the segmentation boundary of the FPGA requires additional calculation. That is, the timing budget calculation needs to be performed based on the timing path passing through the path segment to be analyzed, and the delay calculation when the timing path passes through the connection and TDM.

[0101] 4. The timing budget delay value is applied to the FPGA in the form of constraints

[0102] After calculating the timing budget of each path segment to be analyzed, the set_max_delay command is used to constrain the output of the boundary timing budget constraints corresponding to each FPGA. The set_max_delay command is used to specify the maximum delay limit from the internal trigger of the FPGA to the output port to ensure that the signal can reach the output within the specified time.

[0103] Specifically, Figure 2 : is a schematic diagram of a timing budget calculation method applicable to an embodiment of the present invention. Wherein, F refers to FPGA, which is divided into F1 and F2; r refers to trigger, which is divided into r1 and r2; Tx_budget refers to the sending timing budget, which represents the total time budget from the output port of the trigger to the signal being sent to the outside of the FPGA; Rx_budget refers to the receiving timing budget, which represents the total time budget from the external signal of the FPGA to the input port of the trigger being correctly received by the internal logic of the FPGA; board_delay refers to the board-level delay, which represents the delay of the signal when it is transmitted outside the FPGA chip, and may include the propagation delay of the signal in the connection and connector; Tx_user_logic_delay refers to the user logic sending delay, which represents the time delay of the signal from the user logic part to the output port of the FPGA, and may include the delay of the internal logic of the FPGA and the delay of the output buffer; Rx_user_logic_delay refers to the user logic receiving delay, which represents the time delay of the signal from the input port of the FPGA to the user logic part, and may include the delay of the input buffer and the delay of the signal routing inside the FPGA; user_clk refers to the user clock signal generated by the clock management unit inside the FPGA, which is used to drive the design of the user logic. The timing budget is divided into path delay and time margin distribution. Path delay refers to the path logic delay, that is, the delay value of the path in the FPGA. Time margin distribution refers to the time margin of the entire path distributed proportionally to the time margin value of the FPGA.

[0104] Accordingly, when calculating the timing budget value and adding the timing budget constraint based on the user's cross-FPGA design netlist, the following steps can be followed:

[0105] 1. Read the user design netlist, build the timing diagram, and obtain the path segment to be analyzed

[0106] Figure 3This is an FPGA timing diagram applicable to an embodiment of the present invention, wherein F refers to FPGA, which is divided into F1, F2 and F3; r refers to a trigger, which is divided into r1, r2, r3 and r4, and the trigger includes a data input terminal D, a data output terminal Q and a clock signal terminal C; d is a data input terminal, which is divided into d1 and d2; clk is a clock signal, which is divided into clk1, clk2, clk3 and clk4; w1, w2, w6, w8 and n15 are ports of FPGA; LUT is a lookup table, which stores a mapping relationship between a set of input combinations and output results, so that when the input signal changes, there is no need to perform complex calculations, and only the results in the lookup table need to be quickly provided to provide corresponding outputs to realize combinational logic.

[0107] like Figure 3 As shown, the following path segments to be analyzed are obtained: the path segments in F1 are r1 / Q->F1 / w1 and r2 / Q->F1 / w2, the path segments in F2 are F2 / w1->F2 / n15 and F2 / w2->F2 / n15, and the path segments in F3 are F3 / n15->r3 / D and F3 / w8->r4 / D.

[0108] 2. According to Figure 3 The acquired path segments to be analyzed are judged for their types one by one and at least one longest path corresponding to each path segment to be analyzed is confirmed.

[0109] Figure 4 It is a single longest path acquisition flow chart applicable to the embodiment of the present invention. Among them, FF refers to a trigger, D terminal refers to a data input terminal, Q terminal refers to a data output, port refers to a port, reg refers to a trigger, reg to reg refers to a trigger to a trigger, reg to port refers to a trigger to a port, port to reg refers to a port to a trigger, port to port refers to a port to a port, output port refers to an FPGA output port, and input port refers to an FPGA input port.

[0110] For by Figure 3 For each path segment to be analyzed, if the path segment type is reg->port, such as the path segment in F1, search backward until reg or output port is found, and save the longest path; if the path segment type is port->reg, such as the path segment in F3, search forward for the driving point, F3 / n15->r3 / D path segment, search forward to r1 / Q in F1 as the starting point, confirm the longest path and save it; if the path segment type is port->port, search forward and backward from the two ports respectively until reg or port is found. After confirming the longest path type, save it as the longest path of the currently traversed path segment to be analyzed.

[0111] In particular, according to Figure 4 After obtaining a single longest path, all the path segments to be analyzed in the FPGA timing diagram need to be traversed in a loop by this method to identify all possible longest paths. During the traversal process, the obtained single longest paths are deduplicated to avoid repeated calculations.

[0112] 3. According to the longest path passed by each path segment to be analyzed, calculate the timing budget value of each path segment to be analyzed for each longest path matched, and determine the timing budget constraint that needs to be added to each path segment to be analyzed based on all the timing budget values ​​calculated for each path segment to be analyzed.

[0113] Each clock-constrained path will have a timing path report and timing margin (also called time margin). Figure 5 is a timing budget constraint output flow chart applicable to an embodiment of the present invention, Figure 6 This is an example diagram of a timing path report applicable to an embodiment of the present invention.

[0114] in, Figure 6 Incr(ns) refers to the incremental propagation delay on the timing path, that is, the time delay experienced when passing through the unit, in nanoseconds. This parameter is used in the timing report to analyze the time required for the signal to propagate between logic elements. Time refers to the cumulative delay from the starting point of the path to the current unit. Description describes the relevant information of the current signal propagation location. The timing path report is divided into a part that records the data signal propagation process and a part that records the clock signal propagation process. Among them, data arrival time is the propagation delay of the data signal, data required time is the propagation delay of the clock signal, and slack is the time margin.

[0115] As mentioned above, the total time margin corresponding to a longest path = the propagation delay of the clock signal on the longest path - the propagation delay of the data signal on the longest path; the time margin distribution of a path segment to be analyzed on the longest path = [logical delay of the path segment to be analyzed / (propagation delay of the data signal on the longest path - total delay when the data signal propagates to the starting point of the longest path - total delay between FPGAs of the longest path)] × the total time margin of the longest path; the timing budget value of the path segment to be analyzed = the time margin distribution of the path segment to be analyzed on the longest path + the logic delay of the path segment to be analyzed.

[0116] In a specific example, Figure 3As shown in the figure, in order to calculate the timing budget value of the path segment F2 / w2->F2 / n15 to be analyzed on the longest path r2 / Q->r3 / D, it is necessary to first calculate the logic delay of F2 / w2->F2 / n15 on r2 / Q->r3 / D. Figure 6 As shown in the figure, by querying the timing report content of the longest path r2 / Q->r3 / D, it can be obtained that the time for the data signal to propagate to F2 / n15 is 10.912ns, and the time for the data signal to propagate to F2 / w2 is 9.14ns. Therefore, the logical delay of the path segment F2 / w2->F2 / n15 to be analyzed is calculated to be 10.912-9.14=1.772ns; the total time margin of the longest path r2 / Q->r3 / D is 51.814-20.061=31.753ns; among them, the propagation delay of the data signal of r2 / Q->r3 / D is 20.061ns; the longest path r2 / Q->r3 / D passes through two FPGAs (F1->F2 and F2->F3), so the crossing delay of the two FPGAs needs to be subtracted, as shown in the figure. Figure 6 As shown in , the delay between each two FPGAs is 7.12, so the total delay between FPGAs r2 / Q->r3 / D is 7.12+7.12=14.24ns; in addition, Figure 6 As shown, the total delay of data propagation to the starting point (r2 / Q) of the longest path r2 / Q->r3 / D is 2.02ns; furthermore, the time margin distribution of the path segment F2 / w2->F2 / n15 to be analyzed is 1.772 / (20.061-14.24-2.02)×31.753≈14.801ns, and finally the timing budget value of the path segment 2 / w2->F2 / n15 to be analyzed is 14.801+1.772=16.573ns.

[0117] 4. Determine whether each path segment to be analyzed passes through multiple timing paths (that is, the longest path). If there are multiple timing paths, then calculate multiple timing budget values ​​for the same path segment to be analyzed for these multiple timing paths respectively, and then select the maximum calculated timing budget value as the constraint of the path segment to be analyzed.

[0118] like Figure 3 As shown, for the path segment F3 / n15->r3 / D to be analyzed, there are two longest paths, one is F2 / w1->r3 / D, and the other is F2 / w2->r3 / D. Through calculation, it can be seen that the timing budget value calculated for the longest path F2 / w2->r3 / D is larger. Therefore, the timing budget value calculated for the longest path F2 / w2->r3 / D is used to add constraints to the path segment F3 / n15->r3 / D to be analyzed.

[0119] 5. Output constraints, Figure 7 This is an example diagram of a timing report applicable to an embodiment of the present invention. The set_max_delay command is used to add corresponding timing budget constraints to the F2 / w1->F2 / n15 and F2 / w2->F2 / n15 path segments on FPGA2.

[0120] The present invention aims at the design across FPGAs. By adding a timing budget to the timing path at the split boundary, the problem of inaccurate static timing analysis results due to the path passing through the connection and TDM module is avoided, resulting in the problem that the user constrained clock cannot reach the specified frequency during subsequent user layout and routing. The invention realizes that the influence of the timing path at the split boundary is considered in the cross-FPGA design, and accurate timing budget and constraint are performed, thereby improving the stability and reliability of the design.

[0121] Embodiment 2

[0122] Figure 8 This is a schematic diagram of the structure of a timing budget constraint device across FPGAs provided in the second embodiment of the present invention. Figure 8 As shown, the device includes: a cross-FPGA timing diagram construction module 810, a longest path acquisition module 820, a timing budget value calculation module 830 and a timing budget constraint adding module 840.

[0123] A cross-FPGA timing diagram construction module 810 is used to read a user netlist and construct a cross-FPGA timing diagram according to the user netlist;

[0124] The longest path acquisition module 820 is used to extract the path segments to be analyzed in each FPGA in the cross-FPGA timing diagram, and acquire at least one longest path corresponding to each path segment to be analyzed according to the segment type of the path segment to be analyzed;

[0125] The timing budget value calculation module 830 is used to obtain the timing report content corresponding to each longest path in the timing report of the cross-FPGA timing diagram, and calculate the timing budget value of each path segment to be analyzed for each matching longest path according to the timing report content;

[0126] The timing budget constraint adding module 840 is used to add a timing budget constraint to each path segment to be analyzed according to each calculated timing budget value.

[0127] The technical solution of the embodiment of the present invention reads the user netlist, constructs a cross-FPGA timing diagram according to the user netlist, extracts the path segments to be analyzed in each FPGA, and obtains at least one corresponding longest path according to the segment type; in the timing report of the cross-FPGA timing diagram, obtains the timing report content corresponding to each longest path, calculates the timing budget value corresponding to each longest path, and adds a timing budget constraint to each path segment to be analyzed. By calculating the timing budget value of each path segment to be analyzed according to the longest path of each path segment to be analyzed in the cross-FPGA timing diagram, and adding a timing budget constraint to each path segment to be analyzed, the influence of the timing path at the segmentation boundary is considered in the cross-FPGA design, and accurate timing budget and constraints are performed, thereby improving the stability and reliability of the design.

[0128] Optionally, based on the above embodiments, the longest path acquisition module 820 is specifically configured to:

[0129] In the cross-FPGA timing diagram, identify at least one cross-FPGA flow path;

[0130] Segment each cross-FPGA flow path according to the FPGA to which it belongs to obtain multiple path segments, and filter out the path segment where the clock or data signal directly flows into the trigger device in the FPGA from the multiple path segments;

[0131] The path segments falling into each FPGA are respectively determined as the path segments to be analyzed in each FPGA.

[0132] Further, based on the above embodiments, the longest path acquisition module 820 can also be specifically used for:

[0133] If the segment type of the first path segment to be analyzed currently being processed is a trigger-to-port type, obtaining a first port in the target path segment to be analyzed;

[0134] In each first cross-FPGA flow path including the first path segment to be analyzed, performing a backward search starting from the first port;

[0135] At least one longest path corresponding to the first path segment to be analyzed is formed according to the first loading point searched in each first cross-FPGA flow path.

[0136] Further, based on the above embodiments, the longest path acquisition module 820 can also be specifically used for:

[0137] If the segment type of the second path segment to be analyzed currently being processed is a port-to-trigger type, obtaining a second port in the second path segment to be analyzed;

[0138] In each second cross-FPGA flow path including the second path segment to be analyzed, forward search is performed starting from the second port;

[0139] At least one longest path corresponding to the second path segment to be analyzed is formed according to the first driving point searched in each second cross-FPGA flow path.

[0140] Further, based on the above embodiments, the longest path acquisition module 820 can also be specifically used for:

[0141] If the segment type of the third path segment to be analyzed currently being processed is a port-to-port type, obtaining a start port and an end port in the target path segment to be analyzed;

[0142] In each third cross-FPGA flow path including the third path segment to be analyzed, forward search is performed starting from the start port, and backward search is performed starting from the end port;

[0143] At least one longest path corresponding to the third path segment to be analyzed is formed according to the second driving point searched based on the starting port in each third cross-FPGA flow path and the second loading point searched based on the end port.

[0144] Optionally, based on the above embodiments, the timing budget value calculation module 830 is specifically used to:

[0145] Obtain the target path segment to be analyzed currently being processed, as well as a target longest path matching the target path segment to be analyzed, and extract the path start point and path end point in the target path segment to be analyzed;

[0146] In the target timing report content matching the target longest path, a first incremental propagation delay at the starting point of the path and a second incremental propagation delay at the end point of the path are respectively obtained;

[0147] Calculate the logical delay of the target path segment to be analyzed for the target longest path according to the first incremental propagation delay and the second incremental propagation delay;

[0148] In the target timing report content, obtain the data arrival time and clock arrival time corresponding to the longest path of the target;

[0149] According to the data arrival time and the clock arrival time, the total time margin of the longest path to the target is calculated;

[0150] Calculate the time margin allocation value of the target path segment to be analyzed for the target longest path according to the logic delay of the target path segment to be analyzed for the target longest path, the target longest path, and the total time margin value;

[0151] According to the calculated logic delay and time margin allocation value, the timing budget value of the target path segment to be analyzed for the target longest path is calculated.

[0152] Optionally, based on the above embodiments, the timing budget constraint adding module 840 is specifically used to:

[0153] Among the timing budget values ​​of the longest paths matched by the path segments to be analyzed, the maximum timing budget value is obtained as the timing budget constraint of the path segments to be analyzed.

[0154] The cross-FPGA timing budget constraint device provided in the embodiment of the present invention can execute the cross-FPGA timing budget constraint method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0155] In the technical solution of the present disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved are in compliance with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0156] Embodiment 3

[0157] Fig. 9 A schematic diagram of the structure of an electronic device 10 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0158] like Fig. 9 As shown, the electronic device 10 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0159] A number of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0160] The processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The processor 11 executes the various methods and processes described above, such as the timing budget constraint method across FPGAs, that is:

[0161] Read the user netlist and construct a cross-FPGA timing diagram based on the user netlist, wherein the cross-FPGA timing diagram includes multiple FPGAs with marked input and output ports, and describes the flow path of the clock or data signal in each device in each FPGA through wiring;

[0162] In the cross-FPGA timing diagram, extract the path segments to be analyzed in each FPGA, and obtain at least one longest path corresponding to each path segment to be analyzed according to the segment type of the path segment to be analyzed;

[0163] In the timing report of the cross-FPGA timing diagram, the timing report content corresponding to each longest path is obtained, and the timing budget value of each path segment to be analyzed for each matched longest path is calculated according to the timing report content;

[0164] According to the calculated timing budget values, a timing budget constraint is added to each path segment to be analyzed.

[0165] In some embodiments, the timing budget constraint method across FPGAs may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the timing budget constraint method across FPGAs described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to execute the timing budget constraint method across FPGAs in any other appropriate manner (e.g., by means of firmware).

[0166] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0167] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0168] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0169] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0170] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0171] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0172] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0173] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A timing budget constraint method across FPGAs, characterized in that: include: Read the user netlist and construct a cross-FPGA timing diagram based on the user netlist, wherein the cross-FPGA timing diagram includes multiple FPGAs with marked input and output ports, and describes the flow path of the clock or data signal in each device in each FPGA through wiring; In the cross-FPGA timing diagram, extract the path segments to be analyzed in each FPGA, and obtain at least one longest path corresponding to each path segment to be analyzed according to the segment type of the path segment to be analyzed; In the timing report of the cross-FPGA timing diagram, the timing report content corresponding to each longest path is obtained, and the timing budget value of each path segment to be analyzed for each matched longest path is calculated according to the timing report content; According to the calculated timing budget values, a timing budget constraint is added to each path segment to be analyzed.

2. The method according to claim 1, characterized in that In the cross-FPGA timing diagram, extract the path segments to be analyzed in each FPGA, including: In the cross-FPGA timing diagram, identify at least one cross-FPGA flow path; Segment each cross-FPGA flow path according to the FPGA to which it belongs to obtain multiple path segments, and filter out the path segment where the clock or data signal directly flows into the trigger device in the FPGA from the multiple path segments; The path segments falling into each FPGA are respectively determined as the path segments to be analyzed in each FPGA.

3. The method according to claim 2, characterized in that According to the segment type of the path segment to be analyzed, obtaining at least one longest path corresponding to each path segment to be analyzed, including: If the segment type of the first path segment to be analyzed currently being processed is a trigger-to-port type, obtaining a first port in the target path segment to be analyzed; In each first cross-FPGA flow path including the first path segment to be analyzed, performing a backward search starting from the first port; According to the first loading point searched in each first cross-FPGA flow path, at least one longest path corresponding to the first path segment to be analyzed is formed; wherein the first loading point includes a data input end of a trigger or an output port of the FPGA.

4. The method according to claim 2, characterized in that: According to the segment type of the path segment to be analyzed, obtaining at least one longest path corresponding to each path segment to be analyzed, including: If the segment type of the second path segment to be analyzed currently being processed is a port-to-trigger type, obtaining a second port in the second path segment to be analyzed; In each second cross-FPGA flow path including the second path segment to be analyzed, forward search is performed starting from the second port; At least one longest path corresponding to the second path segment to be analyzed is formed according to the first driving point searched in each second cross-FPGA flow path; wherein the first driving point includes a data output end of a trigger or an input port of the FPGA.

5. The method according to claim 2, characterized in that: According to the segment type of the path segment to be analyzed, obtaining at least one longest path corresponding to each path segment to be analyzed, including: If the segment type of the third path segment to be analyzed currently being processed is a port-to-port type, obtaining a start port and an end port in the target path segment to be analyzed; In each third cross-FPGA flow path including the third path segment to be analyzed, forward search is performed starting from the start port, and backward search is performed starting from the end port; According to the second driving point searched based on the starting port in each third cross-FPGA flow path, and the second loading point searched based on the end port, at least one longest path corresponding to the third path segment to be analyzed is formed; The second driving point includes a data output terminal of the trigger or an input port of the FPGA, and the second loading point includes a data input terminal of the trigger or an output port of the FPGA.

6. The method according to any one of claims 1 to 5, characterized in that: According to the timing report content, calculate the timing budget value of each path segment to be analyzed for each longest matching path, including: Obtain the target path segment to be analyzed currently being processed, as well as a target longest path matching the target path segment to be analyzed, and extract the path start point and path end point in the target path segment to be analyzed; In the target timing report content matching the target longest path, a first incremental propagation delay at the starting point of the path and a second incremental propagation delay at the end point of the path are respectively obtained; Calculate the logical delay of the target path segment to be analyzed for the target longest path according to the first incremental propagation delay and the second incremental propagation delay; In the target timing report content, obtain the data arrival time and clock arrival time corresponding to the longest path of the target; According to the data arrival time and the clock arrival time, the total time margin of the longest path to the target is calculated; Calculate the time margin allocation value of the target path segment to be analyzed for the target longest path according to the logic delay of the target path segment to be analyzed for the target longest path, the target longest path, and the total time margin value; According to the calculated logic delay and time margin allocation value, the timing budget value of the target path segment to be analyzed for the target longest path is calculated.

7. The method according to any one of claims 1 to 5, characterized in that: According to the calculated timing budget values, add timing budget constraints to each path segment to be analyzed, including: Among the timing budget values ​​of the longest paths matched by the path segments to be analyzed, the maximum timing budget value is obtained as the timing budget constraint of the path segments to be analyzed.

8. A timing budget constraint device across FPGAs, characterized in that: include: A cross-FPGA timing diagram construction module is used to read the user netlist and construct a cross-FPGA timing diagram based on the user netlist; The longest path acquisition module is used to extract the path segments to be analyzed in each FPGA in the cross-FPGA timing diagram, and obtain at least one longest path corresponding to each path segment to be analyzed according to the segment type of the path segment to be analyzed; A timing budget value calculation module is used to obtain the timing report content corresponding to each longest path in the timing report of the cross-FPGA timing diagram, and calculate the timing budget value of each path segment to be analyzed for each matching longest path according to the timing report content; The timing budget constraint adding module is used to add a timing budget constraint to each path segment to be analyzed according to each calculated timing budget value.

9. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so as to enable the at least one processor to perform the cross-FPGA timing budget constraint method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the cross-FPGA timing budget constraint method according to any one of claims 1 to 7 when the processor executes the computer instructions.

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