Method for constructing digital twin model of electronic component reliability and computer device

Abstract

The present invention discloses a method for constructing a reliability digital twin model of an electronic component and a computer device. The method includes: determining input information and constructing a fault mechanism model of electronic components; obtaining sampling values of the first failure time series of all electronic components from the fault mechanism model of electronic components and constructing a first failure time model of electronic components; constructing a failure rate model of electronic components based on the first failure time model; constructing a board-level failure rate model of a circuit board; constructing a failure rate model of an electronic component; constructing a first failure time model of an electronic component; constructing a reliability model of an electronic component; and constructing a reliability digital twin model of an electronic component based on the first failure time model, the failure rate model, and the reliability model of the electronic component. The present invention can construct a complete reliability digital twin model of an electronic component and realize the reliability design analysis, test evaluation, and diagnosis prediction of the electronic component by means of digitalization.

Description

Technical Field

[0001] The present invention belongs to the technical field of reliability, and relates to a method for constructing a reliability digital twin model of electronic components and a computer device. Background Art

[0002] Electronic components are important constituent units of electronic products, which are directly related to the performance, stability, and service life of the entire electronic device. With the rapid development of electronic technology, electronic components have become increasingly complex, with more functions and higher integration levels, which increases the difficulty of reliability design of electronic components. Due to the limitations of reliability test equipment and environmental conditions, it is often difficult to fully simulate the real working environment, which may affect the accuracy and reliability of test results, and cannot truly reflect the reliability level of products. Reliability tests usually require a large number of sample quantities and long test cycles, which increases the cost and time investment of the tests. These existing reliability bottleneck problems of electronic components make it impossible to meet the requirements of rapid product iteration, quality improvement, and efficiency enhancement at the present stage. As an emerging simulation technology, reliability digital twin technology realizes real-time simulation, monitoring, prediction, and optimization of the reliability operation state of physical entities by creating digital mirrors of physical entities. With the rapid development of computer technology and the wide application of technologies such as big data and artificial intelligence, reliability digital twin technology has gradually expanded to multiple fields. In the reliability design analysis, test evaluation, and operation monitoring of electronic products, reliability digital twin technology can provide solutions for the reliability guarantee of their life cycles.

[0003] Currently, the application of digital twin technology mainly focuses on functions and performance, but rarely establishes a reliability digital twin model for electronic components, and it is impossible to simulate, monitor, diagnose, predict, and control the reliability characteristics, reliability behaviors, and reliability processes of electronic components in the digital space, and it is difficult to meet the requirements of forward design, rapid testing, and diagnostic prediction of the reliability of electronic components. Summary of the Invention

[0004] The purpose of the present invention is to provide a method for constructing a reliability digital twin model of electronic components, a computer device, a computer-readable storage medium, and a computer program product, which can construct a complete reliability digital twin model of electronic components and realize the reliability design analysis, test evaluation, and diagnostic prediction of electronic components by digital means.

[0005] To achieve the above purpose, one aspect of the present invention provides a method for constructing a reliability digital twin model of electronic components, including:

[0006] Step S1, determining input information and constructing a failure mechanism model of electronic components:

[0007] M model(ij) = M(IPA(ij) , I PR(ij) , I CAE(ij) )

[0008] Among them, M model(ij) represents the failure mechanism model of the j-th electronic component in the i-th circuit board of the electronic component, I PA(ij) represents the input of the packaging information of the j-th electronic component in the i-th circuit board, I PR(ij) represents the input of the cross-sectional information of the j-th electronic component in the i-th circuit board, I CAE(ij) represents the input of the CAE simulation model information of the j-th electronic component in the i-th circuit board;

[0009] Step S2, obtain the sampling values of the first failure time series of all electronic components from the failure mechanism model of the electronic components, and construct the first failure time model of the electronic components:

[0010]

[0011] Among them, MTTF model(ij) represents the first failure time model of the j-th electronic component in the i-th circuit board, l represents the number of sampling values of the first failure time of the j-th electronic component in the i-th circuit board in the sampling values, M model(ijk) represents the k-th first failure time model of the j-th electronic component in the i-th circuit board in the sampling values; or

[0012] MTTF model(ij) = E(M model(ij) )

[0013] Among them, E(M model(ij) ) represents the expected first failure time based on the distribution fitting of the series sampling values;

[0014] Step S3, construct the failure rate model of the electronic components based on the first failure time model of the electronic components:

[0015]

[0016] Among them, λ model(ij) represents the failure rate model of the j-th electronic component in the i-th circuit board;

[0017] Step S4, construct the board-level failure rate model of the circuit board based on the failure rate model of the electronic components:

[0018]

[0019] Among them, λ model(i) represents the board-level failure rate model of the i-th circuit board, and n represents the number of electronic components included in the i-th circuit board;

[0020] Step S5, constructing an electronic component failure rate model based on the circuit board level failure rate model:

[0021]

[0022] where λ model represents the electronic component failure rate model, and m represents the number of circuit boards included in the electronic component;

[0023] Step S6, constructing an electronic component first failure time model based on the electronic component failure rate model:

[0024]

[0025] where MTTF model represents the electronic component first failure time model;

[0026] Step S7, constructing an electronic component reliability model based on the electronic component failure rate model:

[0027]

[0028] where R model represents the electronic component reliability model;

[0029] Step S8, constructing a reliability digital twin model of the electronic component based on the electronic component first failure time model, the electronic component failure rate model, and the electronic component reliability model:

[0030]

[0031] where RDT represents the reliability digital twin model of the electronic component, and respectively represent the electronic component first failure time model, the failure rate model, and the reliability model that conform to the FMI protocol formed by simulating MTTF model , λ model and R model ;

[0032] Another aspect of the present invention provides a computer device, including a memory, a processor, and a computer program stored on the memory, and the processor executes the computer program to implement the steps of the above method.

[0033] Still another aspect of the present invention provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above method are implemented.

[0034] Another aspect of the present invention provides a computer program product, including a computer program which, when executed by a processor, implements the steps of the above-mentioned method.

[0035] According to the method for constructing an electronic component reliability digital twin model, computer device, computer-readable storage medium and computer program product of the above aspect of the present invention, a complete electronic component reliability digital twin model can be constructed, and the reliability design analysis, test evaluation and diagnostic prediction of electronic components can be realized by digital means. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can also obtain other drawings based on these drawings without creative efforts:

[0037] Figure 1 is a schematic flowchart of a method for constructing an electronic component reliability digital twin model according to an embodiment of the present invention;

[0038] Figure 2 is a structural diagram of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0039] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below in conjunction with the drawings. Obviously, the described embodiments are only some of the embodiments of the present invention, rather than all of them. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0040] The embodiments of the present invention focus on reliability and provide a method for constructing an electronic component reliability digital twin model based on the fusion of mechanism models and simulation models, providing a digital model basis for the reliability design analysis, test evaluation and diagnostic prediction of electronic components. As Figure 1 shown, the method for constructing an electronic component reliability digital twin model according to the embodiment of the present invention includes steps S1 to S8.

[0041] In step S1, input information is determined and a failure mechanism model of electronic components is constructed.

[0042] The premise for constructing an electronic component reliability digital twin model is to first determine its input information, which covers three categories: input of electronic component package information, input of profile information, and input of CAE simulation information.

[0043] Category 1: Input of electronic component packaging information, including information such as component materials, packaging dimensions, load responses, etc.:

[0044] I PA(ij) = I1(M P(ij) , D P(ij) , L S(ij) )

[0045] An electronic component generally contains one or more circuit boards, and a circuit board contains multiple electronic components. Among them, I PA(ij) represents the input of the packaging information of the jth electronic component in the ith circuit board of the electronic component, M P(ij) represents the material property of the jth electronic component in the ith circuit board, D P(ij) represents the dimensional parameter of the jth electronic component in the ith circuit board, L S(ij) represents the load response of the jth electronic component in the ith circuit board.

[0046] Set this type of input information to follow a certain distribution:

[0047]

[0048] Among them, the random variable X = {M P , D P , L S} follows a certain distribution, and the distribution probability function is P(X ≤ x), where x represents a certain value. For electronic components, a normal distribution is generally taken.

[0049] Sample the component packaging information to obtain the input sample space of the component packaging information

[0050]

[0051] PA(ij) is the sample space after sampling the packaging information of the jth electronic component in the ith circuit board, represents sampling the random variable X.

[0052] The purpose of sampling here is to obtain a series of sampled values of the packaging information input of a certain electronic component. Combining with the second type of profile information input and the third type of CAE simulation information input described later, a series of output values of the fault mechanism model can be obtained.

[0053] Category 2: Profile information input, including the temperature and vibration environment profiles to which the components are subjected, which can be expressed as:

[0054] I PR(ij) = I2(T P(ij) , V P(ij) , t T(ij) , tV(ij) )

[0055] Among them, I PR(ij) represents the input of the cross-sectional information of the i-th electronic component in the i-th circuit board, and T P(ij) represents the temperature profile magnitude of the j-th electronic component in the i-th circuit board, and V P(ij) represents the vibration profile magnitude of the j-th electronic component in the i-th circuit board, and t T(ij) represents the duration of the j-th electronic component in the i-th circuit board at each step of the temperature profile, and t V(ij) represents the duration of the j-th electronic component in the i-th circuit board at each step of the vibration profile.

[0056] Category 3: Input of CAE simulation information under different temperature and vibration profile steps. To obtain this CAE simulation information, it is necessary to first input the 3D CAD model, and then perform thermal simulation and vibration simulation on the 3D CAD model at each temperature and vibration profile step.

[0057] Construct the CAD geometric model of the electronic component to describe the dimensional parameters and assembly parameters of the electronic component. The CAD geometric model parameters of the j-th electronic component in the i-th circuit board can be expressed as

[0058] G model(ij) = G(D (ij) , A (ij) )

[0059] Among them, G model(ij) represents the CAD geometric model parameters of the j-th electronic component in the i-th circuit board, D (ij) represents the dimensional parameters of the j-th electronic component in the i-th circuit board, and A (ij) represents the assembly parameters of the j-th electronic component in the i-th circuit board.

[0060] Perform thermal simulation and vibration simulation on the electronic component at each temperature and vibration profile step, and construct the CAE simulation under different temperature and vibration profile steps. The simulation model includes a mechanical simulation model and a thermal simulation model, which can be expressed as:

[0061] M CAEmodel(ij) = M CAE (G model(ij) , M PM(ij) , V P(ij) )

[0062] T CAEmodel(ij) = T CAE (G model(ij) , M PT(ij) , T P(ij) )

[0063] Among them, M CAEmodel(ij) represents the CAE mechanical model of the jth electronic component in the ith circuit board, and T CAEmodel(ij) represents the CAE thermal model of the jth electronic component in the ith circuit board. M PM(ij) represents the mechanical material property of the jth electronic component in the ith circuit board. M PT(ij) represents the thermal material property of the jth electronic component in the ith circuit board. V P(ij) represents the vibration profile magnitude of the jth electronic component in the ith circuit board, and T P(ij) represents the temperature profile magnitude of the jth electronic component in the ith circuit board.

[0064] Then, the input of the CAE simulation model information of the jth electronic component in the ith circuit board can be expressed as:

[0065] I CAE(ij) ={M CAEmodel(ij) , T CAEmodel(ij)}

[0066] Among them, I CAE(ij) represents the input of the CAE simulation model information of the jth electronic component in the ith circuit board.

[0067] With the above three types of input information, a fault mechanism model of the electronic component can be constructed to describe the initial failure time of the constructed electronic component. The fault mechanism model of the component is generally a function of the component package information, profile information, and CAE simulation information. The fault mechanism model of the jth electronic component in the ith circuit board can be expressed as

[0068] M model(ij) =M(I PA(ij) , I PR(ij) , I CAE(ij) )

[0069] Among them, M model(ij) represents the fault mechanism model of the jth electronic component in the ith circuit board.

[0070] In step S2, an initial failure time model of the electronic component is constructed based on the fault mechanism model of the electronic component.

[0071] With the fault mechanism model of the component, an initial failure time model of the component can be constructed to describe the initial failure time of the constructed electronic component. From the fault mechanism model, the initial failure time series sampling values of the jth electronic component in the ith circuit board under the aforementioned profile information input can be obtained. Assuming that the sampling sample has l values, the l initial failure times are sorted from small to large to obtain the sorted sample {M model(ij1) , M model(ij2) , …, Mmodel(ijk) , …M model(ijl)}, two methods can be used to calculate the first failure time of components:

[0072] First, take the median value of the distribution function, that is

[0073]

[0074] where l represents the number of sampling values of the first failure time of the jth electronic component in the ith circuit board in the sampling values, and M model(ijk) represents the kth first failure time model of the jth electronic component in the ith circuit board in the sampling values.

[0075] Second, perform distribution fitting on this series of sampling values, and take the characteristic first failure time or the expected first failure time based on the distribution fraction as the first failure time of each component, that is

[0076] MTTF2 (ij) = E(M model(ij) )

[0077] where E(M model(ij) ) represents the expected first failure time based on distribution fitting.

[0078] Then, the first failure time model of the jth electronic component in the ith circuit board can be expressed as:

[0079] MTTF model(ij) = (MTTF1 (ij) or MTTF2 (ij) )

[0080] where MTTF model(ij) represents the first failure time model of the jth electronic component in the ith circuit board.

[0081] In step S3, based on the first failure time model of the electronic component, a failure rate model of the electronic component is constructed.

[0082] After having the first failure time model of the component, a failure rate model of the component can be constructed to describe the failure rate of the constructed electronic component. The following exponential distribution method is used to calculate the failure rate of the component:

[0083]

[0084] where λ model(ij) represents the failure rate model of the jth electronic component in the ith circuit board.

[0085] In step S4, based on the failure rate model of the electronic component, a board-level failure rate model of the circuit board is constructed.

[0086] After obtaining the component failure rate model, a board-level failure rate model of the circuit board can be constructed to describe the failure rate of the constructed circuit board. The series model method is used to calculate the board-level failure rate as follows:

[0087]

[0088] where λ model(i) represents the board-level failure rate model of the i-th circuit board, and n represents the number of electronic components included in the i-th circuit board.

[0089] In step S5, an electronic component failure rate model is constructed based on the board-level failure rate model of the circuit board.

[0090] After obtaining the board-level failure rate model of the circuit board, an electronic component failure rate model can be constructed to describe the failure rate of the constructed electronic component. The series model method is used to calculate the electronic component failure rate as follows:

[0091]

[0092] where λ model represents the electronic component failure rate model, and m represents the number of circuit boards included in the electronic component.

[0093] In step S6, an electronic component first failure time model is constructed based on the electronic component failure rate model.

[0094] After obtaining the electronic component failure rate model, an electronic component first failure time model can be constructed to describe the first failure time of the constructed electronic component. The exponential distribution method is used to calculate the first failure time of the electronic component as follows:

[0095]

[0096] where MTTF model represents the electronic component first failure time model.

[0097] In step S7, an electronic component reliability model is constructed based on the electronic component failure rate model.

[0098] After obtaining the electronic component failure rate model, an electronic component reliability model can be constructed to describe the reliability of the constructed electronic component. The exponential distribution method is used to calculate the first failure time of the electronic component as follows:

[0099]

[0100] where R model represents the electronic component reliability model.

[0101] In step S8, a reliability digital twin model of the electronic component is constructed based on the electronic component fault first-occurrence time model, the electronic component failure rate model, and the electronic component reliability model.

[0102] After constructing the failure rate, reliability, and fault first-occurrence time models of the electronic component, it is necessary to construct the reliability digital twin model of the electronic component. The steps are as follows:

[0103] Using the Simulink module in Matlab software, the mathematical expressions of the obtained failure rate and fault first-occurrence time models of the electronic component are used to create a simulation model in the Simulink environment. Configure the step size mode and step size value for model solving, and export the functional model unit FMU of the electronic component that conforms to the FMI (Functional Mock-up Interface) standard, that is

[0104]

[0105] Among them, FMU represents the functional model unit of the electronic component, represents the mechanism model of the electronic component that conforms to the FMI protocol, respectively represent MTTF model 、λ model and R model The fault first-occurrence time model, failure rate model, and reliability model of the electronic component that conform to the FMI protocol formed through simulation.

[0106] Since this FMU has fast computing capabilities and a general FMI interface for system simulation, it can be used as the reliability digital twin model of the electronic component:

[0107] RDT = FMU

[0108] Among them, RDT represents the reliability digital twin model of the electronic component.

[0109] In summary, the method of the embodiment of the present invention focuses on reliability. By establishing a reliability digital twin model of the electronic component, it realizes the simulation, monitoring, diagnosis, prediction, and control of reliability indicators such as the failure rate, reliability, life, and remaining life of the electronic component, thereby using digital means to achieve the reliability design analysis, test evaluation, and diagnosis prediction of the electronic component, greatly shortening the product iteration and upgrade cycle, and significantly reducing the R & D and use costs of the electronic component.

[0110] The embodiment of the present invention also provides a computer device. This computer device can be a server, and its internal structure diagram can be as Figure 2As shown. The computer device includes a processor, a memory, and a network interface connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store the operation parameter data of each framework. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, the steps of the method according to the embodiments of the present invention are implemented.

[0111] Those skilled in the art can understand that Figure 2 the structure shown in is only a block diagram of some structures related to the solution of this application, and does not constitute a limitation on the computer device to which the solution of this application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0112] An embodiment of the present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method according to the embodiments of the present invention are implemented.

[0113] An embodiment of the present invention also provides a computer program product, including a computer program. When the computer program is executed by a processor, the steps of the method according to the embodiments of the present invention are implemented.

[0114] Only some exemplary embodiments of the present invention have been described above by way of illustration. Undoubtedly, for those of ordinary skill in the art, without departing from the spirit and scope of the present invention, the described embodiments can be modified in various different ways. Therefore, the above drawings and descriptions are illustrative in nature and should not be construed as limiting the protection scope of the claims of the present invention.

Claims

1. A method for constructing a digital twin model of the reliability of electronic components, characterized in that Including: Step S1: Determine the input information and construct a failure mechanism model of electronic components. M model(ij) = M(I PA(ij) , I PR(ij) , I CAE(ij) ) Among them, M model(ij) represents the failure mechanism model of the j-th electronic component in the i-th circuit board of the electronic component, I PA(ij) represents the input of the packaging information of the j-th electronic component in the i-th circuit board, I PR(ij) represents the input of the cross-sectional information of the j-th electronic component in the i-th circuit board, I CAE(ij) represents the input of the CAE simulation model information of the j-th electronic component in the i-th circuit board; Step S2: Obtain the sampling values of the first failure time series of all electronic components from the failure mechanism model of electronic components, and construct a first failure time model of electronic components. Among them, MTTF model(ij) represents the first failure time model of the j-th electronic component in the i-th circuit board, l represents the number of first failure time sampling values of the j-th electronic component in the i-th circuit board in the sampling values, M model(ijk) represents the k-th first failure time model of the j-th electronic component in the i-th circuit board in the sampling values; or MTTF model(ij) = E(M model(ij) ) where, E(M model(ij) ) represents the expected first failure time based on the distribution fitting of a series of sampled values; Step S3: Construct a failure rate model of electronic components based on the first failure time model of electronic components. Among them, λ model(ij) represents the failure rate model of the j-th electronic component in the i-th circuit board; Step S4: Construct a board-level failure rate model of a circuit board based on the failure rate model of electronic components. Among them, λ model(i) represents the board-level failure rate model of the i-th circuit board, and n represents the number of electronic components included in the i-th circuit board; Step S5: Construct a failure rate model of an electronic component based on the board-level failure rate model of a circuit board. Among them, λ model represents the failure rate model of the electronic component, and m represents the number of circuit boards included in the electronic component; Step S6: Construct a first failure time model of an electronic component based on the failure rate model of the electronic component. Among them, MTTF model represents the first failure time model of electronic components; Step S7: Construct a reliability model of an electronic component based on the failure rate model of the electronic component. Among them, R model represents the reliability model of electronic components; Step S8: Construct a reliability digital twin model of an electronic component based on the first failure time model, the failure rate model, and the reliability model of the electronic component. Among them, RDT represents the reliability digital twin model of electronic components, and respectively represent MTTF model , λ model and R model The time-to-first-failure model, failure rate model, and reliability model of electronic components that conform to the FMI protocol formed through simulation.

2. The method according to claim 1, wherein The input representation of the package information of the electronic component is: I PA(ij) = I1(M P(ij) , D P(ij) , L S(ij) ) Among them, I PA(ij) represents the input of the package information of the jth electronic component in the ith circuit board, M P(ij) represents the material property of the jth electronic component in the ith circuit board, D P(ij) represents the dimensional parameter of the jth electronic component in the ith circuit board, L S(ij) represents the load response of the jth electronic component in the ith circuit board.

3. The method according to claim 1 or 2, characterized in that, The input representation of the cross-sectional information of the electronic component is: I PR(ij) = I2(T P(ij) , V P(ij) , t T(ij) , t V(ij) ) Among them, I PR(ij) represents the input of the cross-sectional information of the i-th electronic component in the i-th circuit board, T P(ij) represents the temperature profile magnitude of the j-th electronic component in the i-th circuit board, V P(ij) represents the vibration profile magnitude of the j-th electronic component in the i-th circuit board, t T(ij) represents the duration of the j-th electronic component in the i-th circuit board at each step of the temperature profile, t V(ij) represents the duration of the j-th electronic component in the i-th circuit board at each step of the vibration profile.

4. The method according to claim 1 or 2, characterized in that, The input representation of the CAE simulation model information of the electronic component is: I CAE(ij) = {M CAEmodel(ij) , T CAEmodel(ij)} Among them, I CAE(ij) represents the input of the CAE simulation model information of the jth electronic component in the ith circuit board; M CAEmodel(ij) = M CAE (G model(ij) , M PM(ij) , V P(ij) ) T CAEmodel(ij) = T CAE (G model(ij) , M PT(ij) , T P(ij) ) Among them, M CAEmodel(ij) represents the CAE mechanical model of the j-th electronic component in the i-th circuit board, and T CAEmodel(ij) represents the CAE thermal model of the j-th electronic component in the i-th circuit board, and M PM(ij) represents the mechanical material property of the j-th electronic component in the i-th circuit board, and M PT(ij) represents the thermal material property of the j-th electronic component in the i-th circuit board, and V P(ij) represents the vibration profile magnitude of the j-th electronic component in the i-th circuit board, and T P(ij) represents the temperature profile magnitude of the j-th electronic component in the i-th circuit board; G model(ij) = G(D (ij) , A (ij) ) Among them, G model(ij) represents the CAD geometric model parameters of the j-th electronic component in the i-th circuit board, D (ij) represents the dimensional parameters of the j-th electronic component in the i-th circuit board, A (ij) represents the assembly parameters of the j-th electronic component in the i-th circuit board.

5. A computer device, comprising a memory, a processor, and a computer program stored on the memory, characterized in that, The processor executes the computer program to implement the steps of the method according to any one of claims 1-4.

6. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the method according to any one of claims 1-4.

7. A computer program product, including a computer program, which implements the steps of the method according to any one of claims 1-4 when executed by the processor.

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