An online-learning neuromorphic processor based on approximate computation

Abstract

This invention relates to an online-learnable neuromorphic processor based on approximate computation, comprising: a communication subsystem, a training subsystem, and an inference subsystem; the communication subsystem is used to construct a multi-pulse core neuromorphic processor with a hierarchical routing architecture; the training subsystem is used to optimize the weights and threshold parameters of the multi-pulse core neuromorphic processor using an online learning method; the inference subsystem is used for the multi-pulse core neuromorphic processor, after online training or offline weight deployment, to perform inference on encoded input image data and generate the classification output of the multi-pulse core neuromorphic processor. This invention proposes a neuromorphic processor architecture based on online learning and approximate computation to achieve a high degree of trade-off between accuracy, energy efficiency, and response speed, enabling real-time and efficient processing of dynamic and complex task data.

Description

Technical Field

[0001] This invention relates to the field of neuromorphic processor design technology, and in particular to an online learning neuromorphic processor based on approximate computation. Background Technology

[0002] Neuromorphic processors based on spiking neural networks (SNNs) aim to simulate the function of the brain's neural networks through biomimetic principles and hardware design, achieving efficient computation and task processing, particularly with online learning and event-driven characteristics. Neuromorphic processors are an important research direction in neuromorphic computing, with wide applications in fields such as medical image processing, autonomous driving, intelligent monitoring systems, and smart transportation. Unlike traditional circuits based on artificial neural networks (e.g., convolutional neural networks (CNNs)), which use continuous signal processing and fixed training models, these methods are less efficient when handling dynamic and sparse data. Furthermore, because CNN-based hardware circuits cannot fully simulate the brain's biological characteristics and dynamic learning capabilities, they rely on offline training, resulting in poor adaptability and energy efficiency for real-time applications and resource-constrained environments.

[0003] Current digital spiking neuromorphic processors suffer from key issues such as high hardware resource overhead, low neuron computational efficiency, limitations of online learning methods, and low flexibility in inter-chip communication, hindering their practical application. Among these, the spiking neuron is the computational core of neuromorphic chips, but current spiking neurons suffer from high resource overhead and low computational efficiency. For example, the current-based Leaky Integrate-and-Fire (LIF) model offers the advantage of configurable neuron behavior, but its complex membrane potential transitions introduce additional overhead. ODIN employs both LIF neurons and the more biologically accurate Izhikevich (Izh) neuron model. The LIF neuron model lacks hardware optimization, resulting in low computational efficiency, while the Izh neuron model, although simulating dozens of neuron behaviors, introduces highly complex control logic and additional resource consumption. Due to the complex neuron computation in neural networks, many studies have applied approximate computational techniques such as weight quantization and pruning to neuron circuits, but these have problems such as significantly reducing the accuracy of neural network models. Secondly, existing SNN processors typically lack online learning capabilities or are poorly optimized. Due to computational complexity and cost considerations, many existing SNN processors, such as TrueNorth, Tsinghua Tianjic, and SpiNNaker, lack on-chip learning capabilities, limiting them to offline weight deployment and making them unsuitable for adapting to changing real-world scenarios. Other neuromorphic chips with online learning capabilities, such as those using Spiking-Timing-Dependent Plasticity (STDP), can design different learning rules in microcode format. However, these rules are complex and consume significant hardware resources during implementation. ODIN uses a simplified STDP-based Spike-Driven Synaptic Plasticity (SDSP) learning rule, but overly simplistic rules can lead to overfitting in the neural network, resulting in decreased recognition accuracy. Furthermore, existing hardware implementations lack flexible on-chip routing control. Neuromorphic chips primarily update neuron states and synaptic weights in real time based on pulse information. To adapt to different time windows and multi-scale input images, a certain level of routing and scheduling is required to control the correctness and flexibility of the spiking neural network's operation. Existing technologies typically require customized neuron storage space and perform row and column storage access to neuron states. However, fixed storage space limits the processor's applicability to large neural networks.Another common solution is to fix the input time window to be the same. This is because if the time window size is different for each layer, the processing time for each layer will vary. Since the core completes its operation for that layer but must wait until the previous layer finishes its computation, this leads to a waste of computational resources. However, with increasingly complex computational demands, designing on-chip routers to handle the computation of large networks and support processing different time windows is an inevitable trend. Summary of the Invention

[0004] The purpose of this invention is to address the technical problems of existing neuromorphic processors, such as high hardware resource consumption, low computational efficiency, limited online learning capabilities, and insufficient routing scheduling, thereby achieving more efficient neuromorphic computing results. Aiming at applying neuromorphic processor technology to real-time intelligent computing, this invention proposes an online-learning neuromorphic processor architecture based on approximate computation to achieve a high degree of trade-off between recognition accuracy, response speed, and hardware resource consumption, enabling accurate, real-time, and efficient processing of dynamic and complex image target recognition tasks.

[0005] This invention proposes a processor design system capable of dynamically updating and efficiently processing complex tasks by combining a bio-inspired computational model and hardware design. It presents a low-power, high-precision, online-learning processor based on a spiking neural network, capable of efficiently simulating the complex computational functions of a biological nervous system. This design system not only significantly improves computational speed and energy efficiency but also reduces the hardware resource consumption of the processor design. This system is applicable to various industries requiring neural network computation, such as medical image processing, autonomous driving, intelligent monitoring systems, and smart transportation, thereby addressing the problems existing in the prior art.

[0006] To achieve the above objectives, the present invention provides the following solution:

[0007] An online learnable neuromorphic processor based on approximate computation includes: an inference subsystem, a training subsystem, and a communication subsystem;

[0008] The inference subsystem includes an input layer, a hidden layer, and an output layer. The hidden layer includes multiple parallel pulse processing kernels, and the output layer includes at least one pulse processing kernel. Each pulse processing kernel includes multiple physical neurons established using a preset neuron model.

[0009] The inference subsystem is used to perform approximate calculations on the multi-scale input image after encoding and input to the input layer based on the pre-stored synaptic weights and activation thresholds, through the pulse processing kernels in the hidden layer and the output layer, to statistically analyze the calculation results of multiple time steps within a time window, and generate the recognition result of the multi-scale input image.

[0010] The training subsystem is used to access multiple images from the input layer to the hidden layer and the output layer, and to update the synaptic weights and the activation threshold using a random online learning method based on historical weights.

[0011] The inference subsystem is also used to update the recognition results of the multi-scale input image by performing approximate calculations through the pulse processing kernels in the hidden layer and the output layer based on the updated synaptic weights and activation thresholds after training.

[0012] The communication subsystem is used to perform multi-level routing control on the data transmission between the inference subsystem and the training subsystem through a hierarchical routing architecture.

[0013] Optionally, the input layer includes multiple virtual neurons, the number of which matches the scale of the input image, for accessing the pulse sequence of the binarized image after rate encoding of the input image;

[0014] Both the hidden layer and the output layer have built-in synaptic kernels and neuron computation kernels in their pulse processing kernels; the synaptic kernels pre-store synaptic weights obtained through pre-training; the neuron computation kernels pre-store activation thresholds obtained through pre-training; the neuron computation kernels have built-in multiple physical neurons; the multiple physical neurons form a pipeline structure to sequentially pass the pulse sequence of the input binarized image.

[0015] Optionally, each physical neuron includes: a PE array composed of multiple approximate computation units, an approximate addition tree, and a pulse firing decision unit; the approximate computation unit has a built-in accumulation control logic circuit and at least one approximate adder; the approximate addition tree is composed of multiple approximate adders added in pairs in a hierarchical manner;

[0016] The PE array is used to receive local pulse sequences of the binarized image in batches and distribute each pulse of the local pulse sequence to the corresponding approximate calculation unit for independent parallel summation; and by time-division multiplexing the multiple approximate calculation units, the cumulative calculation of multiple local pulse sequences of the binarized image is performed in batches to obtain the membrane potential increment accumulated by each approximate calculation unit.

[0017] Each of the approximate calculation units is also used to update the local membrane potential of the physical neuron distributed in the current approximate calculation unit at the current time using the membrane potential increment accumulated at each batch time according to the preset neuron model.

[0018] The approximate addition tree is used to sum the local membrane potentials output by each approximate calculation unit to obtain the membrane potentials corresponding to the physical neurons and the accessed binarized images.

[0019] The pulse firing decision unit is used to compare the membrane potential summarized by the approximate addition tree with the activation threshold to determine whether to activate the current physical neuron; if the current physical neuron is not activated, the membrane potential of the current physical neuron is decayed according to the preset neuron model; if the current physical neuron is activated, a new pulse is fired to the next layer of neurons, and after the physical neuron is activated and a pulse is fired, the membrane potential of the current neuron is reset according to the preset neuron model.

[0020] Optionally, the neuron model includes a neuron charging model, the mathematical model of which is:

[0021] V(t) = V(t-1) + X(t),

[0022] or

[0023]

[0024] or

[0025]

[0026] Where V(t) is the membrane potential of the neuron at the current moment, V(t-1) is the membrane potential of the neuron at the previous moment, and X(t) is the membrane potential increment caused by the input pulse at the current moment. V is the preset membrane potential attenuation factor; rst This is the reset reference potential for neurons.

[0027] Optionally, the neuron model includes a neuron reset model:

[0028] V(t + ) = V rst ,

[0029] or

[0030]

[0031] Wherein, the V(t) + V(t) represents the neuron's post-reset membrane potential at the current moment. - V represents the neuron's reset presynaptic membrane potential at the current moment; rst This is the preset reset reference potential; V is the preset membrane potential attenuation factor; th This represents the activation threshold of the current neuron.

[0032] Optionally, the training subsystem includes: a controller, a neuron comparator, an update arbitrator, a random number generator, and a parameter updater;

[0033] The controller is used to control the duration of the input pulse sequence received by the neuron, and to control the correct timing and functional operation of the training subsystem.

[0034] The neuron comparator is used to compare the activation states of different physical neurons and select the most active physical neuron based on the pulse firing rate.

[0035] The update arbitrator is used to receive the output of the neuron comparator and send the most active physical neuron to the parameter updater.

[0036] The random number generator is used to generate pseudo-random numbers based on a linear feedback shift register and by using shift operations.

[0037] The parameter updater is used for a random online learning strategy based on historical weights, and updates the synaptic weights and activation thresholds of the most active physical neurons using the pseudo-random numbers and the currently stored synaptic weights of the neurons.

[0038] Optionally, the random online learning strategy based on historical weights specifically includes:

[0039] If the difference between the current membrane potential of the physical neuron and the current activation threshold is greater than the pseudo-random number, then the synaptic weights and activation threshold of the current physical neuron are updated according to the following mathematical model:

[0040]

[0041] Where W(t) represents the updated synaptic weights, W(t-1) represents the original synaptic weights, and V th (t) represents the updated activation threshold, V th (t-1) represents the activation threshold before the update, Δt represents the time difference between the release of pulses by the preneuron and the postneuron, a and b represent the two different weight update magnitudes, and c represents the update magnitude of the activation threshold.

[0042] Otherwise, the synaptic weights and activation thresholds of the physical neuron remain unchanged at the current moment.

[0043] Optionally, the neuron comparator selects the most active physical neuron based on the pulse firing rate, specifically:

[0044] The cumulative membrane potential of the input pulse sequence is obtained by performing a weighted summation of each pulse signal in the input pulse sequence with the synaptic weight corresponding to the current physical neuron.

[0045] The cumulative membrane potential is subtracted from the activation threshold of the current physical neuron to obtain the cumulative difference.

[0046] The trigger timing is assigned to each pulse signal in the input pulse sequence in sequence; and the pulse signals with trigger timing are weighted and summed with the synaptic weights corresponding to the current physical neuron to obtain the time-weighted membrane potential of the input pulse sequence.

[0047] The ratio of the time-weighted membrane potential to the cumulative difference is used as the normalized pulse firing duration of the current physical neuron;

[0048] The normalized pulse firing duration of all physical neurons in the hidden layer is compared one by one, and the neuron corresponding to the minimum value is selected as the most active physical neuron in the hidden layer.

[0049] The normalized pulse firing duration of all physical neurons in the output layer is compared one by one, and the neuron corresponding to the minimum value is the most active physical neuron in the output layer.

[0050] Optionally, the approximate adder is a speculative carry adder with error correction mechanism.

[0051] Optionally, the communication subsystem is a three-level routing system, including: a level 0 router, a level 1 router, and a level 2 router;

[0052] The zero-level router is located inside each pulse processing core and is used to transmit the encapsulation signal of the first-level router to the corresponding pulse processing core, and to re-encapsulate the calculation result of the pulse processing core into a data packet and send it to the first-level router.

[0053] The first-level router is used to collect and encapsulate the data from the zero-level router according to a preset communication protocol, so as to realize the communication transmission of data between various pulse processing cores.

[0054] The secondary router is used to collect the output data of the primary router according to a preset communication protocol, so as to realize data communication between multiple neuromorphic processors composed of pulse processing core clusters, or data communication between the neuromorphic processor and external circuits.

[0055] The beneficial effects of this invention are as follows:

[0056] This invention proposes a structurally optimized, online-learning neuromorphic processor. By designing a hardware-friendly neuron structure, a high-precision approximation calculation circuit, an improved online learning method, and a flexible three-level on-chip communication routing, combined with the computational characteristics of spiking neural networks, a neuromorphic processor with low power consumption, high computational efficiency, and high recognition accuracy is obtained. Attached Figure Description

[0057] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0058] Figure 1 This is a schematic diagram illustrating the principle of a specific structure of an online learning neuromorphic processor based on approximate computation, according to an embodiment of the present invention.

[0059] Figure 2 This is a schematic diagram of the principle structure of a hidden layer pulse processing kernel according to an embodiment of the present invention;

[0060] Figure 3 This is a schematic diagram of the principle structure of the output layer pulse processing core according to an embodiment of the present invention;

[0061] Figure 4 This is a structural block diagram of the multi-pulse core neuromorphic processor according to an embodiment of the present invention;

[0062] Figure 5 This is a circuit architecture diagram of the pulse processing core according to an embodiment of the present invention;

[0063] Figure 6 This is a flowchart of the method for selecting the most active neuron based on a competitive learning strategy according to an embodiment of the present invention;

[0064] Figure 7 The flowchart of the update algorithm for selecting the most active neuron in the hidden or output layer of the network based on the normalized pulse firing duration is shown in the embodiment of the present invention.

[0065] Figure 8 This is a schematic diagram of the encapsulation format of a data packet distributed in various levels of routing according to an embodiment of the present invention;

[0066] Figure 9 This is a schematic diagram of an implementable structure of a secondary router in an on-chip three-level router according to an embodiment of the present invention;

[0067] Figure 10 This is a partial structural diagram of a neuromorphic processor built using a three-level on-chip routing architecture combined with a multi-pulse processing core, according to an embodiment of the present invention. Detailed Implementation

[0068] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0069] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0070] This embodiment proposes an online learnable neuromorphic processor based on approximate computation, including: an inference subsystem, a training subsystem, and a communication subsystem. For example... Figure 1 The diagram shown is a schematic diagram of a specific structure of an online learning neuromorphic processor based on approximate calculation provided in an embodiment of the present invention.

[0071] The inference subsystem includes an input layer, a hidden layer, and an output layer. The hidden layer includes multiple parallel pulse processing kernels, and the output layer includes at least one pulse processing kernel. Each pulse processing kernel includes multiple physical neurons built using a preset neuron model. For example, ... Figure 1 The neuromorphic processor shown has four spiking cores in its hidden layer and one spiking core in its output layer. The spiking cores 1-4 in each hidden layer have the same structure, as shown below. Figure 2 As shown; the structure of the output layer pulse processing core is as follows Figure 3 As shown, the hidden layer spiking kernel and the output layer spiking kernel have the same structural design principle, but the number and function of neurons in the current network layer will differ depending on the input signal and position of the current network layer. In a preferred implementation, the hidden layer spiking kernel is constructed based on the IF neuron model, and the output layer spiking kernel is constructed based on the LIF neuron model, which can achieve higher recognition accuracy.

[0072] The inference subsystem is used to perform approximate calculations on the multi-scale input image after encoding and input to the input layer through the pulse processing kernel in the hidden layer and the output layer, based on the pre-stored synaptic weights and activation thresholds, and to generate the recognition result of the multi-scale input image by statistically analyzing the calculation results of multiple time steps within a time window.

[0073] The training subsystem is used to input multiple images into the hidden layer and the output layer using the input layer, and to update the synaptic weights and the activation threshold using a random online learning method based on historical weights.

[0074] The inference subsystem is also used to update the recognition results of the multi-scale input image by performing approximate calculations through the spur processing kernels in the hidden layer and the output layer based on the trained and updated synaptic weights and activation thresholds.

[0075] The communication subsystem is used to perform multi-level routing control on the data transmission between the inference subsystem and the training subsystem through a hierarchical routing architecture.

[0076] Preferably, such as Figure 4 As shown, in this embodiment of the invention, the input layer includes multiple virtual neurons, the number of which matches the scale of the input image, and is used to access the pulse sequence of the binarized image after rate encoding of the input image;

[0077] like Figure 5 As shown, both the spiking kernels in the hidden layer and the output layer have a built-in synaptic kernel 300 and a neuron computation kernel 400; the synaptic kernel 300 pre-stores synaptic weights W obtained through pre-training; the neuron computation kernel 400 pre-stores activation thresholds V obtained through pre-training. th The neuron computation kernel 400 contains multiple physical neurons (NEs); these multiple physical neurons (NEs) form a pipeline structure, sequentially transmitting the pulse sequence of the input binarized image. In specific implementations, the number of physical neurons (NEs) built into the neuron computation kernel 400 can differ between the pulse processing kernels in the hidden layer and the output layer. In a preferred embodiment, the number of physical neurons (NEs) in the hidden layer is 20, and the number of physical neurons (NEs) in the output layer matches the total number of object categories to be identified. For example, for the MNIST dataset of handwritten digits 0-9, the number of physical neurons (NEs) in the output layer should be 10.

[0078] Unlike traditional ANNs, which can directly receive pixel values ​​from an image, SNNs are driven by pulse sequences. Therefore, before a two-dimensional image is input into an SNN, the image needs to undergo a series of preprocessing steps.

[0079] Preferably, the online learning neuromorphic processor based on approximate calculation further includes a pulse encoder, used to rate-encode the input digital image according to a preset time step to generate multiple frames of binarized images; the pulse encoder is also used to send the pulse sequence of each frame of the binarized image in batches to the corresponding physical neurons in the hidden layer to perform parallel membrane potential calculation in an entire row or column manner; or, to send the pulse sequence of each frame of the binarized image to the corresponding pulse processing kernel in the hidden layer at once to perform parallel membrane potential calculation in an entire frame manner.

[0080] In one feasible implementation, embodiments of the present invention downsample an input image of arbitrary size to obtain an image with a width (M) × height (N) pixels, and then encode the input image into a pulse sequence with a firing number conforming to a Poisson process through rate coding, such as Poisson coding:

[0081]

[0082] Where M and N represent the number of image pixels with variable scale, P represents the probability that the random variable X takes the value k, which should be normalized to [0,1], k represents the number of times the event occurs, and λ represents the average number of times the event occurs, also known as the parameter or average rate of the Poisson distribution. It represents the expected number of times the event occurs within a given time period or region.

[0083] Therefore, the pulse input process for multi-scale images implemented in this invention using Poisson coding is as follows: First, a time step size of T is set. In each time step, the probability of each pixel generating a pulse is proportional to the size of that pixel value. Then, several time steps are executed to obtain the pulse sequence generated by each pixel. Finally, the pulse sequence generated by each pixel is input into the corresponding SNN input layer neuron through an external interface.

[0084] Preferably, the online learnable neuromorphic processor based on approximate computation further includes a neuron timing generator 100 (e.g., Figure 5 (As shown). The neuron timing generator 100 is used to generate the time step of the control pulse sequence input to the physical neurons. This time step can control the pulse coding length of each pixel in the input image after rate coding, thereby affecting the representation accuracy of each pixel value and the recognition accuracy obtained after calculation by the pulse processing kernel. Therefore, for a whole frame of input image, after rate coding, a number of multi-frame binarized images corresponding to the time step can be obtained according to the time step. The pixel values ​​of each frame of binarized image form a pulse sequence, which is distributed to the input layer of the pulse processing kernel by the controller 200 in the form of whole rows, whole columns or whole frames, thereby starting the calculation of each physical neuron in the hidden layer and output layer in sequence according to the preset neuron model.

[0085] Because spiking neural networks (SNNs) allow for various forms of synaptic connections, including different types of neurons, to simulate the diversity of neurons in biological systems, SNNs can better simulate information processing in biological nervous systems, enabling higher-level neural computation. In this embodiment of the invention, to flexibly adapt to the neuron model in the spiking neural network, two neuron models are used: Integrate and Fire (IF) neurons and Leaky Integrate and Fire (LIF) neurons.

[0086] The IF neuron model is an ideal integrator model, characterized by a constant membrane potential of the neuron when there is no input. The basic equation (charging equation) of the IF neuron model is:

[0087]

[0088] Where I(t) is the input current, V(t) is the membrane potential, and C is the membrane capacitance.

[0089] In practical implementation, because the pulse input signal of a spiking neural network (SNN) is discrete, it is difficult to obtain the input current I(t) by performing differentiation operations using continuous signal calculation methods when implementing it on digital circuit hardware. To adapt the spiking neural network model to digital circuit hardware, this invention improves both of the above models to obtain a hardware-friendly neuromorphic processor based on spiking neural networks.

[0090] For the original IF neuron model, this invention approximates the continuous-time differential equation as a discrete-time recursive equation. Therefore, within the discrete time step Δt, the differential term can be approximately equivalent to:

[0091]

[0092] The charging equation (also known as the neuron dynamic equation) of the IF neuron model can be equivalently expressed as:

[0093]

[0094] This equation is the neurodynamic equation for the current physical neuron before it reaches the activation threshold, describing the change in the membrane potential of the current physical neuron before it reaches the threshold potential required to fire a pulse (pulse value of 1).

[0095] For the LIF neuron model, the effect of leakage conductance on the membrane potential changes of the physical neuron needs to be considered. When there is no input current (pulse value of 0), the membrane potential gradually recovers to the resting potential, which simulates the natural diffusion process of ions through the membrane. The basic equation (charging equation) of the LIF model is:

[0096]

[0097] Where g is the leakage conductance and E is the resting potential of the neuron, this equation describes the relationship between the input current, membrane potential, and decay. Similarly, the differential equation (neuron dynamics equation) of the LIF neuron charging model can be approximated as a recursive equation for a discrete-time signal.

[0098] In this embodiment of the invention, the pulse sequence is input serially according to the overall clock step of the digital circuit system. Simultaneously, multiple pulses (0 or 1) can be combined into a multi-bit digital signal and input in parallel to the neuron for parallel computation. Within the accumulated discrete time step Δt, for the SNN, the pulse sequence input current I(t) primarily affects the increment X(t) of the neuron's membrane potential. Therefore, the membrane potential increment X(t) can be obtained by multiplying the input current I(t) and the time step Δt, i.e., X(t) = I(t)·Δt.

[0099] In this embodiment of the invention, the pulse sequence of the binarized image obtained after rate encoding of the input image is input into a physical neuron. The real-time membrane potential of the physical neuron is calculated according to a preset neuron charging model, and a decision is made on whether to fire a pulse to the next layer of physical neurons. The neuron model provided in this embodiment of the invention includes a neuron charging model.

[0100] In a preferred embodiment, after improving the above-mentioned IF neuron model, the mathematical model of the neuron charging model is as follows:

[0101] V(t) = V(t-1) + X(t),

[0102] Alternatively, by improving the LIF neuron model, the following results were obtained:

[0103] Neuron charging model that does not decay the input pulse:

[0104]

[0105] Alternatively, a neuron charging model that attenuates the input pulse:

[0106]

[0107] Where V(t) is the membrane potential of the neuron at the current moment, V(t-1) is the membrane potential of the neuron at the previous moment, and X(t) is the membrane potential increment caused by the input pulse at the current moment. V is the preset membrane potential attenuation factor; rst This is the reset reference potential for neurons.

[0108] In practice, when using a LIF neuron charging model that does not attenuate the input pulse, the increment of the membrane potential X(t) directly affects the neuron's membrane potential, which is then adjusted according to the attenuation factor. Adjusting the membrane potential from the previous moment and resetting the reference potential V rst The difference, i.e., the membrane potential is simultaneously adjusted relative to the reset reference potential V. rst The decay of the membrane potential. When using a LIF neuron charging model that decays the input pulse, the increment of the membrane potential X(t) also participates in the decay. The change in the overall membrane potential of the neuron considers both the influence of the input membrane potential increment and the natural decay of the membrane potential relative to the reset potential. In the neurodynamic equations of the two optimized LIF neuron charging models above, τ is a time constant, which can be selected according to the needs of the neuron model, biological rationality, etc. Preferably, if the physical neuron needs to respond quickly to rapidly changing input pulse signals, a smaller τ (a larger decay factor) is selected so that the membrane potential can decay faster; and vice versa. This selection method mainly imitates the response mechanism of actual biological neurons. For example, fast-rhythmic neurons in the cerebral cortex usually have a smaller time constant (a larger decay factor), while neurons related to memory and learning usually have a larger time constant (a smaller decay factor). In biological neuroscience, a τ value consistent with the behavior of actual biological neurons is selected. As for the reset reference potential V... rst The preferred setting is V. rst Setting it below the resting membrane potential E aims to keep the neuron in the refractory period after activation, mimicking the behavior of real biological neurons and preventing overactivation. This mechanism is very common in biological nervous systems.

[0109] The optimized IF neuron model in this embodiment maintains a constant membrane potential in the absence of pulse input. This model is suitable for computational units that require high sensitivity because any tiny input current can rapidly affect the membrane potential, enabling the neuron to respond quickly to the input signal.

[0110] The optimized LIF neuron model in this embodiment considers the natural decay of membrane potential; when there is no input, the membrane potential gradually returns to the resting potential. This model more closely resembles the behavior of biological neurons, making it suitable for simulating real biological signal processing, while also possessing a certain degree of noise resistance.

[0111] In this embodiment, the neuron models of the physical neurons in the hidden and output layers can be selected based on the characteristics of the input image, choosing between different types of neuron models (including IF neuron models and LIF neuron models). Specifically, for images with varied and complex details, the LIF neuron model is preferred because it simulates the dynamic characteristics of biological neurons, namely the leakage of neuronal membrane potential and the refractory period. This helps extract time-related features from the input image, enhances the feature representation of subtle differences, and adapts to more varied and complex input images. For input images with simpler textures, the IF neuron model is preferred because the membrane potential of IF neurons does not leak and remains constant until it reaches the activation state. It is more sensitive to changes in pulses and is suitable for processing simpler input images with more obvious features, enabling fast and accurate target classification and recognition. For example, by combining the characteristics of both types of neurons, using LIF neurons in the hidden layer can enhance the feature representation of the input image and extract subtle features. After extraction by the hidden layer, the IF neurons in the output layer can quickly and accurately complete the classification based on the pulse sequences of these significant features, achieving better inference performance (recognition accuracy).

[0112] At each time step, if no neuronal activation event occurs, the leaked neuronal membrane potential will be stored for use by neuronal events in the next time step. As time accumulates, the neuronal membrane potential can change in real time with the number and frequency of input pulses. If, according to the above neuronal charging model, the neuron generates a corresponding neuronal pulse firing event for the membrane potential increment X(t) formed by multiple input pulses, i.e., the neuron is activated and emits a pulse (signal "1"), then the neuron model will simulate the actual biological neuron behavior and reset the neuron's potential state.

[0113] Specifically, the neuron model includes a neuron reset model. The neuron reset model includes a hard mode:

[0114] V(t + ) = V rst ,

[0115] Alternatively, Soft mode:

[0116]

[0117] Wherein, the V(t) + V(t) represents the neuron's post-reset membrane potential at the current moment. - V represents the neuron's reset presynaptic membrane potential at the current moment; rst This is the preset reset reference potential; V is the preset membrane potential attenuation factor; thThis represents the activation threshold of the current neuron.

[0118] Therefore, in hard mode, the neuronal membrane potential is reset directly to a pre-set reset reference potential; while in soft mode, the membrane potential is not reset, but is reset based on the decay factor and the activation threshold of the current membrane potential.

[0119] During the inference process, the neuromorphic processor provided in this embodiment of the invention can be used to perform target recognition on the input image. Specifically, the input image is encoded and converted into a pulse sequence of a binary image with a corresponding time step. This pulse sequence code stream is input to the input layer of the neuromorphic processor. Based on the design principle of the neuron model described above, through layer-by-layer calculations between the hidden layer physical neurons and the output layer physical neurons, the category label of the input image can be quickly and intelligently recognized through the firing and propagation of pulses.

[0120] This invention further implements the physical neurons of each pulse processing core in the hidden layer and the output layer based on digital circuits to achieve high-speed processing and low-power neuron activation and reset. In a preferred implementation, the circuit structures of each physical neuron in the hidden layer and the output layer are the same, but the synaptic weights they are connected to can differ according to the training update based on the input pulses. Therefore, the membrane potential and activation state of each physical neuron are not consistent during real-time calculation.

[0121] In a preferred embodiment, such as Figure 5 As shown, each physical neuron (NE) includes: an array of PE (Processing Element) consisting of multiple Approximate Computational Units (ACUs), an approximate addition tree, and a pulse firing decision unit; the approximate computational unit has a built-in accumulation control logic circuit and at least one approximate adder; the approximate addition tree is composed of multiple approximate adders added in pairs in a hierarchical manner.

[0122] The PE array is used to receive local pulse sequences of the binarized image in batches and distribute each pulse of the local pulse sequence to the corresponding approximate calculation unit for independent parallel summation; and by time-division multiplexing the multiple approximate calculation units, the cumulative calculation of multiple local pulse sequences of the binarized image is performed in batches to obtain the membrane potential increment accumulated by each approximate calculation unit.

[0123] Each of the aforementioned approximate computing units (ACUs) is also used to update the local membrane potential of the physical neuron distributed in the current approximate computing unit at the current time, based on the membrane potential increment accumulated at each batch of time according to the preset neuron model.

[0124] The approximate addition tree is used to sum the local membrane potentials output by each approximate calculation unit to obtain the membrane potentials corresponding to the physical neurons and the accessed binarized images.

[0125] The pulse firing decision unit is used to compare the membrane potential summarized by the approximate addition tree with the activation threshold to determine whether to activate the current physical neuron; if the current physical neuron is not activated, the membrane potential of the current physical neuron is decayed according to the preset neuron model; if the current physical neuron is activated, a new pulse is fired to the next layer of neurons, and after the physical neuron is activated and a pulse is fired, the membrane potential of the current neuron is reset according to the preset neuron model.

[0126] During inference, the controller 200 in the pulse processing core controls the operation of the entire inference subsystem, managing and coordinating the operation of various internal devices. It receives time step information from the neuron timing generator 100 and feedback information from other modules, ensuring correct timing and functional control of the entire inference process. The synaptic core 300 stores the synaptic weights of each physical neuron connected to it via its built-in memory 301, and receives pulse signals from the input layer or the previous layer (hidden layer for a three-layer SNN). During the inference phase, the synaptic core 300 transmits the synaptic weights corresponding to each physical neuron to the neuron computing core 400 for inference computation via the first arbitrator 302. The neuron computing core 400 contains a pipeline neuron sequence 401 composed of multiple physical neurons (NEs), and stores parameters such as membrane potential, activation threshold, and activation state of each physical neuron. These parameters can be obtained in advance through offline training and pre-stored in its internal neuron storage space 403 before online training. Each physical neuron (NE) in the neuronal computational core 400 includes an approximate computational array (i.e., a PE array), an approximate addition tree, and a neuronal pulse firing unit, simulating the membrane potential changes of biological neurons. Within one neuronal time step, the membrane potential of the neuron is calculated using the approximate computational array and the approximate addition tree. At each time step, the membrane potential is sent to the neuronal pulse firing unit. The second arbitrator 402 compares the membrane potential with a preset neuronal model (e.g., an optimized IF or LIF model) and, together with the pulse firing decision unit, determines whether the current physical neuron should fire a pulse, and stores the reset or leaked neuronal membrane potential.

[0127] In this embodiment of the invention, the multiple physical neurons (NEs) built into the neuron computing core 400 form a pipeline structure, sequentially transmitting the pulse sequence of the input binarized image; and each physical neuron employs a time-division multiplexing method, using multiple built-in approximate computing units (ACUs). Each clock cycle, multiple input pulses are allocated to each ACU for parallel computation, accumulating the local membrane potential of the current physical neuron according to the neuron model. For example... Figure 5 As shown, multiple approximate computational units (ACUs) form a one-dimensional PE array with low resource consumption, which can significantly reduce circuit area and power consumption. Then, through time-division multiplexing, the pulse sequence of the input image is input to the physical neuron in multiple batches according to the clock cycle for parallel superposition, thus achieving good computational efficiency. Specifically, the pulse sequence corresponding to a row or column (of M pixels) can be input at a time. Therefore, the PE array of the physical neuron is composed of M ACUs in parallel. By multiplexing N times, all pulse signals of the input image with an M×N scale can be sent to the physical neuron for membrane potential calculation. Therefore, with certain instruction control, input images of various scales can be processed under limited hardware resources.

[0128] In the pulse processing core, the adder is the approximate computation unit of the PE array and the core component of the approximate addition tree. To obtain a hardware-friendly, low-power, fast neuronal circuit that simulates the operating mechanism of biological neurons, an approximate computation unit (ACU) is designed to calculate the membrane potential of physical neurons. The core circuit of the ACU and each adder constituting the approximate addition tree are approximate adders.

[0129] In a preferred embodiment, the approximate adder is a speculative carry adder with error correction. The current mainstream adder is the Ripple Carry Adder (RCA), but a characteristic of the RCA is that subsequent adders depend on the carry signal of the preceding stage. When all carry signals in this critical path are 1, the delay of the critical path becomes very large. A longer critical path increases the overall computation time of the processor, i.e., reduces computational efficiency. The computational principle of RCA can be expressed mathematically as follows:

[0130] s i =a i ⊕b i ⊕c i

[0131] c i+1 =a i b i +c i (a i +b i )

[0132] p i =a i +b i

[0133] g i =a i b i

[0134] Among them, a i and b i It is the input operand of the i-th bit, s i Input the sum of the outputs of the i-th bit, c i It is the carry signal of the i-th bit, p i It is a carry propagation signal, g i It is a carry-generating signal.

[0135] Therefore, this invention proposes an approximate adder that reduces the carry propagation chain length. It employs a carry prediction strategy to truncate the carry chain, effectively reducing critical path delay while minimizing the adder's accuracy loss. Specifically, for two input signals a and b with a bit width of n to be added, signals a and b can be divided into m segments, each segment consisting of k bits, i.e., n = m * k.

[0136] Assuming that the symbol i represents the sequence number of each sub-addition block, this embodiment assigns m segments of k-bit sub-signals to i propagation carry generators, where k is the sub-signal bit width of the local membrane potential; and for any 1≤i≤m-1, the predicted carry signal of the propagation carry generator in the i-th sub-addition block... The generated signal is set to the most significant bit of block i-1, i.e. Among them, the carry signal of carry generator 0 is maintained as Furthermore, this embodiment stipulates that for any 1≤i≤m-1, The carry signal, which represents a prediction, can be represented by using... Replace the actual carry signal c at each level i ,get:

[0137]

[0138] Where i represents the current sub-addition block number, j represents the bit number within the sub-addition block, and k represents the bit width of each sub-addition block. This represents the generated signal of the (k-1)th bit in sub-adder block i. This represents the propagation signal of the j-th bit in sub-adder block i. This represents the approximate carry signal of the i-th sub-adder block.

[0139] From the above definitions, this embodiment yields two conclusions:

[0140] Conclusion 1: If the predicted carry signal generated by the carry signal propagated by the i-th carry generator is 1, then the actual carry signal generated by the i-th carry generator must be 1. The reason is: according to the definition of a signal and the generation principle of the carry signal in an RCA adder, the actual carry signal... Expanding this formula, we get:

[0141]

[0142] in, Equal to the predicted carry signal If it equals 1, then It must be 1.

[0143] Conclusion 2: Assumption If P pi =0, meaning the result of a logical AND operation on the propagation signal generated by each bit in the sub-adder block is 0. Therefore, the predicted carry output must equal the actual carry output. The reason is: P pi =0 indicates that there is no carry propagation chain from the carry input of the i-th carry generator to its carry output. Therefore, the carry output does not depend on the carry input, and thus depends only on the locally generated carry. Thus, the predicted carry output must be 0, and the actual carry output must also be 0.

[0144] However, due to practical circumstances, P may exist. pi In the case where the carry signal is 1, the actual carry signal might be 1 when the carry signal is predicted to be 0. This would result in an error of the order 2i, causing irreparable damage to the entire neural network inference or training process. Therefore, to reduce this error, this invention proposes an error correction mechanism: a "two-to-one" multiplexer is inserted only between sub-addition blocks of 1 ≤ i ≤ m-1. The two input signals of the multiplexer are the generation signal of the previous addition block. and the predicted carry signal generated by the previous adder block The selected signal is the transmission signal P. pi Because of P pi The carry has already been generated in the carry generator of each addition block, so no additional circuitry is needed. This embodiment defines the circuit function as follows: if P... pi =1, the output selection of the multiplexer is Otherwise choose The output signal serves as the carry input signal for the sub-adder of the current adder block. As can be seen, this modification does not significantly increase the area of ​​the original adder, but it effectively prevents excessive errors caused by carry mistakes.

[0145] Furthermore, in signed number addition, an error in the sign bit can lead to a very large calculation deviation. While approximate adders allow for some loss of precision, the loss of the sign bit is an unacceptable error. In this invention, by transmitting signal P... pi and The result of the AND operation is used as the symbol error correction signal S. pi If there is an S at any level pi If the signal is 1, the symbol correction circuit is triggered to determine whether to select an approximate carry signal. As the final carry signal, it corrects the final sign to prevent irreversible major errors.

[0146] Next, the relative error of the approximate adder will be listed to prove its reliability, and the relative error (E) between the approximate sum and the correct sum will be shown. re The formula is as follows:

[0147]

[0148] Where S is the result of the exact adder, S apx It is the result of an approximate adder, SG i It is the result of each stage of precise adder, SG apx,i It is the result of each stage of the approximate adder.

[0149] Regarding the maximum error, according to the carry generation signal principle above, the maximum error is caused by the failure of the (m-1)th carry signal prediction. Therefore:

[0150]

[0151] Combining the two formulas above, we can see that the maximum relative error is... In this invention, k is greater than or equal to 3. Due to the robustness of neural networks, this error has almost no impact on the pulse firing of neurons.

[0152] The approximate adder with error correction mechanism designed in this invention can reduce the delay of the critical path, thereby increasing the maximum operating frequency of the processor. At the same time, the introduction of the idea of ​​approximate calculation can reduce the computational complexity and reduce the overall power consumption of the processor. Finally, the introduction of error correction mechanism improves the accuracy of the accumulation result, prevents system crashes caused by approximate calculation, and ensures the robustness of the spiking neural network based on approximate calculation. Experimental results show that the use of this approximate adder has almost no impact on the recognition accuracy of the entire inference and training process of the spiking neural network.

[0153] In this embodiment of the invention, when the neuromorphic processor performs real-time target recognition on the input image using the inference subsystem, each physical neuron needs to utilize its internally stored model parameters, such as synaptic weights and activation thresholds, to function properly. Before online learning or training, these model parameters, including synaptic weights and activation thresholds, need to be obtained in advance through an offline training process. Typically, during offline training, synaptic weights and activation thresholds are obtained on an external computing platform using a large amount of labeled datasets, and optimization algorithms such as gradient descent and backpropagation are used to iteratively adjust the synaptic weights. After training, the optimized synaptic weights need to undergo quantization and fixed-point processing before being deployed to the neuromorphic processor implemented based on digital circuits for use in the inference phase.

[0154] In this embodiment of the invention, the neuromorphic processor further includes a training subsystem. This subsystem can access encoded image pulse sequences and use the training subsystem to update the synaptic weights and activation thresholds stored in each physical neuron in real time. This allows the neuromorphic processor to be adapted to different scenarios in real-world environments, enhancing the model's adaptability and accuracy in practical applications.

[0155] Specifically, such as Figure 5 As shown, the training subsystem includes: a controller 200, a neuron comparator 500, an update arbitrator 400, a random number generator 700, and a parameter updater 600. Figure 2 and Figure 3 As shown, in the pulse processing core, the controller 200, together with the neuron comparator, update arbitrator, random number generator, and parameter updater, realizes the online learning function.

[0156] The controller 200 is used to control the duration of the input pulse sequence received by the neuron, and to control the correct timing and functional operation of the training subsystem.

[0157] The neuron comparator 500 is used to compare the activation states of different physical neurons and select the most active physical neuron based on the pulse firing rate.

[0158] Preferably, such as Figure 6 As shown, the neuron comparator 500 employs a competitive learning strategy to select the most active neuron. Specifically, the neuron comparator 500 selects the most active physical neuron based on the pulse firing rate, as follows:

[0159] Step S101: Perform a weighted summation of each pulse signal in the input pulse sequence with the synaptic weight corresponding to the current physical neuron to obtain the cumulative membrane potential of the input pulse sequence;

[0160] Step S102: Subtract the accumulated membrane potential from the current activation threshold of the physical neuron to obtain the accumulated difference;

[0161] Step S103: Assign trigger timings to each pulse signal in the input pulse sequence in sequence; and perform a weighted summation of each pulse signal with trigger timings and the synaptic weights corresponding to the current physical neuron to obtain the time-weighted membrane potential of the input pulse sequence. Specifically, neurons requiring accumulation can be further screened before performing the weighted summation. For example, whether each pulse signal with trigger timings is greater than or equal to 1; if it is greater than or equal to 1, it is selected as a candidate neuron, and the membrane potential of each candidate neuron is weighted summated with the synaptic weights to obtain the time-weighted membrane potential.

[0162] Step S104: Use the ratio of the time-weighted membrane potential to the cumulative difference as the normalized pulse firing duration of the current physical neuron;

[0163] Step S105: Compare the normalized pulse firing duration of all physical neurons in the hidden layer one by one, and select the neuron corresponding to the minimum value as the most active physical neuron in the hidden layer.

[0164] Step S106: Compare the normalized pulse firing duration of all physical neurons in the output layer one by one, and obtain the neuron corresponding to the minimum value as the most active physical neuron in the output layer.

[0165] Combining steps S101-S106 above, the algorithm flow for updating the most active neurons in the selected hidden or output layer of the network can be illustrated as follows: Figure 7 As shown, it provides an implementation process for determining the shortest pulse time and selecting the update mechanism of the most active neuron.

[0166] First, initialize the parameter updater 600 (step S201) and input the pulse signal Z. sorted [i](Step S202), the pulse signal is an input pulse sequence with a triggering sequence (e.g., sequence 1, 2, 3, ...), and the sum of N synaptic weights ∑W connected to the current neuron is retrieved from the storage 301 of the synaptic nucleus 300. sorted [j], The first arbitrator 302 determines each pulse signal Z with the current trigger timing. sorted [i] is greater than or equal to 1; if so, the synaptic weight index of the candidate neuron is set to 1, marking the synaptic weight of that neuron as an object to be processed, and the neuron corresponding to that index is listed as a candidate update neuron (step S203). Furthermore, the cumulative sum of the synaptic weights ∑W of the i-th candidate neuron is calculated. sorted [j] and its activation threshold V thThe cumulative difference of [i] (step S204):

[0167]

[0168] Calculate the output pulse Z of the i-th candidate neuron with the triggering timing. sorted [i] multiplied by the sum of the synaptic weights of that neuron, W sorted [i], to obtain the time-weighted membrane potential C of the input pulse sequence. usum (Step S204), that is

[0169]

[0170] Traverse all input pulses and determine whether the input pulse sequence has been calculated (step S205); if not, continue the above calculation; if yes, proceed to parameter judgment step S206.

[0171] In step S206, if C usum [i] and W cs [i] are all greater than 0, so C usum [i] and W cs The ratio of [i] is used as the normalized pulse firing duration Z of the neuron. out [i](Step S207), then select the neurons in this layer that have the minimum normalized pulse firing duration Z. out The neuron of [i] is the most active neuron that needs to be updated (judged in step S208 and confirmed in step S209). If C usum [i] and W cs If [i] is not all greater than 0, then W is selected. cs [i] The largest neuron (step S210) is the most active neuron that needs to be updated (step S209).

[0172] In resource-constrained hardware implementations, employing the aforementioned competitive learning strategy to update only the most active neurons can significantly reduce computational resource consumption. This embodiment of the invention focuses on updating weights and membrane potentials based on important inputs, reducing unnecessary computational overhead and improving learning efficiency. Simultaneously, the sparse activation characteristic reduces energy consumption, contributing to improved model stability and accuracy.

[0173] The training subsystem also includes an update arbitrator 400. The update arbitrator 400 is used to receive the output of the neuron comparator 500 and send the most active physical neuron to the parameter updater 600.

[0174] The arbitrator 400 receives the results from the neuron comparator 500, determines the state of each neuron, and ultimately decides which neuron needs updating. This decision-making process considers not only the current neuron's membrane potential and synaptic weights but also its contribution to the overall network performance. Once the neuron requiring updating is identified, the arbitrator sends an update signal to the parameter updater 600 to trigger specific weight and activation threshold adjustments. Therefore, more active neurons are more likely to undergo synaptic weight updates, consistent with the fundamental characteristics of biological learning.

[0175] At the same time, such as Figure 5 As shown, the training subsystem introduces a random number generator 700. This module aims to increase the network's flexibility and versatility by introducing a degree of randomness. The random number generator 700 generates pseudo-random numbers P based on a linear feedback shift register (LFSR). The LFSR consists of a set of registers. At each clock cycle, the values ​​in the registers are shifted, and new input bits are generated based on feedback signals from certain registers. The shift register and feedback logic work together to generate a cyclic pseudo-random sequence. The accumulated difference W of the neurons mentioned above... cs Compare W with the size of the pseudo-random number P. cs If the value is greater than P, proceed to the next parameter update; otherwise, terminate the update logic.

[0176] The parameter updater 600 is used for a random online learning strategy based on historical weights, which uses the pseudo-random number and the currently stored synaptic weights of the neuron to update the synaptic weights and activation thresholds of the most active physical neuron.

[0177] In the online training process of this embodiment, similar to the inference process, the neuron timing generator is also used to generate the time step of the neuron, that is, the time length of the input pulse sequence. It can adjust the representation precision of the pulse data after encoding the input image, i.e., it determines how many frames of binary images the input image is encoded into. The pulse sequence of each frame of binary image needs to be input into the neuromorphic processor for training in a certain order, thus determining the number of training rounds in the training subsystem. Each time step executes one training process. During training, the controller controls the operation of the entire training subsystem, managing and coordinating the operation of each submodule, receiving time step information from the neuron timing generation module and feedback information from other modules, and performing correct timing and functional control of the entire training process. In the weight update phase, the synaptic nucleus 300 sends the synaptic weights to the parameter updater 600 for update calculations, and receives and stores the updated synaptic weights. During training, the neuron computation core 400 stores parameters such as neuron membrane potential, activation threshold, and activation state. Each NE in its built-in pipeline neuron sequence 401 includes an approximate computation PE array and a neuronal spiking unit. Based on the optimized LIF / IF neuron model, it incorporates an approximate computation unit (ACU) and an approximate addition tree to simulate membrane potential changes in biological neurons. Within a neuron's time step, the approximate adder in the PE array calculates a partial membrane potential (local membrane potential). The accumulated membrane potential determines the neuron's event at the current moment. When the accumulated membrane potential exceeds the neuron's threshold, a spiking event is triggered, and the membrane potential is reset to a pre-set reference potential. Otherwise, the current membrane potential is decayed and stored for the next time step. Therefore, in this embodiment, the training process of the neuromorphic processor with a multi-spiking processing core includes all modules and computational steps of the inference process. That is, during training, the training subsystem calls and controls the components of the inference subsystem to update data such as neuron membrane potential, synaptic weights, and activation thresholds, optimizing the performance of the spiking neural network.

[0178] Experiments have shown that the synaptic weight of a neuron is affected by the firing of the pre- and post-neurons connected to the synapse. Specifically, if the pre-neuron fires first and the post-neuron fires later, the synaptic weight increases; conversely, if the pre-neuron fires later and the post-neuron fires first, the synaptic weight decreases. Therefore, a synaptic plasticity mechanism can be proposed: Spike Timing Dependent Plasticity (STDP), used to implement an online training subsystem. The STDP training subsystem can be fitted using the following equation:

[0179] t in =α(1-input) β

[0180]

[0181] Among them, t in The input pulse time (t) is used to calculate the pulse time of each input neuron; input is the normalized input pixel value, ranging from [0,1], which is the pulse value (0 or 1) of the binary image obtained after encoding; α and β are constants used to adjust the time encoding. The larger the pixel input value of the original image, the longer the input pulse time (t). in The smaller the value, the earlier the input neuron fires its pulse. It is the membrane potential of the output neuron, and set C contains pulse times earlier than the current neuron's output time t. out The input neuron. W i Indicates synaptic weight, It is the time-dependent term of the input pulse, V th It is the activation threshold of a neuron. out The logarithm of the output neuron's membrane potential represents the time it takes for the output neuron to fire a pulse. ΔW represents the change in synaptic weight, which depends on the time difference Δt between the output pulse and the input pulse. If the output pulse is later than the input pulse (Δt > 0), the weight increases; if the output pulse is earlier than the input pulse (Δt ≤ 0), the weight decreases. P and A n T is the magnitude parameter of the weight change. p and T n This is the time constant. These equations collectively describe the weight update process in the STDP learning method. However, since the training subsystem described above adjusts the synaptic weights of neurons based on the time difference between the pre- and post-synaptic pulses, to obtain the changing weights ΔW in this STDP learning method, the time difference Δt needs to be accurately obtained. This requires logarithmic and exponential operations to update the synaptic weights. However, these complex mathematical calculations are difficult to implement precisely on digital circuits, and also require a large amount of storage space to store the pulse release status of each neuron at the time step, which is clearly not conducive to the rational allocation of hardware resources.

[0182] Therefore, to reduce the computational complexity of the weight update phase and to rationally allocate hardware resources, this invention proposes a simplified linear computation online learning method. Specifically, the training subsystem can employ a stochastic online learning strategy based on historical weights to update the synaptic weights and activation thresholds of each physical neuron, reducing computational complexity while improving the training and inference accuracy of the hardware-based neuromorphic processor.

[0183] In one feasible preferred embodiment, the historical weight-based random online learning strategy specifically includes:

[0184] If the difference between the current membrane potential of the physical neuron and the current activation threshold (|W) cs If |) is greater than the pseudo-random number (P), then the synaptic weights and activation thresholds of the current physical neuron are updated according to the following mathematical model:

[0185]

[0186] Where W(t) represents the updated synaptic weights, W(t-1) represents the original synaptic weights, and V th (t) represents the updated activation threshold, V th (t-1) represents the activation threshold before the update, Δt represents the time difference between the release of pulses by the preneuron and the postneuron, a and b represent the two different weight update magnitudes, and c represents the update magnitude of the activation threshold.

[0187] Otherwise (i.e., |W) cs If |≤P), the synaptic weights and activation thresholds of the physical neuron remain unchanged at the current moment.

[0188] Here, Δt represents only the time difference between the release of pulses by the preceding and following neurons; that is, if the following neuron releases its pulse before the preceding neuron, then Δt is greater than 0, otherwise it is considered less than 0. Compared to the traditional STDP algorithm, this embodiment of the invention no longer needs to store a large amount of historical parameter information, reducing excessive storage space requirements. a and b are the update magnitude parameters of the synaptic weights, and the settings of these parameters are empirical values ​​obtained through numerous experiments. In a preferred embodiment, assuming a>b, and incorporating historical synaptic weights into the current synaptic weight update process, the historical weight W(t-1) from the previous moment is preferably used. Specifically, when Δt>0 and W(t-1)≤0, the weight is increased by a larger value a; when Δt>0 and W(t-1)>0, the weight is increased by a smaller value b. If Δt≤0 and W(t-1)<0, the weight is decreased by a smaller value b, otherwise it is decreased by a larger value a. This invention considers how to optimize the expression of time difference and how the weights themselves determine the plasticity of synaptic weights, and uses two parameters, a and b, to reflect weight adjustments under different conditions. Specifically, a can be set to 2 and b to 1. Similarly, the activation threshold can be set empirically through extensive experimentation. In this embodiment, the activation threshold V is preferably set... thThe update magnitude c of (t) is set to be the same as the update magnitude a of the synaptic weights. Generally, the update magnitudes of the activation threshold and synaptic weights need to be set to the same value to ensure the proper functioning of the physical neuron model. For example, when a is set to 2, c is also set to 2.

[0189] In biological neural systems, the updating of synaptic weights is not a deterministic process but is influenced by many factors (such as neuronal activity, voltage changes, and neurotransmitter release), exhibiting a high degree of randomness and probability. Introducing probability to determine whether to update synaptic weights can better simulate this characteristic of biological learning. Simultaneously, this approach effectively avoids network overfitting caused by frequent updates. Overfitting typically leads to networks performing well on training data but lacking generalization ability in practical applications. In neural networks, the updates of each neuron and synapse are independent. By setting update probabilities, the network can form diverse synaptic connections, which helps to cover the input space more broadly and improve the predictive ability for unknown data.

[0190] Furthermore, the neuromorphic processor in this embodiment of the invention also includes a communication subsystem. For example... Figure 1 and Figure 4 As shown, in a preferred embodiment, the communication subsystem is a three-level routing system, including: a level 0 router (L0 router), a level 1 router (L1 router), and a level 2 router (L2 router).

[0191] The Level 0 router (L0 router) is located inside each pulse processing core. It transmits the encapsulation signal from the Level 1 router to the corresponding pulse processing core, and re-encapsulates the calculation result from the pulse processing core into a data packet before sending it to the Level 1 router. For example... Figure 5 As shown, the L0 route includes a scheduler L01, a packet encoding module L02, a packet decoding module L03, a data buffer (FIFO1) L04 for encoding, and a data buffer (FIFO2) L05 for decoding.

[0192] The Level 1 router (L1 router) is used to collect and encapsulate the data from the Level 0 router according to a preset communication protocol, so as to realize the communication transmission of data between each pulse processing core.

[0193] The secondary router (L2 router) is used to collect the output data of the primary router according to a preset communication protocol, so as to realize data communication between multiple neuromorphic processors composed of pulse processing core clusters, or data communication between the neuromorphic processor and external circuits.

[0194] in, Figure 4The communication routing characteristics of a neuromorphic processor with a multi-pulse processing core are demonstrated.

[0195] In practical implementation, the secondary router can exchange data between the processor and external systems through interface modules in several directions. Specifically, the secondary router (L2 router) transmits data with the outside world through the local interface (LOCAL) and the external interface (EXT.I / F), ensuring the efficiency and real-time performance of data transmission for a single neuromorphic processor. It can also combine multi-core neuromorphic processors into arrays through the four directional interfaces (EAST, SOUTH, WEST, and NORTH) to construct neuromorphic processors with a larger computational scale.

[0196] The three-level on-chip routing is used to transmit pulse data packets after preprocessing the input image data to obtain a pulse sequence, which is then transmitted to the pulse processing core through the three-level routing structure for data preparation during the inference stage. Figure 8 It provides an encapsulation format for data packets distributed at various levels of routing. For example... Figure 8 As shown, the contents of a pulse data packet include flow control units (Flits) with different transmission information: routing path, chip selection (signal), (input) pulse sequence, neuron type, image dimension, number of neurons, and synaptic weights. The purpose of decomposing a package into multiple Flits is to better control the transmission of smaller Flits between routes and prevent route congestion. Each Flit records the aforementioned different transmission information.

[0197] Level 2 (L2) routers: L2 routers handle the highest-level on-chip connectivity and have five different parallel links leading to the east, west, south, north, and local directions. For L2 routing, pulse data is sent to the local route or to one of the other four L2 routes based on the routing path of the pulse packet. L2 routing is controlled by a round-robin arbitrator, which cycles through communication in each link direction. When a path in one direction is granted permission, its next permission time is at most the time required to traverse the other four paths, ensuring the maximum latency required to process packets.

[0198] Level 1 Router (L1): L1 routing preferably uses a star topology on-chip routing, which determines the number of pulse processing cores used, allowing for one to four hidden-layer pulse processing cores to process input pulses in parallel. The output-layer pulse processing core only sends data to the L1 router for calculation and output after the aforementioned four hidden-layer pulse processing cores have completed their calculations. In L1 routing, for pulse packets (Packages) from L2 routers, the pulse packets are re-encapsulated into... Figure 8 The flow control units (Flits) shown, which contain different transmission information, wait for the on-chip routing path calculation module to obtain the transmission path based on the chip selection signal through the input buffer. Then, through the polling arbitration module, the pulse processing core to which each Flit should flow is determined based on the input chip selection signal. For example, the input chip selection signal, after passing through the L1 routing calculation path, determines that the pulse data packet is sent to one of the hidden layer pulse processing cores 1, 2, 3, or 4. The four cores receive pulse sequences at different time steps of the same image after Poisson coding, process all pulse sequences in parallel, and after the four cores have finished processing, send the hidden layer pulses to the output layer pulse processing core for the calculation of output layer neurons.

[0199] Level 0 Router (L0 Router): The L0 router is the lowest-level router within the pulse processing core. For encapsulated signals from the L1 router, the Flits are sent to the computing core for processing according to the scheduler's control. For the local calculation results, an encoder packages each Flit into a pulse data packet, and then uses a FIFO to temporarily store it, waiting for the control signal to be sent to the next-level L1 router.

[0200] After transmission through three levels of routing, the data participating in the inference or training process is routed through L0 routing. Under the control of the scheduler, Flits are sent to the physical neurons for inference computation or training learning. Figure 1 In the diagram, white neurons represent virtual neurons, which are only used to receive input pulse sequences and do not actually perform calculations; black neurons represent neurons in the hidden layer or output layer, which have physical circuitry to implement the neuron model and determine the generation of pulses.

[0201] In a preferred embodiment, the neuromorphic processor provided by the present invention implements the following inference process for target recognition of an input image based on the above-described three-level on-chip routing:

[0202] (1) Multi-size image processing and network construction: Based on the image dimension signal in the Flits of the pulse data packet, the ratio M*N of the input image can be determined (e.g., if M is 14 and N is less than or equal to 28, then an input image of 14*14 pixels or 14*28 pixels is obtained). Simultaneously, this signal also determines the number of virtual neurons, that is, the number of virtual neurons in the input layer used to receive the input pulse sequence. For input images of different sizes, it can be ensured that the image is not distorted. Specifically, M virtual neurons can be used to simultaneously receive pulses corresponding to a row of pixels, and the entire frame image can be accessed in batches (N times); N virtual neurons can also be used to simultaneously receive pulses corresponding to a row of pixels, and the entire frame image can be accessed in batches (M times); or, when the input image size is small, M×N virtual neurons can be used to access all pixels of the entire frame image simultaneously. The neuron count signal encapsulated in the pulse data packet determines the number of physical neurons in the hidden layer, satisfying the construction requirements of different sizes, such as lightweight or large neural networks.

[0203] (2) Data preparation for synaptic nucleus 300 and neuron computing core 400: Based on the synaptic weights and input pulse sequence in the Flits of the pulse data packet, synaptic nucleus 300 and neuron computing core 400 respectively receive and store the corresponding synaptic weights and neuron initial states for further inference calculation.

[0204] (3) Inference computation in the approximate computation array of hidden layer physical neurons: After determining the input image size and the number of neurons, according to the data structure required by the approximate computation array, the neuron computation kernel 400 has received the input pulse sequence from the L0 source and retrieved the corresponding synaptic weights from the synaptic kernel 300, and calculated the neuron's membrane potential in the PE array in the NE. When a neuron's time step is completed, the accumulated membrane potential at the current time is sent to the neuron pulse firing decision unit.

[0205] (4) The neuron pulse firing decision unit determines the neuron's pulse event: When the neuron pulse firing decision unit obtains the neuron membrane potential of the approximate calculation array output, it will determine the neuron's event state at the current moment according to the aforementioned neuron model.

[0206] (5) On-chip three-level routing summarizes and transmits hidden layer neuron pulses: After the neuron time step ends, the inference phase for all neuron time steps is performed. In the last neuron step, the on-chip three-level routing summarizes the pulse sequences of all output neurons within that neuron time step. This result has two transmission directions: ① Pulse processing kernel (pulse processing kernel 0) where the output layer neurons are located: If the pulse summarization of all hidden layer neurons has been completed, the output pulses of the hidden layer are transmitted to the next output layer through L1 routing to continue the inference phase. The inference process is the same as described above. ② Pulse processing kernel (pulse processing kernels 1, 2, 3, 4) where the next hidden layer neurons are located: If there are still next layer hidden layer neurons (multiple hidden layers) that have not been calculated, the output pulses of that hidden layer are transmitted to the next hidden layer through L1 routing to continue the inference phase. The inference process is the same as described above. After all hidden layer neurons have been calculated, they will be sent to the pulse processing kernel where the output layer physical neurons are located for output layer pulse calculation.

[0207] (6) Recognition and reasoning results: If all hidden layer neurons have been calculated, without on-chip training, the encapsulated pulse data packets will be processed by the physical neurons of the output layer and then processed by three levels of on-chip routing. The L2 routing will output the final recognition result, thus completing the entire reasoning process for the input image.

[0208] Figure 9 A schematic diagram of an implementable structure for a level 2 router in an on-chip three-level router is provided. The structure and implementation principles of the level 1 and level 0 routers are similar to those of the level 2 router.

[0209] like Figure 9 As shown, the L2 router is internally divided into three pipelines: Phase 1 (path calculation), Phase 2 (switching), and Phase 3 (transmission). Each phase is assigned different tasks by the scheduler.

[0210] Stage 1: Path Calculation

[0211] During this phase, the router receives encapsulated data packets from the input buffer. The data packet encapsulation format is as follows: Figure 8 As shown, the data packet contains key information such as path information and input data. The packet is broken down into multiple fragments, each containing key information such as path information and input data. The routing calculation module parses this information to determine the next transmission direction of the data packet. The calculation result (i.e., the transmission direction) is stored in the RC register for use in subsequent stages.

[0212] Stage 2: Switching

[0213] In the second stage, the path information in the RC register is transmitted to the switching module, which is responsible for matching the output channel of the data packet with the path information and generating a corresponding path permission signal. This signal is then stored in the SW register, preparing for the next step of data transmission.

[0214] Stage 3: Transmission

[0215] In the final stage, based on the arbitration result of the path grant signal, the data packet is transmitted to the designated output port (South, North, East, West, or local) via a crossbar. Finally, the data packet is sent to the next router node through the output buffer, completing the data packet forwarding task.

[0216] This three-stage pipeline architecture significantly improves the router's throughput and packet forwarding efficiency, ensuring that packets can be transmitted quickly and efficiently in the network.

[0217] The L2 routing connects the various routing nodes of the neuromorphic processors. Data can be routed through arbitration to specific paths, including east, south, west, north, and local directions, enabling the combination of multiple neuromorphic processor arrays. The L1 routing connects the five pulse processing cores, facilitating data flow between the internal pulse processing cores and the external top-level processor.

[0218] Figure 10 This invention presents a multi-pulse processing core system built using a three-level on-chip routing architecture, as an embodiment of the present invention. A representative structure of a multi-core system built using a three-level on-chip routing architecture is as follows: Figure 10 As shown, the top layer uses a mesh structure composed of L2 routes, connecting various L2 route nodes. Through an appropriate arbitration mechanism, data packets can flow along the east, west, south, north, and local directions. The local direction is connected to L1 routes, while the other directions are connected to L2 routes of other nodes. In the L1 routing layer, the L0 routes of the five pulse processing cores are connected, replacing the route nodes in the east, west, south, north, and local directions respectively. The transmission directions are pulse processing core 0 (output layer pulse processing core), 1 (hidden layer pulse processing core), 2 (hidden layer pulse processing core), 3 (hidden layer pulse processing core), and 4 (hidden layer pulse processing core). The five pulse processing cores transmit pulse data packets through communication between L1 and L0 routes, forming a star topology on-chip routing system. In the bottom L0 routes, pulse data packets are decoded into corresponding input signals and sent to the pulse processing cores for processing. After processing, the output signals are re-encoded into pulse data packets and used for data communication between different processing cores through L1 routes.

[0219] In summary, the embodiments of this invention achieve higher computational speed and accuracy while ensuring efficient network transmission. The improvements primarily involve three aspects: optimization of the neuron approximation kernel, optimization of the online learning method, and optimization of the on-chip routing design. Firstly, in the SNN processor, the adder is a key component for performing neuron membrane potential accumulation and weight updates. To address the impact of the large area and high latency of the carry-lookahead adder on the performance of the SNN system, a novel approximation computation method—a high-precision approximation adder design with an error correction module—is proposed. This novel adder design not only reduces the adder area and increases the operating frequency but also improves the overall performance of the processor. Simultaneously, to further reduce energy consumption, a shutdown mechanism is implemented for idle neurons to optimize energy use while ensuring processing efficiency. Secondly, the traditional online learning method of Temporal Synaptic Plasticity (STDP) is improved by proposing an improved stochastic STDP learning method based on historical weights (Weighted-STDP, or W-STDP), which improves training accuracy while reducing storage space usage and shrinking the area of ​​the weight update-related logic circuitry. Third, a hierarchical routing strategy and a multi-directional data transmission strategy were adopted, and combined with a flexible SNN core connection design, on-chip routing was optimized to achieve efficient data processing and transmission.

[0220] Furthermore, to demonstrate the performance improvements in recognition accuracy and computational efficiency of the neuromorphic processor provided by this invention, this embodiment presents a neuromorphic processor based on a 40-nanometer (nm) CMOS process, with parameters as shown in Table 1. Its frequency, power consumption, and area are evaluated in detail. The training and inference accuracy of the neuromorphic processor provided by this invention are further verified on the MNIST handwritten digit dataset (which includes images of ten categories of handwritten digits from 0 to 9, containing 70,000 images, of which 60,000 are training images and 10,000 are test images. This embodiment uses these two types of images as the training and test sets, respectively).

[0221] Table 1: Parameters of the neuromorphic processor proposed in this invention

[0222]

[0223]

[0224] As shown in Table 1, the neuromorphic processor proposed in this embodiment is implemented based on 40nm digital technology, integrating 330 neurons and 128,640 synapses. It supports online learning, employs a randomized and simplified STDP algorithm, and has 4-bit weights. The processor occupies an area of ​​1.01 mm². 2It operates at a voltage of 0.8V, has a maximum frequency of 333MHz, and a dynamic power consumption of 75.6μW / MHz.

[0225] As shown in Table 2, the experimental results indicate that, using a 40nm CMOS process, the highest operating frequency of this neuromorphic processor is 333MHz, and its area is 1.01mm². 2 The total power consumption is 29.9mW, and the dynamic power consumption is 25.2mW. On the MNIST dataset, after on-chip training, the inference accuracy reaches 95%, higher than the 89% accuracy achieved by offline training on the same dataset with the same network architecture. Compared with other processors with similar functions, the neuromorphic processor in this invention has advantages in area, power consumption, and recognition accuracy.

[0226] Table 2: Comparison with other previous neuromorphic processors with online functionality

[0227]

[0228] Table 2 shows a comparison of this embodiment with other online learning neuromorphic processors. In comparison, the processor in this embodiment has a larger number of neurons (330) at the same technology node, and achieves a classification accuracy of 95% on the MNIST dataset, higher than most of the other compared processors. Furthermore, this processor achieves a resolution of 1.01 mm... 2 This processor achieves high learning capacity and power efficiency within a normalized area, demonstrating superior performance. Although the processor in this embodiment uses a 4-bit synaptic width, while other processors employ synaptic widths ranging from 1 to 9 bits, the processor in this embodiment still achieves a good balance between power consumption and accuracy. For example, compared to the 65nm processor in TBCAS2019, the processor in this embodiment achieves higher accuracy on the MNIST dataset, while its dynamic power consumption is 75.6 μW / MHz, significantly lower than some processors using larger bit widths (such as TCAS2022, which uses a 9-bit synapse processor with 311.3 μW / MHz).

[0229] The neuromorphic processor in this embodiment, through rational design and optimization, exhibits significant advantages in terms of neuron count, processing accuracy, power efficiency, and area utilization. This not only makes it superior in performance to existing processors of the same type but also achieves a good balance between power consumption and integration, providing strong support for future neuromorphic computing applications.

[0230] This embodiment proposes a processor design system capable of dynamically updating and efficiently processing complex tasks by combining a bio-inspired computational model and hardware design. It presents a low-power, high-precision, online-learning processor based on a spiking neural network, capable of efficiently simulating the complex computational functions of a biological nervous system. This design system not only significantly improves computational speed and energy efficiency but also reduces the hardware resource consumption of the processor design. This system is applicable to various industries requiring neural network computation, such as medical image processing, autonomous driving, intelligent monitoring systems, and smart transportation, thereby addressing the problems existing in the prior art.

[0231] Neuromorphic processors are currently widely used in the field of intelligent computing. This embodiment provides a neuromorphic processor microarchitecture based on online learning and approximate computation, which improves the processor's energy efficiency and response speed while ensuring computational accuracy. This embodiment mainly focuses on two technical issues: first, how to effectively reduce the hardware resource overhead and energy consumption of the neuromorphic processor, thereby improving the processor's overall computational efficiency and meeting real-time processing requirements; second, how to fully utilize online learning mechanisms to improve the processor's adaptability to dynamic tasks and processing accuracy while reducing resource overhead. Ultimately, by combining bio-inspired computational models and hardware design, it provides a highly efficient and flexible neuromorphic processor architecture that can dynamically update and efficiently process complex tasks in practical applications.

[0232] The embodiments described above are merely preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Various modifications and improvements made to the technical solutions of the present invention by those skilled in the art without departing from the spirit of the present invention should fall within the protection scope defined by the claims of the present invention.

Claims

1. An online-learning neuromorphic processor based on approximate computation, characterized in that, include: The system comprises an inference subsystem, a training subsystem, and a communication subsystem. The inference subsystem includes an input layer, a hidden layer, and an output layer. The hidden layer includes multiple pulse processing cores that process in parallel, and the output layer includes at least one pulse processing core. Each pulse processing core includes multiple physical neurons built using a pre-defined neuron model; Each physical neuron includes: a PE array composed of multiple approximate computation units, an approximate addition tree, and a pulse firing decision unit; the approximate computation unit has a built-in accumulation control logic circuit and at least one approximate adder; the approximate addition tree is composed of multiple approximate adders added in pairs in a hierarchical manner; The PE array is used to receive local pulse sequences of the binarized image in batches and distribute each pulse of the local pulse sequence to the corresponding approximate calculation unit for independent parallel summation; and by time-division multiplexing the multiple approximate calculation units, the cumulative calculation of multiple local pulse sequences of the binarized image is performed in batches to obtain the membrane potential increment accumulated by each approximate calculation unit. Each of the approximate calculation units is also used to update the local membrane potential of the physical neuron distributed in the current approximate calculation unit at the current time using the membrane potential increment accumulated at each batch time according to the preset neuron model. The approximate addition tree is used to sum the local membrane potentials output by each approximate calculation unit to obtain the membrane potentials corresponding to the physical neurons and the accessed binarized images. The pulse firing decision unit is used to compare the membrane potential summarized by the approximate addition tree with the activation threshold to determine whether to activate the current physical neuron; if the current physical neuron is not activated, the membrane potential of the current physical neuron is decayed according to the preset neuron model; if the current physical neuron is activated, a new pulse is fired to the next layer of neurons, and after the physical neuron is activated and a pulse is fired, the membrane potential of the current neuron is reset according to the preset neuron model. The inference subsystem is used to perform approximate calculations on the multi-scale input image after encoding and input to the input layer based on the pre-stored synaptic weights and activation thresholds, through the pulse processing kernels in the hidden layer and the output layer, to statistically analyze the calculation results of multiple time steps within a time window, and generate the recognition result of the multi-scale input image. The training subsystem is used to access multiple images from the input layer to the hidden layer and the output layer, and to update the synaptic weights and the activation threshold using a random online learning method based on historical weights. The training subsystem includes: a controller, a neuron comparator, an update arbitrator, a random number generator, and a parameter updater; The controller is used to control the duration of the input pulse sequence received by the neuron, and to control the correct timing and functional operation of the training subsystem. The neuron comparator is used to compare the activation states of different physical neurons and select the most active physical neuron based on the pulse firing rate. The update arbitrator is used to receive the output of the neuron comparator and send the most active physical neuron to the parameter updater. The random number generator is used to generate pseudo-random numbers based on a linear feedback shift register and by using shift operations. The parameter updater is used for a random online learning strategy based on historical weights, using the pseudo-random number and the currently stored synaptic weights of the neuron to update the synaptic weights and activation thresholds of the most active physical neuron. The neuron comparator selects the most active physical neuron based on the pulse firing rate, specifically: The cumulative membrane potential of the input pulse sequence is obtained by performing a weighted summation of each pulse signal in the input pulse sequence with the synaptic weight corresponding to the current physical neuron. The cumulative membrane potential is subtracted from the activation threshold of the current physical neuron to obtain the cumulative difference. The trigger timing is assigned to each pulse signal in the input pulse sequence in sequence; and the pulse signals with trigger timing are weighted and summed with the synaptic weights corresponding to the current physical neuron to obtain the time-weighted membrane potential of the input pulse sequence. The ratio of the time-weighted membrane potential to the cumulative difference is used as the normalized pulse firing duration of the current physical neuron; The normalized pulse firing duration of all physical neurons in the hidden layer is compared one by one, and the neuron corresponding to the minimum value is selected as the most active physical neuron in the hidden layer. The normalized pulse firing duration of all physical neurons in the output layer is compared one by one, and the neuron corresponding to the minimum value is the most active physical neuron in the output layer. The inference subsystem is also used to update the recognition results of the multi-scale input image by performing approximate calculations through the pulse processing kernels in the hidden layer and the output layer based on the updated synaptic weights and activation thresholds after training. The communication subsystem is used to perform multi-level routing control on the data transmission between the inference subsystem and the training subsystem through a hierarchical routing architecture.

2. The online learnable neuromorphic processor based on approximate computation according to claim 1, characterized in that, The input layer includes multiple virtual neurons, the number of which matches the scale of the input image, and is used to access the pulse sequence of the binarized image after rate encoding of the input image; Both the hidden layer and the output layer have built-in synaptic kernels and neuron computation kernels in their pulse processing kernels; the synaptic kernels pre-store synaptic weights obtained through pre-training; the neuron computation kernels pre-store activation thresholds obtained through pre-training; the neuron computation kernels have built-in multiple physical neurons; the multiple physical neurons form a pipeline structure to sequentially pass the pulse sequence of the input binarized image.

3. The online learnable neuromorphic processor based on approximate computation according to claim 1, characterized in that, The neuron model includes a neuron charging model, and the mathematical model of the neuron charging model is as follows: ， or ， or ， Where V(t) is the membrane potential of the neuron at the current moment, V(t-1) is the membrane potential of the neuron at the previous moment, and X(t) is the membrane potential increment caused by the input pulse at the current moment. This is a preset membrane potential attenuation factor; This is the reset reference potential for neurons.

4. The online learnable neuromorphic processor based on approximate computation according to claim 1, characterized in that, The neuron model includes a neuron reset model: ， or ， Wherein, the V(t) + V(t) represents the neuron's post-reset membrane potential at the current moment. - V represents the neuron's reset presynaptic membrane potential at the current moment; rst This is the preset reset reference potential; V is the preset membrane potential attenuation factor; th This represents the activation threshold of the current neuron.

5. The online learnable neuromorphic processor based on approximate computation according to claim 1, characterized in that, The aforementioned random online learning strategy based on historical weights specifically includes: If the difference between the current membrane potential of the physical neuron and the current activation threshold is greater than the pseudo-random number, then the synaptic weights and activation threshold of the current physical neuron are updated according to the following mathematical model: ， ， in, This represents the updated synaptic weights. This indicates the synaptic weights before the update. This indicates the updated activation threshold. This indicates the activation threshold before the update. This represents the time difference between the release of pulses by the preneuron and the postneuron; a and b represent two different weight update magnitudes; c represents the update magnitude of the activation threshold. Otherwise, the synaptic weights and activation thresholds of the physical neuron remain unchanged at the current moment.

6. The online learnable neuromorphic processor based on approximate computation according to claim 1, characterized in that, The approximate adder is a speculative carry adder with error correction mechanism.

7. The online learnable neuromorphic processor based on approximate computation according to claim 1, characterized in that, The communication subsystem is a three-level routing system, including: a level 0 router, a level 1 router, and a level 2 router; The zero-level router is located inside each pulse processing core and is used to transmit the encapsulation signal of the first-level router to the corresponding pulse processing core, and to re-encapsulate the calculation result of the pulse processing core into a data packet and send it to the first-level router. The first-level router is used to collect and encapsulate the data from the zero-level router according to a preset communication protocol, so as to realize the communication transmission of data between various pulse processing cores. The secondary router is used to collect the output data of the primary router according to a preset communication protocol, so as to realize data communication between multiple neuromorphic processors composed of pulse processing core clusters, or data communication between the neuromorphic processor and external circuits.

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