Display panel and display device

Abstract

The invention discloses a display panel and a display device.The side, in the longitudinal direction, of the display panel is used for arranging a driving IC, a display area and a frame area surrounding the outer side of the display area are formed on the display panel, and the frame area is provided with a first side edge used for being close to the driving IC; the display panel comprises a pixel driving circuit, a reset connecting line and two first reset signal lines, and an eighth transistor is connected to the pixel driving circuit; the reset connecting line is arranged on the first side edge and is connected with the driving IC; at least two first reset signal lines are arranged corresponding to the display area, the two first reset signal lines are arranged in a crisscross manner and are electrically connected at the intersection, in the two first reset signal lines, the transversely arranged first reset signal line is electrically connected with the drain electrode of an eighth transistor of the pixel driving circuit, and the second reset signal line is electrically connected with the drain electrode of an eighth transistor of the pixel driving circuit. One end of a first reset signal line which is longitudinally arranged extends to the first side edge and is in lap joint with the reset connecting line.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] The mainstream driving circuits on the market are 7T2C and 8T1C. Due to limitations in layout space or routing layout, in a large number of products, in actual layouts, VI signals are mostly only connected horizontally to a whole row of pixels. The source of the VI signal is from the source end (signal sending end) at the bottom of the panel to the panel pixels. When only horizontal connections are made, the VI routing must go around the periphery of the panel to connect to each row of horizontal VI signals. In the process of upward transmission, the metal routing impedance must be overcome to interfere with the transmission signal, and the Delay increases.

[0003] Application Contents

[0004] The embodiments of the present application provide a display panel and a display device, which can be implemented.

[0005] In a first aspect, an embodiment of the present application provides a display panel, wherein one side of the display panel in a longitudinal direction is used for arranging a driver IC, and a display area and a frame area surrounding the outside of the display area are formed on the display panel, and the frame area has a first side edge for being close to the driver IC;

[0006] The display panel comprises:

[0007] A pixel driving circuit, wherein an eighth transistor is connected to the pixel driving circuit;

[0008] a reset connection line, disposed on the first side and connected to the driver IC; and

[0009] At least two first reset signal lines are arranged corresponding to the display area, and the two first reset signal lines are arranged vertically and horizontally and are electrically connected at the intersection. Among the two first reset signal lines, the horizontally arranged first reset signal line is electrically connected to the drain of the eighth transistor of the pixel driving circuit, and one end of the vertically arranged first reset signal line extends to the first side and overlaps with the reset connection line.

[0010] In one embodiment, the display panel further includes:

[0011] A first power connection line is provided in the frame area and extends along the circumference of the frame area, and the first power connection line is used to electrically connect the pixel driving circuit and the driving IC; and

[0012] Two power signal lines are arranged in a vertical and horizontal cross pattern and are electrically connected at the intersection. The end of each power signal line passes through the display area and extends to the frame area to overlap with the power connection line on the corresponding side.

[0013] In one embodiment, a first wiring layer and a second wiring layer are stacked and formed on the display panel;

[0014] The power signal line arranged horizontally is arranged on the first wiring layer, the power signal line arranged vertically is arranged on the second wiring layer, and the intersection of the two power signal lines is electrically connected through a first via.

[0015] In one embodiment, a third wiring layer and a fourth wiring layer are stacked and formed on the display panel;

[0016] The first reset signal line in the transverse direction is arranged in the third wiring layer, and the first reset signal line in the longitudinal direction is arranged in the fourth wiring layer. The intersection of the two first reset signal lines is electrically connected through a second via hole.

[0017] In one embodiment, three reset connection lines are provided, and the three reset connection lines are arranged side by side and spaced apart in the longitudinal direction, so as to be respectively connected to the driving IC;

[0018] The display panel further includes:

[0019] Two second reset signal lines are arranged in a vertical and horizontal manner and are electrically connected at the intersection, the second reset signal line arranged in the horizontal direction is electrically connected to the drain of the fourth transistor of the pixel driving circuit, and one end of the second reset signal line arranged in the vertical direction extends to the first side; and

[0020] Two third reset signal lines are arranged in a vertical and horizontal manner and are electrically connected at the intersection, the third reset signal line arranged in the horizontal direction is electrically connected to the drain of the seventh transistor of the pixel driving circuit, and one end of the third reset signal line arranged in the vertical direction extends to the first side;

[0021] The ends of the first reset signal line, the second reset signal line and the third reset signal line are respectively connected to the three reset connection lines.

[0022] In one embodiment, the display panel includes a first signal line group and a second signal line group arranged in a vertical and horizontal manner, and the first signal line group and the second signal line group each include the first reset signal line, the second reset signal line and the third reset signal line arranged side by side and spaced apart.

[0023] In one embodiment, the first signal line group is arranged in the longitudinal direction;

[0024] A plurality of the first signal line groups are provided, and the plurality of the first signal line groups are arranged side by side and spaced apart in a lateral direction.

[0025] In one embodiment, the display panel further includes a second power connection line, which is disposed on the first side and is used to electrically connect the pixel driving circuit and the driving IC.

[0026] In one embodiment, the pixel driving circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, the third transistor and the fourth transistor are N-type oxide transistors, and the first transistor, the second transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are all P-type oxide transistors.

[0027] In a second aspect, the present application provides a display device, comprising the above-mentioned display panel.

[0028] Beneficial effect: The display panel provided by the present application is provided with a driver IC on one side in the longitudinal direction, and a display area and a frame area are formed on the display panel, and a side of the frame area close to the driver IC is a first side; a pixel driving circuit is provided on the display panel, and a reset connection line is provided on the first side, and the reset connection line is connected to the driver IC, and at least two first reset signal lines are arranged in a criss-cross pattern in the display area, and the first reset signal line arranged horizontally is electrically connected to the drain of the eighth transistor of the pixel driving circuit, and one end of the first reset signal line arranged vertically extends to the first side and overlaps with the reset connection line; it should be noted that the pixel driving circuit involved in the present application The circuit is set as an 8T1C driving circuit, and eight transistors and one capacitor are connected to the 8T1C driving circuit. At the same time, the two first reset signal lines are arranged in a vertical and horizontal cross pattern, and the reset connection line is arranged on the first side. The signal given by the driving IC is transmitted to the first reset signal line arranged vertically via the reset connection line, and then transmitted to the first reset signal line arranged horizontally via the intersection of the two first reset signal lines. In this way, it is no longer necessary to extend the reset connection line along the circumference of the frame area, thereby shortening the signal transmission distance and reducing the transmission delay, and then in the potential maintenance stage, the source and drain of the driving TFT can be reset more fully, thereby improving the improvement effect on low-frequency or low grayscale display. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0030] Figure 1It is the circuit connection diagram of the existing 8T1C driving circuit;

[0031] Figure 2 A schematic diagram of the wiring layout of the display panel (first embodiment) provided in this application;

[0032] Figure 3 A schematic diagram of the wiring layout of the display panel (second embodiment) provided in this application. DETAILED DESCRIPTION

[0033] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0034] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0035] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0036] In the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0037] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the various specific processes and material examples provided by the present application, but those of ordinary skill in the art can appreciate the application of other processes and / or the use of other materials.

[0038] The embodiment of the present application provides a display panel 100 and a display device, and the display device can be a smart phone, a tablet computer, a display screen, etc. The embodiment of the present application provides a display panel 100, see Figure 1 and Figure 2 , one side of the display panel 100 in the longitudinal direction is used for arranging the driver IC200, and a display area a and a frame area b surrounding the outside of the display area a are formed on the display panel 100, and the frame area b has a first side for approaching the driver IC200; the display panel 100 includes a pixel driving circuit 1, a reset connection line 2 and at least two first reset signal lines 3; the reset connection line 2 is arranged on the first side and connected to the driver IC200; the two first reset signal lines 3 are arranged corresponding to the display area a, and the two first reset signal lines 3 are arranged in a vertical and horizontal manner and are electrically connected at the intersection. Among the two first reset signal lines 3, the horizontally arranged first reset signal line 3 is electrically connected to the drain of the eighth transistor 18 of the pixel driving circuit 1, and one end of the vertically arranged first reset signal line 3 extends to the first side and overlaps with the reset connection line 2.

[0039] Please refer to Figure 1The pixel driving circuit 1 involved in the present application is set as an 8T1C driving circuit, and eight transistors and a capacitor are connected to the 8T1C driving circuit. That is to say, on the basis of the mainstream driving circuit 7T2C circuit, by setting the first reset signal line 3, the newly added eighth transistor 18 is connected to the source of the first transistor 11 (forming an 8T1C driving circuit), thereby adding a process of resetting the source and drain of the first transistor 11, alleviating the potential deviation of the first transistor 11 caused by leakage after the signal is written, and having a significant improvement effect on low-frequency flicker and crosstalk. At the same time, based on the existing 8T1C driving circuit, the reset connection line 2 is set on the first side of the frame area b close to the driving IC 200, and two first reset signal lines 3 are set in a vertical and horizontal manner. It can be understood that the reset connection line 2 can be a VI_3 (reset signal connected to the drain of the eighth transistor 18 conversion switch) connection line, and the first reset signal line 3 can be a VI_3 signal line; when the reset signal given by the driver IC200 is transmitted to the longitudinally arranged VI_3 signal line via the VI_3 connection line, it is then transmitted to the transversely arranged VI_3 signal line via the intersection of the two VI_3 signal lines that cross each other vertically and horizontally, and finally transmitted to the drain of the eighth transistor 18 via the transversely arranged VI_3 signal line; in this way, it is no longer necessary to extend the VI_3 connection line along the circumferential direction of the border area b, thereby shortening the signal transmission distance and reducing the transmission delay, and then the source and drain of the driving TFT can be reset more fully in the potential maintenance stage, thereby improving the improvement effect on low-frequency or low grayscale display.

[0040] Furthermore, in the existing display panel 100, each pixel in the display area a is provided with a VDD signal line, but a VSS signal line (a power supply signal connected to the source of the field effect transistor) is not provided. Therefore, the VSS signal line needs to be arranged around the circumference of the border area b to ensure that the VSS signal is transmitted to each pixel in the display area a. In this way, the transmission distance of the VSS signal is increased, and the longer the transmission distance, the more serious the signal distortion, which not only reduces the uniformity of the panel display, but also generates greater power consumption.

[0041] In some embodiments of the present application, the display panel 100 further includes a first power connection line 4 and two power signal lines 5; the first power connection line 4 is arranged in the frame area b and extends along the circumference of the frame area b, and the first power connection line 4 is used to electrically connect the pixel driving circuit 1 and the driving IC 200; the two power signal lines 5 are arranged in a vertical and horizontal cross-arrangement and are electrically connected at the intersection, and each end of the power signal line 5 passes through the display area a and extends to the frame area b to overlap with the power connection line on the corresponding side; it can be understood that the first power connection line 4 and the power signal line 5 are both VSS signal lines, also That is to say, a VSS signal line is arranged along a circle of the border area b and connected to the driver IC 200, and two VSS signal lines are arranged in a cross-arranged manner in the display area a. The two VSS signal lines in the display area a extend to the border area b and overlap with the VSS signal lines on the border area b, thereby forming a VSS signal transmission network on the display panel 100, thereby shortening the power signal transmission distance, reducing the transmission delay, and at the same time, reducing the transmission loss, so that the VSS potential is maintained as much as possible to avoid excessive distortion due to transmission, and at the same time reducing the panel EL power consumption (the energy loss of the panel itself caused by the power signal transmitted into the light-emitting pixels).

[0042] The present application does not impose any restriction on the specific layout form of the two power signal lines 5 that cross each other vertically and horizontally. The two power signal lines 5 can be laid out in the same routing layer or in different routing layers. In one embodiment, a first routing layer and a second routing layer are formed on the display panel 100. The power signal line 5 that is arranged horizontally is laid out in the first routing layer, and the power signal line 5 that is arranged vertically is laid out in the second routing layer. The intersection of the two power signal lines 5 is electrically connected through a first via. By arranging the two power signal lines 5 in layers, the internal routing layout of the display panel 100 is made more reasonable.

[0043] Similarly, the present application does not limit the specific layout form of the two first reset signal lines 3 that cross each other vertically and horizontally. The two first reset signal lines 3 can be arranged in the same routing layer or in different routing layers. In one embodiment, a third routing layer and a fourth routing layer that are stacked are formed on the display panel 100. The first reset signal line 3 in the horizontal direction is arranged in the third routing layer, and the first reset signal line 3 in the vertical direction is arranged in the fourth routing layer. The intersection of the two first reset signal lines 3 is electrically connected through a second via. By routing the two first reset signal lines 3 in layers, the internal routing layout of the display panel 100 is more reasonable.

[0044] In one embodiment, three reset connection lines 2 are provided, and the three reset connection lines 2 are arranged side by side and spaced apart in the longitudinal direction, so as to respectively correspond to and connect to the driving IC 200; the display panel 100 also includes two second reset signal lines 6 and two third reset signal lines 7; the two second reset signal lines 6 are arranged in a vertical and horizontal cross-arrangement and are electrically connected at the intersection, the second reset signal line 6 arranged in the horizontal direction is electrically connected to the drain of the fourth transistor 14 of the pixel driving circuit 1, and one end of the second reset signal line 6 arranged in the vertical direction extends to the first side; the two third reset signal lines 7 are arranged in a vertical and horizontal cross-arrangement and are electrically connected at the intersection, the third reset signal line 7 arranged in the horizontal direction is electrically connected to the drain of the seventh transistor 17 of the pixel driving circuit 1, and one end of the third reset signal line 7 arranged in the vertical direction extends to the first side; wherein, the first reset signal line 3, the second reset signal line 7 The ends of the signal line 6 and the third reset signal line 7 are respectively overlapped with the three reset connection lines 2; it can be understood that in the corresponding 8T1C driving circuit, the three reset connection lines 2 respectively correspond to the VI_3 connection line, the VI_Gate (the reset signal connected to the drain of the fourth transistor 14 conversion switch) connection line and the VI_ANO (the reset signal connected to the drain of the seventh transistor 17 conversion switch) connection line; the first reset signal line 3 is the VI_3 signal line, the second reset signal line 6 is the VI_Gate signal line, and the third reset signal line 7 is the VI_ANO signal line; in the display area a, two VI_3 signal lines are cross-set, two VI_Gate signal lines are cross-set, and two VI_ANO signal lines are cross-set, thereby forming a reset signal transmission network in the display area a, thereby shortening the transmission distance of the reset signal and reducing the transmission delay.

[0045] It should be noted that the display panel 100 includes a first signal line group and a second signal line group arranged in a vertical and horizontal cross pattern, and the first signal line group and the second signal line group both include the first reset signal line 3, the second reset signal line 6 and the third reset signal line 7 arranged side by side and at intervals; that is, in the horizontal direction, the first reset signal line 3, the second reset signal line 6 and the third reset signal line 7 are arranged side by side in sequence; in the vertical direction, the first reset signal line 3, the second reset signal line 6 and the third reset signal line 7 are arranged side by side in sequence.

[0046] And, in one embodiment, see Figure 3The display panel 100 also includes two power signal lines 5, which are arranged in a vertical and horizontal cross pattern and are electrically connected at the intersection. The end of each power signal line 5 passes through the display area a and extends to the frame area b, so as to overlap with the power connection line on the corresponding side; in the horizontal direction, the VI_3 signal line, the VI_Gate signal line, the VI_ANO signal line and the power signal line 5 are arranged side by side in sequence; in the vertical direction, the VI_3 signal line, the VI_Gate signal line, the VI_ANO signal line and the power signal line 5 are arranged side by side in sequence; in this way, four alternating lines are formed in the display area a; not only the transmission distance of the reset signal is shortened, and the transmission delay is reduced; but also the transmission distance of the power signal is shortened, and the transmission delay is reduced.

[0047] In one embodiment, please refer to Figure 2 The first signal line group is arranged in the longitudinal direction; there are multiple first signal line groups, and the multiple first signal line groups are arranged side by side at intervals in the transverse direction.

[0048] In some embodiments of the present application, the display panel 100 also includes a second power connection line 8, which is arranged on the first side to electrically connect the pixel driving circuit 1 and the driving IC200; it can be understood that the second power connection line 8 is a VDD signal line, and in the corresponding 8T1C driving circuit, each pixel in the display area a is evenly provided with a VDD signal line. Therefore, it is only necessary to set a VDD signal line on the first side to connect the driving IC200 and each pixel to realize signal transmission.

[0049] It can be known that the pixel driving circuit 1 is set as an 8T1C driving circuit, and the 8T1C driving circuit includes a first transistor 11, a second transistor 12, a third transistor 13, a fourth transistor 14, a fifth transistor 15, a sixth transistor 16, a seventh transistor 17, and an eighth transistor 18; the third transistor 13 and the fourth transistor 14 are N-type oxide transistors, and the first transistor 11, the second transistor 12, the fifth transistor 15, the sixth transistor 16, the seventh transistor 17 and the eighth transistor 18 are all P-type oxide transistors.

[0050] In the second aspect, the present application also provides a display device, which includes a display panel 100. It should be noted that the display panel 100 is configured as the above-mentioned display panel 100, that is, the display device has the technical features of all the embodiments of the above-mentioned display panel 100, and also has all the beneficial effects brought by all the above-mentioned technical features, which will not be repeated here one by one.

[0051] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0052] The above is a detailed introduction to a display panel provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solution and core idea of ​​the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solution to deviate from the scope of the technical solution of the embodiments of the present application.

Claims

1. A display panel, characterized in that: One side of the display panel in the longitudinal direction is used for arranging the driver IC, and a display area and a frame area surrounding the outside of the display area are formed on the display panel, and the frame area has a first side edge for being close to the driver IC; The display panel comprises: Pixel driving circuit; a reset connection line, disposed on the first side and connected to the driver IC; and At least two first reset signal lines are arranged corresponding to the display area, and the two first reset signal lines are arranged vertically and horizontally and are electrically connected at the intersection. Among the two first reset signal lines, the horizontally arranged first reset signal line is electrically connected to the drain of the eighth transistor of the pixel driving circuit, and one end of the vertically arranged first reset signal line extends to the first side and overlaps with the reset connection line.

2. The display panel according to claim 1, wherein: The display panel further includes: A first power connection line is provided in the frame area and extends along the circumference of the frame area, and the first power connection line is used to electrically connect the pixel driving circuit and the driving IC; and Two power signal lines are arranged in a vertical and horizontal cross pattern and are electrically connected at the intersection. The end of each power signal line passes through the display area and extends to the frame area to overlap with the power connection line on the corresponding side.

3. The display panel according to claim 2, wherein: The display panel is provided with a first wiring layer and a second wiring layer stacked in layers; The power signal line arranged horizontally is arranged on the first wiring layer, the power signal line arranged vertically is arranged on the second wiring layer, and the intersection of the two power signal lines is electrically connected through a first via.

4. The display panel according to claim 1, wherein: A third wiring layer and a fourth wiring layer are stacked and formed on the display panel; The first reset signal line in the transverse direction is arranged in the third wiring layer, and the first reset signal line in the longitudinal direction is arranged in the fourth wiring layer. The intersection of the two first reset signal lines is electrically connected through a second via hole.

5. The display panel according to claim 1, wherein: There are three reset connection lines, which are arranged side by side and spaced apart in the longitudinal direction, so as to be connected to the driving ICs respectively; The display panel further includes: Two second reset signal lines are arranged in a vertical and horizontal manner and are electrically connected at the intersection, the second reset signal line arranged in the horizontal direction is electrically connected to the drain of the fourth transistor of the pixel driving circuit, and one end of the second reset signal line arranged in the vertical direction extends to the first side; and Two third reset signal lines are arranged in a vertical and horizontal manner and are electrically connected at the intersection, the third reset signal line arranged in the horizontal direction is electrically connected to the drain of the seventh transistor of the pixel driving circuit, and one end of the third reset signal line arranged in the vertical direction extends to the first side; The ends of the first reset signal line, the second reset signal line and the third reset signal line are respectively connected to the three reset connection lines.

6. The display panel according to claim 5, wherein: The display panel includes a first signal line group and a second signal line group arranged in a vertical and horizontal manner, and the first signal line group and the second signal line group each include the first reset signal line, the second reset signal line and the third reset signal line arranged side by side and spaced apart.

7. The display panel according to claim 6, wherein: The first signal line group is arranged in the longitudinal direction; A plurality of the first signal line groups are provided, and the plurality of the first signal line groups are arranged side by side and spaced apart in a lateral direction.

8. The display panel according to claim 1, wherein: The display panel further includes a second power connection line, which is disposed on the first side and is used to electrically connect the pixel driving circuit and the driving IC.

9. The display panel according to claim 1, wherein: The pixel driving circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, the third transistor and the fourth transistor are N-type oxide transistors, and the first transistor, the second transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are all P-type oxide transistors.

10. A display device, characterized in that: Comprising the display panel as claimed in any one of claims 1 to 9.

Images