A scanning driving circuit, a display panel and a display device

Abstract

The embodiment of the application provides a scanning driving circuit, a display panel and a display device, characterized in that: input ends of i-th to (i+N)-th stage gating units are electrically connected with a same first scanning signal line; input ends of (i+N+1)-th to (i+N+M)-th stage gating units are electrically connected with a same second scanning signal line; i>=1, N>=1, M>=2; a first end of a first connecting unit is electrically connected with the first scanning signal line and a second end of the first connecting unit is electrically connected with the second scanning signal line; when the i-th to (i+N+M)-th stage gating units output scanning signals in turn, the maintaining time of adjacent output scanning signals in the scanning signals output in turn partially overlap; and in at least part of time period when the (i+N)-th stage gating unit and the (i+N+1)-th stage gating unit are both opened, the first connecting unit is opened and electrically connects the first scanning signal line and the second scanning signal line. The scheme provided by the application can effectively alleviate the horizontal stripe problem at the display partition boundary position.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a scanning drive circuit, a display panel, and a display device. Background Technology

[0002] With the development of display and hardware technologies, display panels are becoming increasingly larger. To fully utilize these panels, split-screen display functionality has emerged, allowing different user interfaces to be displayed simultaneously on different areas of the same panel. For example, some areas might display news, while others might display videos, or different game perspectives could be shown in different areas. Each display partition can be configured with a different refresh rate, but ensuring optimal display quality across all partitions remains a critical challenge. Summary of the Invention

[0003] In view of this, this application provides a scanning drive circuit, a display panel, and a display device.

[0004] In a first aspect, embodiments of this application provide a scan driving circuit, including Q cascaded shift registers and Q gating units. The output terminals of the shift registers are electrically connected to the control terminals of the gating units and are used to control the gating units to turn on. The input terminals of the gating units are electrically connected to the scan signal lines and are used to transmit initial scan signals to the gating units. The output terminals of the gating units are electrically connected to the scan lines and are used to output scan signals to the scan lines.

[0005] The scanning signal line includes a first scanning signal line and a second scanning signal line; the input terminals of the gating units from the i-th level to the (i+N)-th level are all electrically connected to the same first scanning signal line, and the input terminals of the gating units from the (i+N+1)-th level to the (i+N+M)-th level are all electrically connected to the same second scanning signal line; i≥1, N≥1, M≥2;

[0006] The scanning drive circuit further includes at least a first connecting unit, the first end of which is electrically connected to the first scanning signal line and the second end of which is electrically connected to the second scanning signal line; when the i-th to (i+N+M)-th level gating units sequentially output scanning signals, the duration of adjacent output scanning signals in these sequentially output scanning signals partially overlaps; and during at least a portion of the time when both the (i+N)-th level gating unit and the (i+N+1)-th level gating unit are turned on, the first connecting unit is turned on and electrically connects the first scanning signal line and the second scanning signal line.

[0007] In a second aspect, embodiments of this application provide a display panel including the scanning driving circuit provided in the first aspect; the display panel includes a display area, the display area includes a first area and a second area, both the first area and the second area include a first scan line, the output terminal of a first gating unit is electrically connected to the first scan line in the first area and the output terminal of a second gating unit is electrically connected to the first scan line in the second area.

[0008] Thirdly, embodiments of this application provide a display device, including a display panel as provided in the first aspect.

[0009] Among the multiple gating units electrically connected to the first scan signal line, the (i+N)th level gating unit, which outputs the scan signal last, is electrically connected to both the (i+N)th and (i+N+1)th level gating units during at least a portion of the scan signal output period. This is because the first and second scan signal lines are electrically connected through the first connecting unit. Consequently, the scan signal output by the (i+N)th level gating unit is momentarily pulled down during this portion of the period. Therefore, the scan signal output by the (i+N)th level gating unit tends to be consistent with the scan signals output by the i-th to (i+N-1)th level gating units, alleviating the horizontal stripe problem at the boundary of the display partitions. Attached Figure Description

[0010] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 A schematic diagram of a scanning drive circuit provided in an embodiment of this application;

[0012] Figure 2 for Figure 1 The diagram shows a timing diagram of one type of scanning drive circuit.

[0013] Figure 3 This is a schematic diagram of a scan driving circuit related to an embodiment of this application;

[0014] Figure 4 for Figure 3 The diagram shows a timing diagram of one type of scanning drive circuit.

[0015] Figure 5 This is an equivalent circuit diagram of a pixel circuit related to an embodiment of this application;

[0016] Figure 6A schematic diagram of a scanning drive circuit provided in an embodiment of this application;

[0017] Figure 7 A schematic diagram of a scanning drive circuit provided in an embodiment of this application;

[0018] Figure 8 for Figure 7 The diagram shows a timing diagram of one type of scanning drive circuit.

[0019] Figure 9 for Figure 7 The diagram shows a timing diagram of one type of scanning drive circuit.

[0020] Figure 10 A schematic diagram of a scanning drive circuit provided in an embodiment of this application;

[0021] Figure 11 for Figure 10 The diagram shows a timing diagram of one type of scanning drive circuit.

[0022] Figure 12 A schematic diagram of a scanning drive circuit provided in an embodiment of this application;

[0023] Figure 13 for Figure 12 The diagram shows a timing diagram of one type of scanning drive circuit.

[0024] Figure 14 A schematic diagram of a scanning drive circuit provided in an embodiment of this application;

[0025] Figure 15 for Figure 14 The diagram shows a timing diagram of one type of scanning drive circuit.

[0026] Figure 16 A partial schematic diagram of a display panel provided in an embodiment of this application;

[0027] Figure 17 This is a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0028] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0029] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0030] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0031] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0032] In the description of this specification, it should be understood that the terms "substantially", "approximately", "about", "about", "generally", "largely" used in the claims and embodiments of this application refer to values ​​that can be generally agreed upon within a reasonable range of process operations or tolerances, rather than a precise value.

[0033] It should be understood that although terms such as "first," "second," etc., may be used to describe parts, protective layers, vertices, etc., in the embodiments of this application, these should not be limited to these terms. These terms are only used to distinguish parts, protective layers, vertices, etc., from each other. For example, without departing from the scope of the embodiments of this application, the first part may also be referred to as the second part, and similarly, the second part may also be referred to as the first part. Through meticulous and in-depth research, the applicant of this case has provided a solution to the problems existing in the prior art.

[0034] Figure 1 This is a schematic diagram of a scanning drive circuit provided in an embodiment of this application. Figure 2 for Figure 1 The diagram shows a timing diagram of one type of scanning drive circuit.

[0035] like Figure 1 As shown, the scan driving circuit provided in this embodiment includes Q cascaded shift registers 10 and Q gating units 20. The output terminal of the shift register 10 is electrically connected to the control terminal of the gating unit 20, and the input terminal of the gating unit 20 is electrically connected to the scan signal line 30. The scan signal line 30 is used to transmit the initial scan signal PS to the gating unit 20. The output terminal of the shift register 10 outputs a trigger signal, which can trigger the operation of the next-stage shift register 10. In addition, the trigger signal output by the output terminal of the shift register 10 can enable the gating unit 20 electrically connected to the output terminal.

[0036] Shift register 10 is used to control the strobe unit 20 to be enabled, combined with Figure 1 and Figure 2When the outputs of the Q cascaded shift registers 10 sequentially start outputting trigger signals TS1, TS2, ..., TSQ, the Q gating units 20 are activated sequentially. The Q gating units 20 can be considered as the first-stage gating units 20 to the Q-stage gating units 20 electrically connected to the first-stage shift registers 10 to the Q-stage shift registers 10, respectively.

[0037] After receiving the initial scan signal PS, the gating unit 20 can either process and output the signal, or it can simply output the signal without processing it. For clarity, the signal output by the gating unit 20 that is related to the initial scan signal PS is called the scan signal. Therefore, the gating unit 20 is used to output the scan signal to the scan line. Combined with... Figure 1 and Figure 2 The first-stage gating unit 20 to the Q-stage gating unit 20 are used to output scan signals S1, S2, ..., SQ, respectively. The scan lines can be electrically connected to the gates of multiple transistors, and the scan signal refers to the enable signal that controls the transistor to turn on.

[0038] To facilitate understanding in conjunction with the accompanying drawings, Figure 2 The following is an example illustrating the use of a high-level voltage signal as the trigger signal, a high-level voltage signal as the initial scan signal PS, and a high-level voltage signal as the scan signal.

[0039] Multi-frequency Display (MFD) products are products that can achieve zoned frequency display, meaning the refresh rate of different display zones can be independently controlled. Here, a display zone refers to a different display area on the display panel. To achieve independent control of the refresh rate of different display zones, such as... Figure 1As shown, the Q gating units 20 can be divided into at least two gating unit groups 200. Different gating unit groups 200 can correspond to different display partitions. Each gating unit group 200 includes multiple gating units 20. The input terminals of the gating units 20 in the same gating unit group 200 are electrically connected to the same scan signal line 30, and the input terminals of the gating units 20 in at least adjacent different gating unit groups 200 are electrically connected to different scan signal lines 30. Although the first-stage shift register 10 to the Q-stage shift register 10 can sequentially output trigger signals to enable the first-stage gating unit 20 to the Q-stage gating unit 20 sequentially, the gating unit 20 in the gating unit group 200 will only output a scan signal sequentially when the gating unit 20 in the gating unit group 200 is sequentially enabled and the scan signal line 30 electrically connected to the gating unit 20 in the gating unit group 200 transmits the initial scan signal PS; if the scan signal line 30 electrically connected to the gating unit 20 in the gating unit group 200 does not transmit the initial scan signal PS, the gating unit 20 in the gating unit group 200 will not output a scan signal even if the gating unit 20 in the gating unit group 200 is sequentially enabled. Therefore, in this embodiment of the application, the frequency of the initial scan signal PS transmitted by the scan signal line 30 electrically connected to a gating unit group 200 can be controlled, thereby controlling the frequency of the scan signal output by the gating unit 20 in the gating unit group 200, and thus controlling the screen refresh rate of the display partition corresponding to the gating unit group 200.

[0040] by Figure 1 Taking an example, the first-level gating unit 20 to the eighth-level gating unit 20 are divided into a first gating unit group 201 and a second gating unit group 202. The scan signal lines 30 electrically connected to the first-level gating units 20 to the fourth-level gating units 20 in the first gating unit group 201 are different from the scan signal lines 30 electrically connected to the fifth-level gating units 20 to the eighth-level gating units 20 in the second gating unit group 202. Specifically, the input terminals of the gating units 20 in the first gating unit group 201 are all electrically connected to scan signal lines 31, and the input terminals of the gating units 20 in the second gating unit group 202 are all electrically connected to scan signal lines 32.

[0041] Combination Figure 1 and Figure 2In the first stage T1, shift registers 10 through 8 sequentially output trigger signals TS1, TS2, ..., TS8; and when shift registers 10 through 4 sequentially output trigger signals, the scan signal line 31 transmits the initial scan signal PS, and the gating units 20 through 4 sequentially output scan signals S1, S2, ..., S4; when shift registers 10 through 8 sequentially output trigger signals TS5, TS6, ..., TS8, the scan signal line 32 transmits the initial scan signal PS, and the gating units 20 through 5 sequentially output scan signals S5, S6, ..., S8.

[0042] Combination Figure 1 and Figure 2 In the first stage T1, shift registers 10 through 8 sequentially output trigger signals TS1, TS2, ..., TS8. While shift registers 10 through 4 sequentially output trigger signals, the scan signal line 31 transmits the initial scan signal PS, and the gating units 20 through 1 sequentially output scan signals S1, S2, ..., S4. When shift registers 10 through 8 sequentially output trigger signals TS5, TS6, ..., TS8, the scan signal line 30 does not transmit the initial scan signal PS, and the gating units 20 through 5 sequentially do not output scan signals. That is, within one scan cycle, the gating units 20 through 8 do not output scan signals until the gating units 10 through 4 sequentially output scan signals.

[0043] Similarly, in a scanning cycle, it is possible to ensure that the first to fourth level gating units 20 do not output scanning signals before the fifth to eighth level gating units 20 output scanning signals sequentially.

[0044] Therefore, the scanning drive circuit provided in this application embodiment can realize different display partitions with different screen refresh rates.

[0045] It should be noted that in one scan cycle, the first-stage shift register 10 to the Q-stage shift register output trigger signals TS1, TS2, ..., TSQ sequentially. This can also be understood as the period during which the first-stage shift register 10 to the Q-stage shift register outputs a trigger signal once in sequence constituting one scan cycle.

[0046] Furthermore, the duration of adjacent output scan signals overlaps, meaning the duration of scan signals output by adjacent gating units 20 overlaps. For example, combined with Figure 1 and Figure 2 In the first stage T1 and the second stage T2, when the first-level gating unit 20 to the eighth-level gating unit 20 sequentially output scan signals S1, S2, ..., S8, the start time of the scan signal S1 output by the first-level gating unit 20 is earlier than the start time of the scan signal S2 output by the second-level gating unit 20, and the duration of the scan signal S1 output by the first-level gating unit 20 overlaps with the duration of the scan signal S2 output by the second-level gating unit 20. The start time is earlier than the start time of the scan signal S3 output by the third-level gating unit 20, and the duration of the scan signal S2 output by the second-level gating unit 20 overlaps with the time portion of the scan signal S3 output by the third-level gating unit 20; ... the start time of the scan signal S7 output by the seventh-level gating unit 20 is earlier than the start time of the scan signal output by the eighth-level gating unit 20, and the duration of the scan signal S7 output by the seventh-level gating unit 20 overlaps with the time portion of the scan signal S8 output by the eighth-level gating unit 20. For example, combined with Figure 1 and Figure 2 In the first stage T1, when the first-level gating unit 20 to the fourth-level gating unit 20 sequentially output scan signals S1, S2, S3, and S4, the start time of the scan signal S1 output by the first-level gating unit 20 is earlier than the start time of the scan signal S2 output by the second-level gating unit 20, and the duration of the scan signal S1 output by the first-level gating unit 20 overlaps with the time portion of the scan signal S2 output by the second-level gating unit 20. The start time of the scan signal S2 output by the second-level gating unit 20... The start time of the scan signal S3 output by the third-level gating unit 20 is earlier than the start time of the scan signal S3 output by the second-level gating unit 20, and the duration of the scan signal S2 output by the second-level gating unit 20 overlaps with the time portion of the scan signal S3 output by the third-level gating unit 20. The start time of the scan signal S3 output by the third-level gating unit 20 is earlier than the start time of the scan signal S4 output by the fourth-level gating unit 20, and the duration of the scan signal S3 output by the third-level gating unit 20 overlaps with the time portion of the scan signal S4 output by the fourth-level gating unit 20.

[0047] Different gating unit groups 200 are electrically connected to different scan signal lines 30, which can also ensure that different gating units 20 in the gating unit group 200 maintain the same duration of output scan signal. For example, when the first gating unit group 20 to the fourth gating unit 20 of the first gating unit group 201 output scan signals S1, S2, S3 and S4 in sequence, and the fifth to eighth gating units 20 of the second gating unit group 202 do not output scan signals, although the scan signal line 31 is still transmitting the initial scan signal PS1 when the fifth gating unit 20 is turned on so that the fourth gating unit 20 maintains the output scan signal S4, since the fifth gating unit 20 is not electrically connected to the scan signal line 31 and the scan signal line 32 does not transmit scan signals, the fifth gating unit 20 is turned on but does not output scan signals at this time. This means that the duration of the fourth gating unit 20 maintaining the output scan signal S4 is not limited by whether the fifth gating unit 20 outputs scan signals.

[0048] Figure 3 This is a schematic diagram of a scan driving circuit related to an embodiment of this application. Figure 4 for Figure 3 The diagram shows a timing diagram of one type of scanning drive circuit.

[0049] In one embodiment of this application, the initial scan signal PS and the scan signal are both high-level signals, as an example for illustration. Figure 3 and Figure 4While the first-level gating unit 20 is still continuously outputting the scan signal S1, the second-level gating unit 20 begins to output the scan signal S2. The initial scan signal PS1 transmitted on the first scan signal line 31 changes from being provided to the first-level gating unit 20 to being provided to both the first-level gating unit 20 and the second-level gating unit 20 simultaneously. At this time, the scan signal output by the first-level gating unit 20 momentarily drops slightly. While the second-level gating unit 20 is still continuously outputting the scan signal S2, the third-level gating unit 20 begins to output the scan signal S3. The initial scan signal PS1 transmitted on the first scan signal line 31 changes from being provided to the second-level gating unit 20 to being provided to both the second-level gating unit 20 and the third-level gating unit 20 simultaneously. At this time, the scan signal S2 output by the second-level gating unit 20 momentarily drops slightly. While the third-level gating unit 20 is still continuously outputting the scan signal S3, the fourth-level gating unit 20 begins outputting the scan signal S4. The initial scan signal PS1 transmitted on the first scan signal line 31 changes from being supplied to the third-level gating unit 20 to being supplied to both the third-level and fourth-level gating units 20 simultaneously. At this time, the scan signal S3 output by the third-level gating unit 20 momentarily drops slightly. However, when the fourth-level gating unit 20 continuously outputs the scan signal S4, the first scan signal line does not provide the initial scan signal PS1 to any of the other gating units 20 besides the fourth-level gating unit 20. Therefore, the scan signal S4 output by the fourth-level gating unit 20 will not experience the same slight drop as the scan signals S1, S2, and S3 output by the first, second, and third-level gating units 20. This results in horizontal stripes appearing in the display partition corresponding to the first gating unit group 201.

[0050] It should be noted that the provision of the initial scan signal PS to the gating unit 20 means that the initial scan signal PS is transmitted to the activated gating unit 20 so that the activated gating unit 20 outputs a scan signal based on the initial scan signal PS.

[0051] To address this issue, this embodiment connects the scan signal lines 30 electrically connected to adjacent gating unit groups 200 to the same connecting unit 40. When at least one gating unit 20 in a gating unit group 200 that outputs a scan signal later and the next gating unit 20 in a gating unit group 200 that outputs a scan signal earlier are simultaneously activated, the connecting unit 40 enables the scan signal lines 30 electrically connected to the two gating unit groups 200 to conduct. When the scan signal lines 30 electrically connected to the two gating unit groups 200 are conducting, the two gating unit groups 200 can be considered as electrically connected to the same scan signal line 30. Therefore, the scan signal actually output by the gating unit 20 that outputs a scan signal later will be slightly pulled down when the gating unit 20 that outputs a scan signal earlier in the next gating unit group 200 is activated, thus making the scan signals output by different gating units 20 in the same gating unit group 200 essentially identical, thereby solving the aforementioned horizontal stripe problem.

[0052] like Figure 1 As shown, the scan signal line 30 includes a first scan signal line 31 and a second scan signal line 32. The input terminals of the i-th to (i+N)-th level gating units 20 are all electrically connected to the same first scan signal line 31, and the input terminals of the (i+N+1)-th to (i+N+M)-th level gating units 20 are all electrically connected to the same second scan signal line 32. It can be considered that the first gating unit group 201 includes the i-th to (i+N)-th level gating units 20, and the second gating unit group 202 includes the (i+N+1)-th to (i+N+M)-th level gating units 20. Each gating unit 20 in the first gating unit group 201 is electrically connected to the same first scan signal line 31, and each gating unit 20 in the second gating unit group 202 is electrically connected to the same second scan signal line 32.

[0053] Where i≥1, N≥1, and M≥2. Then, both the first gating unit group 201 and the second gating unit group 202 include at least two gating units 20. For example, as... Figure 1 As shown, the first gating unit group 201 includes gating units 20 from level 1 to level 4, so i = 1 and N = 3; the second gating unit group 202 includes gating units 20 from level 5 to level 8, so M = 4.

[0054] The operation of the scan driving circuit includes a first stage T1. In the first stage T1, the i-th to (i+N+M)-th level gating units 20 sequentially output scan signals Si, S(i+1), ..., S(i+N+M), and the duration of adjacent output scan signals Si, S(i+1), ..., S(i+N+M) partially overlaps. That is, in the first stage T1, among the scan signals Si, S(i+1), ..., S(i+N+M) sequentially output by the i-th to (i+N+M)-th level gating units 20, scan signal Si at least partially overlaps with scan signal S(i+1), scan signal S(i+1) at least partially overlaps with scan signal S(i+2), ..., scan signal S(i+N+M-1) at least partially overlaps with scan signal S(i+N+M). For example, as... Figure 1 As shown, if i = 1 and i + N + M = 8, then in the first stage T1, among the scanning signals S1, S2, ..., S8 output sequentially by the gating units 20 from level 1 to level 8, scanning signal S1 overlaps with scanning signal S2 at least partially, scanning signal S2 overlaps with scanning signal S3 at least partially, ..., scanning signal S7 overlaps with scanning signal S8 at least partially.

[0055] Furthermore, in the embodiments of this application, such as Figure 1 As shown, the scan driving circuit further includes at least a first connecting unit 41. The first end of the first connecting unit 41 is electrically connected to the first scan signal line 31, and the second end of the first connecting unit 41 is electrically connected to the second scan signal line 32. During at least a portion of the time when both the (i+N)th level gating unit 20 and the (i+N+1)th level gating unit 20 are turned on in the first stage T1, the first connecting unit 41 is turned on and electrically connects the first scan signal line 31 and the second scan signal line 32. That is, during at least a portion of the time when both the last level gating unit 20 in a gating unit group 200 and the first level gating unit 20 in the next gating unit group 200 output scan signals, the first connecting unit 41 electrically connects the scan signal lines 30 to which the two gating units 20 are respectively electrically connected.

[0056] In this embodiment, among the multiple gating units 20 electrically connected to the first scan signal line 31, the (i+N)th level gating unit 20, which outputs the scan signal last, is electrically connected to both the (i+N)th level gating unit 20 and the (i+N+1)th level gating unit 20 during at least a portion of the output scan signal period. This is because the first scan signal line 31 and the second scan signal line 32 are electrically connected through the first connecting unit 41. Consequently, the scan signal output by the (i+N)th level gating unit 20 is momentarily pulled down during this portion of the period. Therefore, the scan signal output by the (i+N)th level gating unit 20 is closer to the scan signals output by the i-th to (i+N-1)th level gating units 20, alleviating the horizontal stripe problem at the boundary of the display partitions.

[0057] For example, such as Figure 1 As shown, during at least a portion of the output scanning signal S4, the fourth-level gating unit 20 in the first gating unit group 201 is electrically connected to both the fourth-level gating unit 20 of the first gating unit group 201 and the fifth-level gating unit 20 of the second gating unit group 202 during the same period, because the first scanning signal line 31 and the second scanning signal line 32 are electrically connected through the first connecting unit 41. Therefore, at the instant when the first scanning signal line 31 and the second scanning line 32 are electrically connected and the fifth-level gating unit 20 is turned on, or at the instant when the fifth-level gating unit 20 is turned on and the first scanning signal line 31 and the second scanning line 32 are electrically connected, the scanning signal S4 output by the fourth-level gating unit 20 is momentarily pulled down slightly. Therefore, the scanning signal output by the fourth-level gating unit 20 in the first gating unit group 201 is similar to the scanning signals output by the first to third-level gating units 20, which are pulled down slightly, thus alleviating the horizontal stripe problem at the position of the display partition corresponding to the first gating unit group 201 close to the display partition corresponding to the second gating unit group 202.

[0058] In one embodiment of this application, the initial scan signal transmitted by the scan signal line 30 is a high-level signal, and the scan signal output by the gating unit 20 is also a high-level signal. When the scan signal is a high-level signal, the problem of horizontal lines appearing on the display partition is particularly noticeable when both gating units 20 are simultaneously activated, as the scan signal is momentarily pulled down. In this case, the technical solution provided in the embodiment of this application can effectively alleviate the above problem.

[0059] Figure 5 This is an equivalent circuit diagram of a pixel circuit related to an embodiment of this application.

[0060] like Figure 5As shown, the pixel circuit includes a driving transistor M0, a data writing transistor M1, a threshold writing transistor M2, a first reset transistor M3, a second reset transistor M4, a power supply voltage writing transistor M5, a light-emitting control transistor M6, and a storage capacitor Cst. The first terminal of the driving transistor M0 is electrically connected to the data writing transistor M1 and the power supply voltage writing transistor M5; the second terminal of the driving transistor M0 is electrically connected to the first terminal of the threshold writing transistor M2 and the first terminal of the light-emitting control transistor M6; the gate of the driving transistor M0 is electrically connected to the first reset transistor M3 and the storage capacitor Cst; the second terminal of the threshold writing transistor M2 is electrically connected to the gate of the driving transistor M0; and the second terminal of the light-emitting control transistor M6 is electrically connected to the light-emitting device LD and the second reset transistor M4.

[0061] When the first reset transistor M3 and the second reset transistor M4 are turned on, they are used to reset the gate of the driving transistor M0 and the second terminal of the light-emitting control transistor M6, respectively. When the data writing transistor M1 and the threshold writing transistor M2 are turned on, they are used to write the data voltage to the gate of the driving transistor M0, respectively. When the power supply voltage writing transistor M5 and the light-emitting control transistor M6 are turned on, they control the driving transistor M0 to generate a light-emitting driving current.

[0062] The stability of the data voltage written to the gate of the driving transistor M0 affects the reliability of the light-emitting driving current. To ensure that the data voltage is stably stored at the gate of the driving transistor M0, the first reset transistor M3 and the threshold write transistor M2, which are electrically connected to the gate of the driving transistor M0, can be N-channel transistors to alleviate the problem of significant changes in the gate potential of the driving transistor M0 due to leakage current. Optionally, the semiconductor layer of the first reset transistor M3 and the threshold write transistor M2 can be a metal-oxide-semiconductor layer.

[0063] The scan driving circuit provided in this application embodiment can be electrically connected to the gate of the first reset transistor M3 and / or the gate of the threshold write transistor M2 in the pixel circuit. That is, the scan signal output by the gating unit in the scan driving circuit is used to control the first reset transistor M3 to turn on and / or control the threshold write transistor M2 to turn on. When the pixel circuit includes both the first reset transistor M3 and the threshold write transistor M2, and both the first reset transistor M3 and the threshold write transistor M2 are N-channel transistors, the first reset transistor M3 and the threshold write transistor M2 can be electrically connected to different scan driving circuits provided in this application. When only the first reset transistor M3 in the pixel circuit is an N-channel transistor, the first reset transistor M3 can be electrically connected to the scan driving circuit provided in this application. When only the threshold write transistor M2 in the pixel circuit is an N-channel transistor, the threshold write transistor M2 can be electrically connected to the scan driving circuit provided in this application.

[0064] It should be noted that, Figure 5 One possible pixel circuit related to this application is given. Furthermore, the scan driving circuit provided in the embodiments of this application can also be combined with other... Figure 5 The present application does not limit the electrical connections of pixel circuits in other structures besides those mentioned above.

[0065] Figure 6 This is a schematic diagram of a scanning drive circuit provided in an embodiment of this application.

[0066] In one embodiment of this application, such as Figure 6 As shown, the first connecting unit 41 includes at least one connecting transistor MC. The first end of the first connecting unit 41 can be the first pole of the connecting transistor MC, the second end can be the second pole of the connecting transistor MC, and the control end can be the gate of the connecting transistor MC. When the first connecting unit 41 is turned on, the first pole and the second pole of the connecting transistor MC included therein are electrically connected.

[0067] In this embodiment, the at least one connecting transistor MC is a P-channel transistor. Therefore, when a low-level control signal is received at the control terminal of the first connecting unit 41, the first connecting unit 41 is turned on. Since the connecting transistor MC in the first connecting unit 41 is a P-channel transistor, the first connecting unit 41 turns on more promptly upon receiving a low-level control signal. Furthermore, when the scan signal is a high-level signal, selecting the P-channel connecting transistor MC as the switch in the first connecting unit 41 to achieve electrical conduction and insulation between the first scan signal line 31 and the second scan signal line 32 reduces the risk of the first connecting unit 41 being mistakenly turned on by a high-level scan signal and the initial scan signal PS. Therefore, the first connecting unit 41 can function more effectively.

[0068] For ease of description and illustration, the first transistor in the first connecting unit 41 is a P-channel transistor as an example for the following explanation.

[0069] In one embodiment of this application, such as Figure 6 As shown, the first connection unit 41 includes a connection transistor MC, that is, the first scan signal line 31 and the second scan signal line 32 are connected to a single connection transistor MC. By setting fewer connection transistors MC to connect the first scan signal line 31 and the second scan signal line 32, the manufacturing process can be simplified; and when the scan driving circuit is located in the bezel area of ​​the display panel, it is beneficial to achieve a narrow bezel for the display panel.

[0070] Figure 7 This is a schematic diagram of a scanning drive circuit provided in an embodiment of this application.

[0071] In one embodiment of this application, such as Figure 7 As shown, the first connection unit 41 includes at least two connection transistors MC, and the first terminals of the at least two connection transistors MC are electrically connected to the first scan signal line 31, and the second terminals of the at least two connection transistors MC are electrically connected to the second scan signal line 32. That is, the first scan signal line 31 and the second scan signal line 32 are connected to the at least two connection transistors MC. By setting more connection transistors MC to connect the first scan signal line 31 and the second scan signal line 32, on the one hand, the risk of the first scan signal line 31 and the second scan signal line 32 failing to conduct due to damage to the connection transistors MC can be reduced; on the other hand, the impedance between the first scan signal line 31 and the second scan signal line 32 can be made smaller when the at least two connection transistors MC are turned on, so that the (i+N+1)th stage gating unit can effectively pull down the scan signal S(i+N) output by the (i+N)th stage gating unit 20.

[0072] When the first connecting unit 41 includes at least two connecting transistors MC, the positions of these at least two connecting transistors MC can be distributed dispersed along the extension directions of the first scan signal line 31 and the second scan signal line 32. For example, as Figure 7 As shown, the first connecting unit 41 includes three connecting transistors MC, and the three connecting transistors MC are respectively located near the upper end of the first scan signal line 31 and the second scan signal line 32, near the lower end of the first scan signal line 31 and the second scan signal line 32, and near the middle of the first scan signal line 31 and the second scan signal line 32 in their extension direction.

[0073] In addition, such as Figure 7 As shown, when the first connecting unit 41 includes at least two connecting transistors MC, the control terminals of the at least two connecting transistors MC can be electrically connected to the same control signal line 400. Multiple connecting transistors MC in the first gating unit 41 can be simultaneously turned on via a single control signal line 400, eliminating the need to configure an excessive number of control signal lines 400 and reducing manufacturing complexity. Furthermore, when the scanning drive circuit is located in the bezel area of ​​the display panel, it facilitates the achievement of a narrow bezel for the display panel.

[0074] In this embodiment, the conduction time of the first scan signal line 31 and the second scan signal line 32 can be determined based on the number of other scan signals that overlap with the duration of the scan signal. The number of other scan signals that overlap with the duration of the scan signal is approximately equal to the number of times the scan signals output by the gating units 20 in the gating unit group 200, excluding the gating unit 20 that outputs the scan signal later, are instantaneously pulled down.

[0075] Figure 8 for Figure 7The diagram shows a timing diagram of one type of scanning drive circuit.

[0076] For example, such as Figure 8 As shown, if the number of other scan signals overlapping with the duration of a scan signal is 1, then the scan signals S1, S2, ..., S(i+N-1) output by the first-level gating unit 20, the second-level gating unit 20, and the third-level gating unit 20 in the first gating unit group 201 overlap with one adjacent output scan signal, that is, scan signal S1 at least partially overlaps with scan signal S2, scan signal S2 at least partially overlaps with scan signal S3, ..., scan signal S(i+N-1) at least partially overlaps with scan signal S(i+N). It can be understood that the number of times scan signals S1, S2, ..., S(i+N-1) are instantaneously pulled down is 1 each, therefore the conduction time of the first scan signal line 31 and the second scan signal line S2 should ensure that scan signal S(i+N) is pulled down once. Therefore, as... Figure 8 As shown, the scan control line 400 transmits at least a portion of the scan signal enable signal Ctr (low level signal) when the (i+N) level gating unit 20 and the (i+N+1) level gating unit 20 simultaneously output the scan signal. That is, the first scan signal line 31 and the second scan signal line 32 are electrically connected during at least a portion of the time period when the (i+N) level gating unit 20 and the (i+N+1) level gating unit 20 simultaneously output the scan signal, so that the scan signal S(i+N) is pulled down twice.

[0077] Figure 9 for Figure 7 The diagram shows a timing diagram of one type of scanning drive circuit.

[0078] For example, such as Figure 9 As shown, if the number of other scan signals that overlap with the duration of a scan signal is 2, then the scan signals S1, S2, ..., S(i+N-1) output by the first-level gating unit 20, the second-level gating unit 20, ..., the (i+N-1)-level gating unit 20 in the first gating unit group 201 overlap with 2 adjacent output scan signals respectively. That is, scan signal S1 overlaps at least partially with scan signal S2 and at least partially with scan signal S3, scan signal S2 overlaps at least partially with scan signal S3 and at least partially with scan signal S4, ... Understandably, if the scan signals S1, S2, and S3 are pulled down instantaneously twice, the scan signal S(i+N-1) is pulled down instantaneously once, and the scan signal S(i+N) is pulled down instantaneously zero times, then the conduction time of the first scan signal line 31 and the second scan signal line S2 should ensure that the scan signals S(i+N-1) and S(i+N) are pulled down instantaneously twice. Therefore, if Figure 9As shown, the scan control line 400 transmits an enable signal Ctr (low-level signal) during at least a portion of the time when the scan signals are simultaneously output by the (i+N-1)th level gating unit 20, the (i+N)th level gating unit 20, and the (i+N+1)th level gating unit 20. That is, the first scan signal line 31 and the second scan signal line 32 are electrically connected during at least a portion of the time when the scan signals are simultaneously output by the (i+N-1)th level gating unit 20, the (i+N)th level gating unit 20, and the (i+N+1)th level gating unit 20, so that the scan signal S(i+N-1) is transmitted. 1) The scan signal S(i+N-1) is pulled down once again; and the scan control line 400 transmits the enable signal Ctr (low level signal) for at least a part of the time period when the scan signal is simultaneously output by the (i+N) level gating unit 20 and the (i+N+2) level gating unit 20, that is, the first scan signal line 31 and the second scan signal line 32 are electrically connected for at least a part of the time period when the scan signal is simultaneously output by the (i+N) level gating unit 20 and the (i+N+2) level gating unit 20, so that the scan signal S(i+N) is pulled down once again.

[0079] Furthermore, when the gating units 20 at levels i to (i+N) sequentially output scan signals and the gating units 20 at levels (i+N+1) to (i+N+M) remain off, the duration of adjacent output scan signals overlaps, and the first connecting unit 41 remains off. Figure 8 and Figure 9 As shown, the operation of the scanning drive circuit includes a second stage T2. In the second stage T2, the gating unit 20 in the first gating unit group 201 outputs scanning signals in sequence, while the gating unit 202 in the second gating unit group 202 does not output scanning signals. Therefore, the first connecting unit 41 remains in the off state in the second stage T2 to avoid the gating unit 202 in the second gating unit group 202 from mistakenly outputting scanning signals.

[0080] Figure 10 This is a schematic diagram of a scanning drive circuit provided in an embodiment of this application.

[0081] In one embodiment of this application, the Q gating units 20 are at least divided into a first gating unit group 201, a second gating unit group 202, and a third gating unit group 203. Each of the first gating unit group 201, the second gating unit group 202, and the third gating unit group 203 includes a plurality of gating units 20 capable of sequentially outputting scanning signals.

[0082] Specifically, such as Figure 10As shown, the first gating unit group 201 includes gating units 20 at levels i to (i+N), the second gating unit group 202 includes gating units 20 at levels (i+N+1) to (i+N+M), and the third gating unit group 203 includes gating units 20 at levels (i+N+M+1) to (i+N+M+K). The shift registers 10 at levels i to (i+N+M+K) can sequentially output trigger signals TSi to (i+N+M+K). Whether the multiple gating units 20 included in the first gating unit group 201, the second gating unit group 202, and the third gating unit group 203 can output scan signals depends on whether their respective electrically connected scan signal lines 30 transmit primary scan signals when they are turned on. Where K ≥ 2.

[0083] The operation of the scanning drive circuit includes a third stage T3. In the third stage T3, the gating units 20 of the (i+N+1)th to (i+N+M+K)th stages sequentially output S(i+N+1), S(i+N+M+1), ..., S(i+N+M+K), and the duration of adjacent output scanning signals S(i+N+1), S(i+N+M+1), ..., S(i+N+M+K) overlaps. That is, in the third stage T3, among the scanning signals S(i+N+1), S(i+N+M+1), ..., S(i+N+M+K) sequentially output by the gating units 20 from level (i+N+1) to level (i+N+M+K), the scanning signal S(i+N+1) overlaps at least partially with the scanning signal S(i+N+2), the scanning signal S(i+N+2) overlaps at least partially with the scanning signal S(i+N+3), ..., the scanning signal S(i+N+M+K-1) overlaps at least partially with the scanning signal S(i+N+M+K). For example, as... Figure 10 As shown, i+N+1=5 and i+N+M+K=12, then in the third stage T3, among the scanning signals S5, S6, ..., S12 output sequentially by the gating units 20 of the 5th to 12th levels, scanning signal S5 overlaps with scanning signal S6 at least partially, scanning signal S6 overlaps with scanning signal S7 at least partially, ..., scanning signal S11 overlaps with scanning signal S12 at least partially.

[0084] The scan signal line 30 electrically connected to the input terminal of the (i+N+M+1) to (i+N+M+K) level gating unit 20 is different from the scan signal line 30 electrically connected to the input terminal of the (i+N+1) to (i+N+M) level gating unit 20; and the scan driving circuit also includes a second gating unit 42, the first terminal of the second connecting unit 42 is electrically connected to the second scan signal line 32, and the second terminal of the second connecting unit 42 is electrically connected to the scan signal line 30 electrically connected to the input terminal of the (i+N+M+1) to (i+N+M+K) level gating unit 20. During at least a portion of the time when both the (i+N+M)th level gating unit 20 and the (i+N+M+1)th level gating unit 20 are turned on in the third stage T3, the second connecting unit 42 turns on and electrically conducts the scan signal line 30 electrically connected to the input terminals of the second scan signal line 32 and the gating signal line 30 from the (i+N+M+1)th level to the (i+N+M+K)th level gating units 20. That is, during at least a portion of the time when both the last gating unit 20 in the second gating unit group 202 and the first gating unit 20 in the third gating unit group 203 output scan signals, the second connecting unit 42 electrically conducts the scan signal lines 30 electrically connected to the two gating units 20 respectively. During this time period, the second scan signal line 32 simultaneously interacts with both the activated (i+N+M) level gating unit 20 and the activated (i+N+M+1) level gating unit 20, causing the scan signal output by the (i+N+M) level gating unit 20 to be momentarily pulled down. Therefore, the scan signal output by the (i+N+M) level gating unit 20 becomes more consistent with the scan signals output by the (i+N+1) to (i+N+M-1) level gating units 20, alleviating the horizontal stripe problem at the boundary between the display partition corresponding to the second gating unit group 202 and the display partition corresponding to the third gating unit group 203.

[0085] Figure 11 for Figure 10 The diagram shows a timing diagram of one type of scanning drive circuit.

[0086] In one technical solution corresponding to this embodiment, such as Figure 10 As shown, the scan signal line 30 also includes a third scan signal line 33; the input terminals of the (i+N+M+1)th to (i+N+M+K)th level gating units 20 are electrically connected to the same third scan signal line 33; the first terminal of the second connecting unit 42 is electrically connected to the second scan signal line 32 and the second terminal of the second connecting unit 42 is electrically connected to the third scan signal line 33. Combined with... Figure 10 and Figure 11During at least a portion of the time period in the third stage T3 when both the (i+N+M)th level gating unit 20 and the (i+N+M+1)th level gating unit 20 are turned on, the second connection unit 42 is turned on and electrically connects the second scan signal line 32 and the third scan signal line 33. For example, as Figure 11 As shown, the control signal line 402 of the connecting transistor MC included in the second connecting unit 42 transmits an enable signal Ctr2 during at least a portion of the time period when both the (i+N+M) level gating unit 20 and the (i+N+M+1) level gating unit 20 are turned on, so as to electrically connect the second scan signal line 32 and the third scan signal line 33.

[0087] In this technical solution, the gating unit 20 in the first gating unit group 201, the gating unit 20 in the second gating unit group 202, and the gating unit 20 in the third gating unit group 203 are electrically connected to different scanning signal lines 30, which enables the screen refresh rate of the display partitions corresponding to the first gating unit group 201, the second gating unit group 202, and the third gating unit group 203 to be individually controllable, and alleviates the problem of horizontal stripes at the junction of adjacent display partitions.

[0088] Figure 12 This is a schematic diagram of a scanning drive circuit provided in an embodiment of this application. Figure 13 for Figure 12 The diagram shows a timing diagram of one type of scanning drive circuit.

[0089] In one technical solution corresponding to this embodiment, such as Figure 12 As shown, the scan signal line 30 also includes a third scan signal line 33; the input terminals of the (i+N+M+1)th to (i+N+M+K)th level gating units 20 are electrically connected to the same third scan signal line 33; the first terminal of the second connecting unit 42 is electrically connected to the first scan signal line 31, and the second terminal of the second connecting unit 42 is electrically connected to the third scan signal line 33. Combined with... Figure 12 and Figure 13 During at least a portion of the time period in the third stage T3 when both the (i+N+M)th level gating unit 20 and the (i+N+M+1)th level gating unit 20 are turned on, both the first connecting unit 201 and the second connecting unit 202 are turned on and electrically connect the second scan signal line 32 and the third scan signal line 33. For example, as Figure 13 As shown, the control signal line 401 of the first connecting unit 41, which is electrically connected to the connecting transistor MC, and the control signal line 402 of the second gating unit 42, which is electrically connected to the connecting transistor MC, respectively transmit enable signals Ctr1 and Ctr2 during at least a portion of the time periods when both the (i+N+M) level gating unit 20 and the (i+N+M+1) level gating unit 20 are turned on, so as to electrically conduct the second scan signal line 32 and the third scan signal line 33.

[0090] When the first connecting unit 201 is turned on, the first scan signal line 31 and the second scan signal line 32 are electrically connected; when the second connecting unit 201 is turned on, the first scan signal line 31 and the third scan signal line 33 are electrically connected. Therefore, when both the first connecting unit 201 and the second connecting unit 202 are turned on, the second scan signal line 32 and the third scan signal line 33 can be electrically connected.

[0091] It should be noted that the structure and working principle of the second gating unit 42 are similar to those of the first gating unit 41, and will not be repeated here.

[0092] Figure 14 This is a schematic diagram of a scanning drive circuit provided in an embodiment of this application. Figure 15 for Figure 14 The diagram shows a timing diagram of one type of scanning drive circuit.

[0093] In one technical solution corresponding to this embodiment, such as Figure 14 As shown, the input terminals of the (i+N+M+1)th to (i+N+M+K)th level gating units 20 are electrically connected to the first scan signal line 33; combined with Figure 14 and Figure 15 During at least a portion of the time when both the (i+N+M) level gating unit 20 and the (i+N+M+1) level gating unit 20 are active in the third stage T3, the first connection unit 201 is activated and electrically connects the first scan signal line 31 and the second scan signal line 32. Since the input terminals of the (i+N+M+1) to (i+N+M+K) level gating units 20 are electrically connected to the first scan signal line 33, when the (i+N+M+1) level gating unit 20 is active in the third stage T3, the first scan signal line 31 transmits the initial scan signal, thus electrically connecting the first scan signal line 31 and the second scan signal line 32. Therefore, the second scan signal line 32 is equivalent to electrically connecting the simultaneously active (i+N+M) level gating unit 20 and the (i+N+M+1) level gating unit 20. For example, as... Figure 11 As shown, the control signal line 400 of the connecting transistor MC included in the first connecting unit 41 transmits an enable signal Ctr during at least a portion of the time period when both the (i+N+M) level gating unit 20 and the (i+N+M+1) level gating unit 20 are turned on, so as to electrically connect the first scan signal line 31 and the second scan signal line 32.

[0094] It should be noted that the third stage T3 may or may not belong to the same scan cycle as the first stage T1. Similarly, the second stage T2 may or may not belong to the same scan cycle as the first stage T1.

[0095] Figure 16 This is a partial schematic diagram of a display panel provided in an embodiment of this application.

[0096] In one embodiment of this application, such as Figure 16 As shown, the display panel 01 includes a display area AA and a non-display area NA, with the non-display area NA surrounding the display area AA. The display panel 01 includes the scanning drive circuit provided in any of the above embodiments. The scanning drive circuit can be the non-display area NA of the display panel. In narrow-bezel or borderless display panels, the scanning drive circuit can also be located in the display area AA.

[0097] Display area AA includes a first area AA1 and a second area AA2. Both the first area AA1 and the second area AA2 include a first scan line 50. The output terminals of the i-th to (i+N)-th level gating units 20 are electrically connected to the first scan line 50 in the first area AA1, and the output terminals of the (i+N+1)-th to (i+N+M)-th level gating units 20 are electrically connected to the first scan line 50 in the second area AA2. That is, the gating units 20 in the first gating unit group 201 are electrically connected to the first scan line 50 in the first area AA1, and the gating units 20 in the second gating unit group 202 are electrically connected to the first scan line 50 in the second area AA2. The first area AA1 and the second area AA2 can be different display partitions.

[0098] The technical solution provided in this application embodiment can alleviate the problem of horizontal lines at the junction of the first area AA1 and the second area AA2, and improve the display uniformity of the display panel 01.

[0099] In one technical solution, combining Figure 5 As shown, both the first region AA1 and the second region AA2 further include a pixel circuit 60. The pixel circuit 60 includes a driving transistor M0 and a first transistor. The first transistor is electrically connected to the gate of the driving transistor M0, and the first transistor is an N-channel transistor. The first transistor can be a threshold write transistor M2 or a first reset transistor M3. It should be noted that... Figure 5 The pixel circuit shown is only one possible implementation. In some embodiments, the pixel circuit can also be a pixel circuit with other structures.

[0100] The first scan line 60 is electrically connected to the gate of the first transistor, meaning that the gate of the first transistor receives the scan signal output by the scan driving circuit provided in this application embodiment through the first scan line.

[0101] In addition, the display panel 01 may also include a second scan line, a third scan line, etc., which can be electrically connected to the gates of other transistors in the pixel circuit except for the first transistor.

[0102] Figure 17 This is a schematic diagram of a display device provided in an embodiment of this application.

[0103] This application also provides a display device, such as... Figure 17 As shown, the display device includes the display panel 01 provided in any of the above embodiments. The display device provided in this application embodiment can be an electronic device such as a mobile phone, computer, television, or vehicle display device. This application embodiment does not impose specific limitations.

[0104] The display uniformity of the display device provided in this application embodiment can be significantly improved.

[0105] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A scan driving circuit, characterized by comprising: The scan driving circuit comprises Q cascaded shift registers and Q gating units, an output terminal of the shift register is electrically connected with a control terminal of the gating unit and is used for controlling the gating unit to be turned on, an input terminal of the gating unit is electrically connected with a scan signal line and the scan signal line is used for transmitting an initial scan signal to the gating unit, and an output terminal of the gating unit is electrically connected with a scan line and is used for outputting a scan signal to the scan line. The scan signal line comprises a first scan signal line and a second scan signal line; input terminals of the gating units at the i-th stage to the (i+N)-th stage are electrically connected with the same first scan signal line, and input terminals of the gating units at the (i+N+1)-th stage to the (i+N+M)-th stage are electrically connected with the same second scan signal line; i≥1, N≥1, and M≥2. The scan driving circuit further comprises a first connecting unit, a first terminal of the first connecting unit is electrically connected with the first scan signal line, and a second terminal of the first connecting unit is electrically connected with the second scan signal line; when the gating units at the i-th stage to the (i+N+M)-th stage output the scan signals in sequence, the maintaining time of the scan signals output in sequence partially overlaps; and during at least a part of the period when the gating units at the (i+N)-th stage and the (i+N+1)-th stage are both turned on, the first connecting unit is turned on and electrically connects the first scan signal line and the second scan signal line.

2. The scan driving circuit according to claim 1, wherein when the gating units at the i-th stage to the (i+N)-th stage output the scan signals in sequence and the gating units at the (i+N+1)-th stage to the (i+N+M)-th stage are kept in an off state, the maintaining time of the scan signals output in sequence partially overlaps, and the first connecting unit is kept in an off state.

3. The scan driving circuit according to claim 1, wherein The scan signal is a high-level signal.

4. The scan driving circuit according to claim 1 or 3, wherein The first connecting unit comprises at least one connecting transistor, and the at least one connecting transistor is a P-channel transistor.

5. The scan driving circuit according to claim 1, wherein The first connecting unit comprises at least two connecting transistors, first electrodes of the at least two connecting transistors are electrically connected with the first scan signal line, and second electrodes of the at least two connecting transistors are electrically connected with the second scan signal line.

6. The scan driving circuit according to claim 1, wherein The scan signal line further comprises a third scan signal line; input terminals of the gating units at the (i+N+M+1)-th stage to the (i+N+M+K)-th stage are electrically connected with the same third scan signal line, and K≥2. The scan driving circuit further comprises a second connecting unit, a first terminal of the second connecting unit is electrically connected with the second scan signal line, and a second terminal of the second connecting unit is electrically connected with the third scan signal line. The maintaining time of the scan signals outputted by the gate units in the (i+N+1)th stage to the (i+N+M+K)th stage partially overlap with each other, and the second connecting unit is open and electrically connects the second scan signal line and the third scan signal line in at least a part of time period when the gate units in the (i+N+M)th stage and the (i+N+M+1)th stage are both open.

7. The scan driving circuit according to claim 1, wherein The scan signal line further comprises a third scan signal line, and the input terminals of the gate units in the (i+N+M+1)th stage to the (i+N+M+K)th stage are electrically connected with the same third scan signal line, K≥2. The scan driving circuit further comprises a second connecting unit, the first terminal of the second connecting unit is electrically connected with the first scan signal line, and the second terminal of the second connecting unit is electrically connected with the third scan signal line. The maintaining time of the scan signals outputted by the gate units in the (i+N+1)th stage to the (i+N+M+K)th stage partially overlap with each other, and the first connecting unit and the second connecting unit are both open and electrically connect the second scan signal line and the third scan signal line in at least a part of time period when the gate units in the (i+N+M)th stage and the (i+N+M+1)th stage are both open.

8. The scan driving circuit according to claim 1, wherein The input terminals of the gate units in the (i+N+M+1)th stage to the (i+N+M+K)th stage are electrically connected with the same first scan signal line, K≥2. The maintaining time of the scan signals outputted by the gate units in the (i+N+1)th stage to the (i+N+M+K)th stage partially overlap with each other, and the first connecting unit is open and electrically connects the first scan signal line and the second scan signal line in at least a part of time period when the gate units in the (i+N+M)th stage and the (i+N+M+1)th stage are both open.

9. A display panel, characterized by, The display panel comprises a display area, the display area comprises a first area and a second area, and the first area and the second area both comprise a first scan line, the output terminals of the gate units in the ith stage to the (i+N)th stage are electrically connected with the first scan line in the first area, and the output terminals of the gate units in the (i+N+1)th stage to the (i+N+M)th stage are electrically connected with the first scan line in the second area. The first area and the second area both further comprise a pixel circuit, the pixel circuit comprises a driving transistor and a first transistor, the first transistor is electrically connected with the gate of the driving transistor, and the first transistor is an N-channel transistor.

10. The display panel of claim 9, wherein, The first scan line is electrically connected with the gate of the first transistor. The display panel comprises a display area, the display area comprises a first area and a second area, and the first area and the second area both comprise a first scan line, the output terminals of the gate units in the ith stage to the (i+N)th stage are electrically connected with the first scan line in the first area, and the output terminals of the gate units in the (i+N+1)th stage to the (i+N+M)th stage are electrically connected with the first scan line in the second area.

11. A display device, characterized by comprising: The first area and the second area both further comprise a pixel circuit, the pixel circuit comprises a driving transistor and a first transistor, the first transistor is electrically connected with the gate of the driving transistor, and the first transistor is an N-channel transistor. The first scan line is electrically connected with the gate of the first transistor. The display panel comprises a display area, the display area comprises a first area and a second area, and the first area and the second area both comprise a first scan line, the output terminals of the gate units in the ith stage to the (i+N)th stage are electrically connected with the first scan line in the first area, and the output terminals of the gate units in the (i+N+1)th stage to the (i+N+M)th stage are electrically connected with the first scan line in the second area.

Images