Display device and driving method thereof, display terminal

Abstract

The application provides a display device and a driving method thereof and a display terminal. A level converter in the display device is configured to generate a first clock signal. A timing controller is configured to generate a control signal when a refresh rate is greater than a preset value, and the control signal is configured to control the level converter to process the first clock signal to generate a second clock signal. The second clock signal includes a plurality of second clock pulses corresponding to a plurality of first clock pulses in the first clock signal. An end time of the second clock pulse is later than an end time of the corresponding first clock pulse. The risk of incorrect charging at a low refresh rate is reduced.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically to display devices and their driving methods, and display terminals. Background Technology

[0002] In display technology, CS (Charge Sharing) technology can achieve charge sharing when two signals with opposite phases switch between high and low potentials, reducing the additional voltage difference required for active switching and reducing the power consumption of the driver.

[0003] However, the waveform of the signal affected by CS (Continuous Scanning) technology changes, causing the transistors in the pixel circuits to fail to turn off completely in time. This results in leakage of data signals from subsequent rows into the pixel circuits of that row. The lower the refresh rate, the longer the leakage time, the greater the risk of incorrect charging, and the greater the impact on image quality. Summary of the Invention

[0004] The purpose of this invention is to provide a display device and its driving method, and a display terminal, so as to solve the problem that the existing CS technology has a high risk of incorrect charging at low refresh rates.

[0005] This invention provides a display device, comprising:

[0006] Display panel;

[0007] A timing controller is used to generate a control signal based on the refresh rate of the display panel, wherein the control signal is a first control signal when the refresh rate is greater than a preset value;

[0008] A level converter, electrically connected to the timing controller, is used to generate a first clock signal and to process the first clock signal to generate a second clock signal when the control signal is the first control signal.

[0009] The first clock signal includes a plurality of first clock pulses, the time period of the second clock pulse overlaps with the time period of the corresponding first clock pulse, and the end time of the second clock pulse is later than the end time of the corresponding first clock pulse.

[0010] In some embodiments, including:

[0011] A gate driver, integrated within the display panel or disposed independently of the display panel, is configured to generate a first gate signal based on a first clock signal when the refresh rate is less than or equal to the preset value, and to generate a second gate signal based on a second clock signal when the refresh rate is greater than the preset value.

[0012] In some embodiments, the level converter includes:

[0013] Level conversion module, used to generate the first clock signal;

[0014] The charge sharing module, electrically connected to the level conversion module, is used to determine whether to process the first clock signal to generate the second clock signal based on the control signal.

[0015] In some embodiments, the first clock signal includes a first sub-clock signal and a second sub-clock signal that are inverse signals of each other, and the second clock signal includes a first shared sub-clock signal corresponding to the first sub-clock signal and a second shared sub-clock signal corresponding to the second sub-clock signal.

[0016] The charge sharing module includes a first input module, a second input module, a first output module, a second output module, and a first switch module.

[0017] The first input module is used to receive the first sub-clock signal, which includes a plurality of first sub-clock pulses;

[0018] The second input module is used to receive the second sub-clock signal, the second sub-clock signal including a plurality of second sub-clock pulses corresponding to a plurality of first sub-clock pulses;

[0019] The first switch module is used to control the first output module to output the first sub-clock signal and control the second output module to output the second sub-clock signal according to the control signal, or to control the first output module to output the first shared sub-clock signal and control the second output module to output the second shared sub-clock signal.

[0020] In some embodiments, the charge sharing module further includes:

[0021] The second switch module is used to control whether the first input module transmits the first sub-clock signal to the first output module according to the control signal.

[0022] The third switch module is used to control whether the second input module transmits the second sub-clock signal to the second output module according to the control signal.

[0023] In some embodiments, the timing controller is used to obtain the frame blanking duration of the previous frame and to calculate the corresponding refresh rate based on the frame blanking duration.

[0024] Alternatively, the timing controller is used to calculate the corresponding refresh rate based on the frame start signal.

[0025] Embodiments of the present invention also provide a display terminal, including a display device as described above and a motherboard electrically connected to the display device, the motherboard being used to at least transmit image signals to the display device to control the display panel to display an image.

[0026] This invention also provides a driving method for a display device, the display device including a display panel, a timing controller, and a level converter electrically connected to the timing controller, the driving method for the display device including:

[0027] The level converter is controlled to generate a first clock signal, the first clock signal including a plurality of first clock pulses;

[0028] The timing controller is controlled to obtain the refresh rate of the display panel and generate a control signal according to the refresh rate. The control signal is a first control signal when the refresh rate is greater than a preset value.

[0029] The level converter is controlled to process the first clock signal to generate a second clock signal when the control signal is the first control signal. The second clock signal includes a plurality of second clock pulses corresponding to a plurality of first clock pulses. The time periods of the second clock pulses overlap with the time periods of the first clock pulses, and the end time of the second clock pulses is later than the end time of the corresponding first clock pulse.

[0030] In some embodiments, the display device includes a gate driver integrated within or disposed independently of the display panel;

[0031] Wherein, after the step of controlling the level converter to process the first clock signal to generate the second clock signal when the control signal is the first control signal, the method includes:

[0032] The gate driver is controlled to generate a first gate signal based on the first clock signal when the refresh rate is less than or equal to the preset value, and to generate a second gate signal based on the second clock signal when the refresh rate is greater than the preset value.

[0033] In some embodiments, the level converter includes a level conversion module and a charge sharing module electrically connected to the level conversion module;

[0034] The step of controlling the level converter to generate the first clock signal includes:

[0035] The level conversion module is controlled to generate the first clock signal;

[0036] The step of controlling the level converter to process the first clock signal to generate a second clock signal when the control signal is the first control signal includes:

[0037] The charge sharing module is controlled to process the first clock signal to generate the second clock signal when the control signal is the first control signal.

[0038] This invention provides a display device and its driving method, and a display terminal. The display device includes a display panel, a timing controller, and a level converter. The timing controller generates a control signal based on the refresh rate of the display panel, and the control signal is a first control signal when the refresh rate is greater than a preset value. When the control signal is the first control signal, the level converter controls the processing of a first clock signal to generate a second clock signal. That is, the use of charge sharing technology is determined based on the refresh rate of the display panel, rather than using charge sharing technology to process the first clock signal to generate the second clock signal at all refresh rates. Charge sharing technology is only used at high refresh rates and is avoided at low refresh rates, which can reduce the risk of incorrect charging at low refresh rates. Attached Figure Description

[0039] Figure 1 This is a structural block diagram of a display device provided in an embodiment of the present invention.

[0040] Figure 2 The waveform diagrams are provided for some signals in the embodiments of the present invention.

[0041] Figure 3 This is a schematic diagram illustrating the enabled and disabled charge sharing technology provided in an embodiment of the present invention.

[0042] Figure 4 The power-refresh rate curves of the display device with and without charge sharing technology provided in the embodiments of the present invention.

[0043] Figure 5 The charging rate-refresh rate curves of the display device when the charge sharing technology is enabled and disabled, as provided in the embodiments of the present invention.

[0044] Figure 6 This is a structural block diagram of a level converter provided in an embodiment of the present invention.

[0045] Figure 7 A flowchart of a driving method for a display device provided in an embodiment of the present invention. Detailed Implementation

[0046] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0047] In the description of this invention, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0048] Furthermore, it should be noted that the accompanying drawings only provide structures and steps closely related to the present invention, omitting some details less relevant to the invention. The purpose is to simplify the drawings and make the inventive points immediately apparent, not to indicate that the actual device is identical to the one shown in the drawings. Figure 1 It is identical, but this is not a limitation of the actual device.

[0049] The present invention provides a display panel, which may include, but is not limited to, the following embodiments and combinations thereof.

[0050] In some embodiments, combined with Figure 1 and Figure 2 As shown, the display device 100 includes: a display panel 10; a timing controller 20, configured to acquire the refresh rate RS of the display panel 10 and generate a control signal con based on the refresh rate RS, wherein the control signal con is a first control signal when the refresh rate RS is greater than a preset value; and a level converter 30, electrically connected to the timing controller 20, configured to generate a first clock signal CK and further configured to process the first clock signal CK to generate a second clock signal CK' when the control signal con is the first control signal; wherein the first clock signal CK includes a plurality of first clock pulses, and the second clock signal CK' includes a plurality of second clock pulses corresponding to the plurality of first clock pulses, wherein the time period of the second clock pulse overlaps with the time period of the corresponding first clock pulse, and the end time of the second clock pulse is later than the end time of the corresponding first clock pulse.

[0051] The display panel 10 can be, but is not limited to, an organic self-emissive display panel, an inorganic self-emissive direct-view display panel, or a liquid crystal display panel. For example... Figure 1As shown, the arrangement of multiple sub-pixel P arrays in the display panel 10 is illustrated here as an example. For instance, they can be arranged in n rows and m columns (n ​​and m are both positive integers). Furthermore, the display panel 10 can include multiple gate lines (GL1 to GLn) and multiple data lines (DL1 to DLm). The display device 100 can also include a source driver 50 electrically connected to the multiple data lines and a gate driver 40 electrically connected to the multiple gate lines. The gate driver 40 can be a gate driving circuit located on the substrate of the display panel 10 or a chip disposed independently of the display panel 10.

[0052] Specifically, each gate line (any one of GL1 to GLn) is electrically connected to multiple sub-pixels P located in the corresponding row to output a corresponding gate signal Gate (including a gate active pulse for controlling the sub-pixel to turn on). Multiple rows of sub-pixels P are turned on sequentially under the control of multiple gate signals Gate (multiple gate active pulses). Each data line (any one of DL1 to DLm) is connected to multiple sub-pixels P located in the corresponding column to output a corresponding data signal data (each of which includes multiple data voltages of multiple sub-pixels P in the corresponding column). The multiple data signals data corresponding to multiple columns of sub-pixels P are matched so that when each row of sub-pixels P is turned on, the corresponding multiple data voltages are transmitted to the corresponding sub-pixels P respectively through multiple data lines (DL1 to DLm).

[0053] Specifically, combined Figure 1 and Figure 2 As shown, the first clock signal CK generated by the level converter 30 may include multiple sub-clock signals (at least including...) Figure 2 The sub-clock signals CK1 to CKn+1 in the gate driver 40 can be controlled by at least one sub-clock signal to generate a corresponding gate signal Gate. The multiple gate active pulses in the gate signal Gate can be formed according to the pulses in the corresponding sub-clock signal. That is, the multiple first clock pulses in the first clock signal CK acting on the gate driver 401 are used to determine the time period of the multiple gate active pulses in the multiple gate signals Gate.

[0054] like Figure 3As shown, in charge sharing technology, by shorting the two clock lines used to transmit the two signals (i.e., the transistors between the two clock lines are turned on) at the rising and falling edges of the first sub-clock signal CKx (e.g., sub-clock signal CK1) and the second sub-clock signal CKy (e.g., sub-clock signal CKn), which are inverse signals in the first clock signal CK, the potentials of the two clock lines can be combined (the combined potential CS is close to the average potential of the high-voltage signal VGH and the low-voltage signal VGL). Then, the chip can further provide higher or lower voltage signals to achieve the switching of the potentials of the first sub-clock signal CKx and the second sub-clock signal CKy from the potential of the high-voltage signal VGH to the potential of the low-voltage signal VGL, and from the potential of the low-voltage signal VGL to the potential of the high-voltage signal VGH, thereby reducing the power consumption of the chip.

[0055] like Figure 4 As shown, "ON" and "OFF" represent the power consumption-refresh rate curves of the chip when charge sharing technology is enabled and disabled, respectively. It can be observed that when charge sharing technology is enabled, the chip's power consumption (Poc) is lower at each refresh rate compared to when charge sharing technology is disabled. In other words, enabling charge sharing technology can reduce the chip's power consumption.

[0056] For ease of description, the first sub-clock signal CKx and the second sub-clock signal CKy are defined here to form the first shared sub-clock signal CKx' and the second shared sub-clock signal CKy' respectively through the above-mentioned charge-sharing technique. Observation Figure 3 It can be seen that, compared with the corresponding pulses in the first shared sub-clock signal CKx' and the second shared sub-clock signal CKy', the pulses start earlier and the pulses end later.

[0057] It is important to note that since the gate active pulse in the gate signal is formed based on the pulse in the corresponding sub-clock signal (both referred to as the aforementioned first clock pulse), and the pulses of the first shared sub-clock signal CKx' and the second shared sub-clock signal CKy' formed after charge sharing technology are delayed, the end of the gate active pulse in the generated gate signal Gate is also delayed. This causes the transistor in sub-pixel P to fail to turn off completely in time, resulting in leakage of data signals from subsequent rows into sub-pixel P in that row. The lower the refresh rate, the longer the leakage time (the leakage amount can be...). Figure 3 The "leakage rate" in the figure indicates that the normal required charging amount can be Figure 3 The higher the "charging rate" (in the image), the greater the risk of incorrect charging, and thus the greater the impact on image quality.

[0058] like Figure 5As shown, "ON" and "OFF" represent the chip's charging rate-refresh rate curves when charge sharing technology is enabled and disabled, respectively. It can be observed that, compared to disabling charge sharing technology, enabling charge sharing technology results in a lower power consumption charging rate at each refresh rate, meaning that enabling charge sharing technology reduces the charging rate. However, at high refresh rates, whether or not charge sharing technology is enabled has little impact on reducing the charging rate. Only at low refresh rates does enabling charge sharing technology cause a significant reduction in the charging rate.

[0059] Combination Figure 2 and Figure 3 As shown, in this embodiment, the second clock signal CK' includes multiple second clock pulses (with a first pulse width W') corresponding to multiple first clock pulses (with a first pulse width W), and the time periods of the second clock pulses overlap with the time periods of the corresponding first clock pulses, and the end time of the second clock pulses is later than the end time of the corresponding first clock pulses. That is, the second clock signal CK' can be understood as the first clock signal CK obtained through charge sharing. Specifically, the first clock signal CK includes a first sub-clock signal CKx (e.g., sub-clock signal CK1) and a second sub-clock signal CKy (e.g., sub-clock signal CKn), which are mutually inverted signals. By applying charge sharing technology to these two sub-clock signals, two sub-shared sub-clock signals can be obtained (sub-shared sub-clock signal CK1' corresponding to sub-clock signal CK1 and sub-shared sub-clock signal CKn' corresponding to sub-clock signal CKn). For each sub-shared sub-clock signal, at least the end time (i.e., the end time) of the second clock pulse is later than the end time of the corresponding first clock pulse.

[0060] Specifically, since the converter 30 processes the first clock signal CK to generate the second clock signal CK' only when the control signal con is the first control signal, otherwise it can be considered that the second clock signal CK' is not generated, the gate driver 40 can be considered to generate the first gate signal based on the first clock signal CK when the refresh rate is less than or equal to the preset value, and to generate the second gate signal based on the second clock signal CK' when the refresh rate is greater than the preset value. As discussed above, the gate active pulse in the first gate signal is generated based on the first sub-clock signal CKx and the second sub-clock signal CKy, which are inverted signals in the first clock signal CK, and the gate active pulse in the second gate signal is generated based on the first shared sub-clock signal CKx' and the second shared sub-clock signal CKy', which are inverted signals in the second clock signal CK'.

[0061] Understandably, in this embodiment, based on the display device 100's function of generating a second clock signal CK' from a first clock signal CK, the refresh rate RS of the display panel 10 is obtained by the timing controller 20 and a control signal con is generated accordingly. The control signal con is the first control signal when the refresh rate RS is greater than a preset value. The level converter 30 is also used to process the first clock signal CK to generate the second clock signal CK' when the control signal con is the first control signal (i.e., when the refresh rate RS is large). In other words, whether to use charge sharing technology in this embodiment is determined by the refresh rate RS of the display panel 10, rather than using charge sharing technology to process the first clock signal CK to generate the second clock signal CK' at all refresh rates. Charge sharing technology is only enabled when the refresh rate RS is large, and is not enabled when the refresh rate RS is small. This avoids the problem of poor image quality caused by the high risk of incorrect charging at low refresh rates due to the use of charge sharing technology.

[0062] In some embodiments, the timing controller 20 is used to control the level converter 30 to process the first clock signal CK to generate the second clock signal CK' via the control signal con when the refresh rate RS is greater than a preset value (e.g., but not limited to 144 Hz). As discussed above, if charge sharing technology is used to process the first clock signal CK at low refresh rates, the generated second clock signal CK' will have a higher risk of incorrect charging. Therefore, in this embodiment, the timing controller 20 only controls the level converter 30 to process the first clock signal CK to generate the second clock signal CK' when the refresh rate RS is greater than the preset value. Figure 1 , Figure 2 and Figure 5 As shown, due to the high refresh rate and short leakage time, the risk of incorrect charging is small. Even if the charge sharing technology is used to generate the second clock signal CK', it will not cause a significant reduction in the charging rate. On the contrary, it can reduce the power consumption of the chip.

[0063] Of course, when the refresh rate RS is less than or equal to a preset value, the control signal con generated by the timing controller 20 can control the level converter 30 not to process the first clock signal CK to generate the second clock signal CK', but instead directly generate the gate signal Gate through the first clock signal CK, in order to avoid... Figure 5 The problem shown is that the charging rate is severely insufficient due to the high refresh rate.

[0064] In some embodiments, combined with Figure 1 , Figure 2 and Figure 6As shown, the level converter 30 includes: a level conversion module 301, used to generate the first clock signal CK; and a charge sharing module 302, electrically connected to the level conversion module 301, used to determine whether to process the first clock signal CK to generate the second clock signal CK' according to the control signal con.

[0065] Specifically, in combination Figure 1 and Figure 6 As shown, the display device 100 may further include a voltage generator 60, which is used to provide a high voltage signal VGH and a low voltage signal VGL to the level converter 30. The timing controller 20 is also used to provide a clock source signal CLK to the level converter 30. The level conversion module 301 can generate a first clock signal CK according to the high voltage signal VGH, the low voltage signal VGL and the clock source signal CLK. The high and low potentials of the multiple sub-clock signals (at least including sub-clock signals CK1 to sub-clock signals CKn+1) in the first clock signal CK can be the same as the potential of the high voltage signal VGH and the potential of the low voltage signal VGL, respectively. The frequency of the multiple sub-clock signals can be equal to the frequency of the clock source signal CLK. There is a phase difference between each pair of the multiple sub-clock signals.

[0066] Furthermore, the charge sharing module 302 can determine whether to process the first clock signal CK to generate the second clock signal CK' based on the control signal con. When the second clock signal CK' needs to be generated, the charge sharing module 302 performs charge sharing processing on two of the multiple sub-clock signals that are inverse signals. That is, it short-circuits the line used to transmit the first sub-clock signal CKx (e.g., sub-clock signal CK1) and the line used to transmit the second sub-clock signal CKy (e.g., sub-clock signal CKn), thereby generating the corresponding two sub-clock signals CK1' and CKn' (collectively referred to as the second clock signal CK'). When the second clock signal CK' does not need to be generated, the charge sharing module 302 directly outputs the first clock signal CK.

[0067] In some embodiments, combined with Figure 2 and Figure 6As shown, the charge sharing module 302 includes: a first input module 3021 for receiving the first sub-clock signal CKx (e.g., sub-clock signal CK1), the first sub-clock signal CKx including a plurality of first sub-clock pulses (e.g., pulse pc1 of sub-clock signal CK1); a second input module 3022 for receiving the second sub-clock signal CKy (e.g., sub-clock signal CKn), the second sub-clock signal CKy including a plurality of second sub-clock pulses (e.g., pulse pc1 of sub-clock signal CK1) corresponding to the plurality of first sub-clock pulses; a first output module 3023 electrically connected to the first input module 3021; ​​a second output module 3024 electrically connected to the second input module 3022; and a first switch module 3025 electrically connected between the first input module 3021 and the second input module 3022; wherein, the control signal con is used to control whether the first switch module 3025 is turned on at the end time of the first sub-clock pulse (e.g., pulse pc1 of sub-clock signal CK1). That is, the first switch module 3025 is used to control the first output module 3023 to output the first sub-clock signal CKx and control the second output module 3024 to output the second sub-clock signal CKy according to the control signal con, or to control the first output module 3023 to output the first shared sub-clock signal CKx' and control the second output module 3024 to output the second shared sub-clock signal CKy'.

[0068] As discussed above, since the first switch module 3025 is electrically connected between the first input module 3021 and the second input module 3022, its conduction status determines whether the first sub-clock signal CKx and the second sub-clock signal CKy share charge. When the first switch module 3025 is on, the first sub-clock signal CKx and the second sub-clock signal CKy share charge. The first shared sub-clock signal CKx' output by the first output module 3023 and the second shared sub-clock signal CKy' output by the second output module 3024 are the same, and their potentials are equal to the average of the potentials of the high-voltage signal VGH and the low-voltage signal VGL. When the first switch module 3025 is off, the first sub-clock signal CKx and the second sub-clock signal CKy do not share charge. It can be considered that at this time, the first output module 3023 directly outputs the first sub-clock signal CKx, and the second output module 3024 directly outputs the second sub-clock signal CKy.

[0069] In some embodiments, combined with Figure 2 and Figure 6As shown, the charge sharing module 302 further includes: a second switch module 3026 electrically connected between the first input module 3021 and the first output module 3023; and a third switch module 3027 electrically connected between the second input module 3022 and the second output module 3024. The control signal con is used to control the second switch module 3026 and the third switch module 3027 to be off when the first switch module 3025 is on, and to be on when the first switch module 3025 is off. That is, the second switch module 3026 controls whether the first input module 3021 transmits the first sub-clock signal CKx to the first output module 3023 according to the control signal con; the third switch module 3027 controls whether the second input module 3022 transmits the second sub-clock signal CKy to the second output module 3024 according to the control signal con.

[0070] Understandably, in this embodiment, the second switch module 3026 and the third switch module 3027 are configured. When the first switch module 3025 is turned on, the first sub-clock signal CKx and the second sub-clock signal CKy share charge. At this time, by controlling the second switch module 3026 and the third switch module 3027 to be turned off, it is not only beneficial to perform the above-mentioned charge sharing to adjust the voltage output by the first output module 3023 and the second output module 3024 to generate the first shared sub-clock signal CKx' and the second shared sub-clock signal CKy', but also to stop the driving level converter 30 from being driven by the timing controller 20 and the voltage generator 60, thereby reducing the power consumption of the chip.

[0071] Of course, when the first switch module 3025 is off, the first sub-clock signal CKx and the second sub-clock signal CKy do not share charge. At this time, by controlling the second switch module 3026 and the third switch module 3027 to be turned on, it is not only beneficial to carry out the above-mentioned charge sharing to adjust the voltage output by the first output module 3023 and the second output module 3024, but the level converter 30 continues to be driven by the timing controller 20 and the voltage generator 60. The first output module 3023 directly outputs the first sub-clock signal CKx, and the second output module 3024 directly outputs the second sub-clock signal CKy.

[0072] In some embodiments, such as Figure 1 As shown, the timing controller 20 is used to obtain the frame blanking duration of the previous frame and to determine the corresponding refresh rate RS based on the frame blanking duration; or, the timing controller 20 is used to determine the corresponding refresh rate RS based on the frame start signal.

[0073] As discussed above, the data signal Data includes multiple data voltages of multiple sub-pixels P in the corresponding column. The duration of the interval between two adjacent data voltages within a frame is called the row blanking duration. In two adjacent frames, the duration of the interval between the data voltage of the last row of sub-pixels P in the earlier frame and the data voltage of the first row of sub-pixels P in the later frame is called the frame blanking duration. The duration of each frame can be composed of the scan duration and the frame blanking duration. When the scan duration is constant, it can be considered that the longer the frame blanking duration, the lower the refresh rate RS, and vice versa. Therefore, the current refresh rate RS can also be determined based on the frame blanking duration.

[0074] Among them, such as Figure 2 As shown, the frame start signal can also be applied to the gate driver 40 to drive the multi-stage gate driving unit 401 to generate multiple gate signals Gate step by step. The pulse in the frame start signal triggers one of the gate driving units 401 to generate the corresponding gate effective pulse in the gate signal Gate. Subsequently, the gate effective pulse drives other stage gate driving units 401 step by step to perform a frame scan. It can be considered that the sum of the duration between two adjacent pulses in the frame start signal and the pulse width of the pulse is equal to the duration of a frame. Therefore, the corresponding refresh rate RS can also be determined according to the frame start signal.

[0075] The present invention also provides a display terminal, including a display device as described above and a motherboard electrically connected to the display device. The motherboard is used to transmit image signals to the display device to control the display panel to display an image. Specifically, the motherboard can receive image information and control information input from the front end of the display terminal and convert them into image signals and control signals acting on the display device. The gate signal Gate can be generated based on the control signal, and the data signal Data can be considered to be generated jointly by the image signal and the control signal Data.

[0076] The present invention also provides a driving method for a display device, wherein the display device 100 includes the aforementioned display panel 10, a timing controller 20, and a level converter 30 electrically connected to the timing controller 20, such as... Figure 7 As shown, the driving method of the display device includes, but is not limited to, the following steps.

[0077] S1, control the level converter to generate a first clock signal, the first clock signal including a plurality of first clock pulses.

[0078] As discussed above, regardless of the refresh rate RS, the level converter 30 needs to generate the first clock signal CK based on the clock source signal CLK provided by the timing controller 20 and the high-voltage signal VGH and low-voltage signal VGL provided by the voltage generator 60. Figure 2 As shown, the first clock signal CK includes multiple sub-clock signals (at least including...) Figure 2 The sub-clock signals CK1 to CKn+1, and the multiple pulses pc1 in sub-clock signal CK1, multiple pulses pc2 in sub-clock signal CK2, multiple pulses pcn in sub-clock signal CKn, and multiple pulses pcn+1 in sub-clock signal CKn+1 are all referred to as the first clock pulse.

[0079] S2, control the timing controller to obtain the refresh rate of the display panel, and generate a control signal according to the refresh rate. The control signal is a first control signal when the refresh rate is greater than a preset value.

[0080] That is, the control signal con generated by the timing controller 20 based on the refresh rate RS of the display panel 10 can contain the refresh rate RS information of the display panel 10. Specifically, the control signal con is the first control signal when the refresh rate is greater than the preset value, and the second control signal when the refresh rate is less than or equal to the preset value.

[0081] S3, control the level converter to process the first clock signal to generate a second clock signal when the control signal is the first control signal. The second clock signal includes a plurality of second clock pulses corresponding to a plurality of first clock pulses. The time periods of the second clock pulses overlap with the time periods of the first clock pulses, and the end time of the second clock pulses is later than the end time of the corresponding first clock pulses.

[0082] As discussed above, the second clock signal CK' is obtained by the first clock signal CK through charge sharing technology. In this embodiment, whether to process the first clock signal CK to generate the second clock signal CK' is determined by the control signal con, that is, by the refresh rate RS of the display panel 10.

[0083] Specifically, when the control signal con is the first control signal, it indicates that the refresh rate is relatively high. In this case, the first clock signal CK needs to be processed to generate the second clock signal CK'. When the control signal con is the second control signal, it indicates that the refresh rate is relatively low. In this case, it is not necessary to process the first clock signal CK to generate the second clock signal CK'.

[0084] In some embodiments, after step S3, the following steps are included but not limited to:

[0085] S4, control the gate driver to generate a first gate signal according to the first clock signal when the refresh rate is less than or equal to the preset value, and to generate a second gate signal according to the second clock signal when the refresh rate is greater than the preset value.

[0086] As discussed above, in this embodiment, the control signal con generated by the timing controller 20 controls the level converter 30 to process the first clock signal CK to generate the second clock signal CK' only when the refresh rate RS is greater than a preset value. Figure 1 , Figure 2 and Figure 5 As shown, at this time, due to the high refresh rate and short leakage time, the risk of incorrect charging is small. Even if the charge sharing technology is used to generate the second clock signal CK', and the second gate signal is further generated through the second clock signal CK' to control the opening status of the multi-row sub-pixels P in the display panel 10, the charging rate will not be significantly reduced. On the contrary, the power consumption of the chip can be reduced.

[0087] In some embodiments, the level converter 30 includes a level conversion module 301 and a charge sharing module 302 electrically connected to the level conversion module 301; step S1 includes: controlling the level conversion module to generate the first clock signal; step S3 includes: controlling the charge sharing module to process the first clock signal to generate the second clock signal when the control signal is the first control signal.

[0088] That is, the level conversion module 301 can generate a first clock signal CK based on the high voltage signal VGH, the low voltage signal VGL, and the clock source signal CLK. The charge sharing module 302 can determine whether to process the first clock signal CK to generate a second clock signal CK' based on the control signal con. When the second clock signal CK' needs to be generated, the charge sharing module 302 performs charge sharing processing on two of the multiple sub-clock signals that are inverse signals. That is, it short-circuits the line used to transmit the first sub-clock signal CKx (e.g., sub-clock signal CK1) and the line used to transmit the second sub-clock signal CKy (e.g., sub-clock signal CKn), thereby generating the corresponding two sub-clock signals CK1' and CKn' (collectively referred to as the second clock signal CK'). When the second clock signal CK' does not need to be generated, the charge sharing module 302 directly outputs the first clock signal CK.

[0089] The display device and its driving method, as well as the structure of the display terminal provided in the embodiments of the present invention, have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core ideas of the present invention. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display device, characterized in that, include: Display panel; A timing controller is used to generate a control signal based on the refresh rate of the display panel, wherein the control signal is a first control signal when the refresh rate is greater than a preset value; A level converter, electrically connected to the timing controller, is used to generate a first clock signal and to process the first clock signal to generate a second clock signal when the control signal is the first control signal. The level converter includes a level conversion module for generating the first clock signal and a charge sharing module for determining whether to process the first clock signal to generate the second clock signal according to the control signal. The first clock signal includes a plurality of first clock pulses, and the second clock signal includes a plurality of second clock pulses corresponding to the plurality of first clock pulses. The time period of the second clock pulse overlaps with the time period of the corresponding first clock pulse, and the end time of the second clock pulse is later than the end time of the corresponding first clock pulse. The first clock signal includes a first sub-clock signal and a second sub-clock signal that are inverted signals. The second clock signal includes a first shared sub-clock signal corresponding to the first sub-clock signal and a second shared sub-clock signal corresponding to the second sub-clock signal. The first shared sub-clock signal and the second shared sub-clock signal are inverted signals.

2. The display device as claimed in claim 1, characterized in that, include: A gate driver, integrated within the display panel or disposed independently of the display panel, is configured to generate a first gate signal based on a first clock signal when the refresh rate is less than or equal to the preset value, and to generate a second gate signal based on a second clock signal when the refresh rate is greater than the preset value.

3. The display device as claimed in claim 1, characterized in that, The charge sharing module includes a first input module, a second input module, a first output module, a second output module, and a first switch module. The first input module is used to receive the first sub-clock signal, which includes a plurality of first sub-clock pulses; The second input module is used to receive the second sub-clock signal, the second sub-clock signal including a plurality of second sub-clock pulses corresponding to a plurality of first sub-clock pulses; The first switch module is used to control the first output module to output the first sub-clock signal and control the second output module to output the second sub-clock signal according to the control signal, or to control the first output module to output the first shared sub-clock signal and control the second output module to output the second shared sub-clock signal.

4. The display device as claimed in claim 3, characterized in that, The charge sharing module also includes: The second switch module is used to control whether the first input module transmits the first sub-clock signal to the first output module according to the control signal. The third switch module is used to control whether the second input module transmits the second sub-clock signal to the second output module according to the control signal.

5. The display device as claimed in claim 1, characterized in that, The timing controller is used to obtain the frame blanking duration of the previous frame and to calculate the corresponding refresh rate based on the frame blanking duration. Alternatively, the timing controller is used to calculate the corresponding refresh rate based on the frame start signal.

6. A display terminal, characterized in that, The device includes a display device as described in any one of claims 1 to 5 and a motherboard electrically connected to the display device, the motherboard being used to transmit image signals to the display device to control the display panel to display an image.

7. A driving method for a display device, characterized in that, The display device includes a display panel, a timing controller, and a level converter electrically connected to the timing controller. The level converter includes a level conversion module for generating a first clock signal and a charge sharing module for determining whether to process the first clock signal to generate a second clock signal based on the control signal. The driving method of the display device includes: The level converter is controlled to generate a first clock signal, the first clock signal including a plurality of first clock pulses; The timing controller is controlled to obtain the refresh rate of the display panel and generate a control signal according to the refresh rate. The control signal is a first control signal when the refresh rate is greater than a preset value. The level converter is controlled to process the first clock signal to generate a second clock signal when the control signal is the first control signal. The second clock signal includes a plurality of second clock pulses corresponding to a plurality of first clock pulses. The time periods of the second clock pulses overlap with the time periods of the first clock pulses, and the end time of the second clock pulses is later than the end time of the corresponding first clock pulse. The first clock signal includes a first sub-clock signal and a second sub-clock signal that are inverted signals. The second clock signal includes a first shared sub-clock signal corresponding to the first sub-clock signal and a second shared sub-clock signal corresponding to the second sub-clock signal. The first shared sub-clock signal and the second shared sub-clock signal are inverted signals.

8. The driving method for the display device as described in claim 7, characterized in that, The display device includes a gate driver that is integrated into the display panel or disposed independently of the display panel; Wherein, after the step of controlling the level converter to process the first clock signal to generate the second clock signal when the control signal is the first control signal, the method includes: The gate driver is controlled to generate a first gate signal based on the first clock signal when the refresh rate is less than or equal to the preset value, and to generate a second gate signal based on the second clock signal when the refresh rate is greater than the preset value.

9. The driving method for the display device as described in claim 7 or 8, characterized in that, The step of controlling the level converter to generate the first clock signal includes: The level conversion module is controlled to generate the first clock signal; The step of controlling the level converter to process the first clock signal to generate a second clock signal when the control signal is the first control signal includes: The charge sharing module is controlled to process the first clock signal to generate the second clock signal when the control signal is the first control signal.

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