Nonvolatile memory and rewrite control method thereof

Abstract

The invention relates to a non-volatile memory and a rewrite control method thereof. The invention provides a nonvolatile memory system capable of suppressing an overstress on a normal cell and ensuring a data retention margin of the normal cell. In one embodiment of the non-volatile memory system, it determines whether error correction is possible for addresses determined to fail in an erase verification process, counts the number of addresses determined to be error correctable, and if such number of addresses is less than or equal to a predetermined number, the erase process is determined to be normal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2023-122335 filed on July 27, 2023 (including specification, drawings and abstract) is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a nonvolatile memory system and a rewrite control method for the nonvolatile memory. Background Art

[0004] In the rewriting process (i.e., the erasing process and the writing process) of the nonvolatile memory, a verification process is performed to determine whether it has been correctly rewritten. In a normal verification process, if all bits to be rewritten have been correctly rewritten, it is determined to be passed, and if there is a rewriting error in even one bit, it is determined to be failed. Then, the rewriting process and the verification process are repeated until it is determined to be passed, and if it is determined to be failed even after repeating a certain number of times, it is finally determined to be failed.

[0005] The disclosed technologies are listed below.

[0006] [Patent Document 1] Japanese Laid-Open Patent Application Publication No. 2006-048783

[0007] On the other hand, in addition to the data unit, a nonvolatile memory is also known that is equipped with a unit for error correction code (ECC: Error Correction Code) to detect and correct error bits. Patent document 1 discloses a technology in which, even if it is determined to be a failure in the verification process, if the number of error bits is equal to or less than the number of correctable error bits n (n is a natural number), it is finally determined to be passed and allowed. With such a configuration, the failure rate of the nonvolatile memory can be reduced. Summary of the invention

[0008] The inventors have found the following problems with the technology disclosed in Patent Document 1. For example, Figure 6 In the method disclosed in, after the rewriting process and the verification process are repeated for the maximum number of times, it is determined whether the number of bits that can be corrected is n or less. During the erasing process, for example, if there are abnormal cells with a smaller on-current that deviates from the distribution of normal cells, the erasing process will be repeated due to these abnormal cells. As a result, there is a problem of applying excessive stress to normal cells. As a comparative example, the details of the occurrence mechanism of this problem will be explained in the specification.

[0009] On the other hand, in Patent Document 1 Figure 7In the method disclosed in, for example, each time a rewrite process and a verification process are performed, it is determined whether the number of bits that can be corrected is n or less. During the erasure process, for example, if there is no abnormal cell, there is a possibility that error correction can tolerate normal cells whose on-current is less than the threshold level of the erase verification. There is a risk that normal cells with on-currents that do not reach the threshold level of the erase verification may be allowed through error correction. In this case, there is a problem of insufficient data retention margin and shortened data retention time (ie, lifespan). As a comparative example, the details of the occurrence mechanism of this problem will be explained in the specification. Other problems and novel features will become clear through the description and drawings of this specification.

[0010] In a nonvolatile memory system according to one embodiment, a controller determines whether addresses determined to have failed during an erase verification process are correctable, counts the number of addresses determined to be correctable, and if the number of such addresses is less than or equal to a predetermined number, the erase process is determined to be normal.

[0011] In a rewrite control method for a nonvolatile memory according to one embodiment, it is determined whether addresses determined to have failed during an erase verification process are correctable, the number of addresses determined to be correctable is counted, and if the number of such addresses is less than or equal to a predetermined number, the erase process is determined to be normal.

[0012] According to one embodiment, a nonvolatile memory system that can suppress excessive stress on normal cells and ensure a data retention margin of the normal cells can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a block diagram showing a configuration of a nonvolatile memory system according to a first embodiment;

[0014] Figure 2 is a flowchart showing a method for controlling rewriting of a nonvolatile memory according to a first embodiment;

[0015] Figure 3 is a flowchart showing a method for controlling rewriting of a nonvolatile memory according to a first comparative example;

[0016] Figure 4 is a graph for explaining a problem in a method for controlling rewriting of a nonvolatile memory according to a first comparative example;

[0017] Figure 5 is a flowchart showing a method for controlling rewriting of a nonvolatile memory according to a second comparative example;

[0018] Figure 6is a graph for explaining a problem in a method for controlling rewriting of a nonvolatile memory according to a second comparative example;

[0019] Figure 7 is a graph for explaining the effect of the method for controlling rewriting of a nonvolatile memory according to the first embodiment;

[0020] Figure 8 is a flowchart showing a method for controlling rewriting of a nonvolatile memory according to a second embodiment; and

[0021] Fig. 9 It is schematically shown by Figure 8 A diagram showing the transition of data written into a data unit during the writing process shown. DETAILED DESCRIPTION

[0022] Hereinafter, the specific embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. However, the present disclosure is not limited to the following embodiments. For the purpose of explanation, the following description and the accompanying drawings are appropriately simplified. In addition, in each of the accompanying drawings, the same elements are given the same reference numerals, and redundant descriptions are omitted when necessary.

[0023] (First embodiment)

[0024] <Configuration of Nonvolatile Memory System>

[0025] First, refer to Figure 1 , a nonvolatile memory system according to a first embodiment will be described. Figure 1 1 is a block diagram showing the configuration of the nonvolatile memory system according to the first embodiment. Figure 1 As shown, the nonvolatile memory system according to the first embodiment includes a nonvolatile memory 10, a controller 20, and a CPU 30. In the nonvolatile memory system according to the present embodiment, the CPU 30 is not essential.

[0026] The nonvolatile memory 10 is, for example, a flash memory, and includes a data unit and an error correction code (ECC: Error Correction Code) unit for each address. By providing the ECC unit, error correction can be performed for each address. The number n (n is a natural number) of error-correctable bits is appropriately determined.

[0027] For example, to achieve 1-bit error correction per address, a 6-bit ECC unit is added to a 1-address (32-bit) data unit. To achieve 2-bit error correction per address, a 12-bit ECC unit is added to the data unit.

[0028] The controller 20 performs a rewrite process, i.e., an erase process and a write process, on the nonvolatile memory 10. For example, when the nonvolatile memory 10 is a flash memory, in the erase process, all data cells are turned on and all data cell values ​​are set to "1". The write process is performed after the erase process. In other words, in order to perform the write process, the erase process must be performed first. In the write process, based on the write data, a predetermined data cell is switched from on to off, and the value of the data cell is switched from "1" to "0".

[0029] In the nonvolatile memory 10, the erasing process is performed in batches on one block or a plurality of blocks consisting of a plurality of addresses. For example, 256 addresses (ie, 1KB) of 1 address (32 bits) are set as 1 block. However, the capacity of one block is appropriately determined.

[0030] Figure 1 The controller 20 shown includes an ECC encoder 21 and an ECC decoder 22 . Figure 1 1 shows the input and output of signals in the writing process. The ECC encoder 21 adds error correction data to the write data wd1 received from the CPU 30, and generates write data wd2. The controller 20 writes the write data wd2 with the added error correction data to the nonvolatile memory 10. The ECC decoder 22 decodes the read data rd1 read from the nonvolatile memory 10, and corrects the error of the read data rd1. Then, the ECC decoder 22 outputs the error-corrected read data rd2 to the CPU 30.

[0031] Although not shown, in the case of the erasing process, the controller 20 turns on all data cells of the erasing target block in the nonvolatile memory 10 and sets all data cell values ​​to "1". Then, the ECC decoder 22 decodes the data read from the nonvolatile memory 10 after the erasing process and corrects errors of the data.

[0032] The controller 20 performs an erase verification process that determines whether the erase process has passed or failed for each address. For example, when the nonvolatile memory 10 is a flash memory, the controller 20 reads data from the nonvolatile memory 10 after performing the erase process and determines whether all data unit values ​​of each address are "1".

[0033] When all data unit values ​​are "1", the controller 20 determines a pass in the erasure verification process. That is, the controller 20 determines that the erasure process is normal. On the other hand, if not all data unit values ​​are "1" but include "0", the controller 20 determines a fail in the erasure verification process.

[0034] In addition, the controller 20 determines whether the address determined to fail in the erasure verification process can be corrected. For example, the ECC decoder 22 performs an erasure verification process on the error-corrected data. If it passes, it is determined that the error can be corrected, and if it fails, it is determined that the error cannot be corrected.

[0035] Alternatively, the number of error bits included in the data read from the nonvolatile memory 10 after the erase process may be counted, and if the number of error bits is less than or equal to the number n of correctable error bits, it may be determined that error correction is possible. On the other hand, if the number of error bits exceeds the number n of correctable error bits, it may be determined that error correction is impossible. That is, the controller 20 does not have to have the ECC decoder 22 inside, and the ECC decoder 22 may be provided outside the controller 20.

[0036] Then, the controller 20 counts the number of addresses determined to be error-correctable, and if the number of such addresses is less than or equal to a predetermined number m (where m is a natural number), the controller 20 determines that the erasure process is normal. Here, for example, the number m is appropriately determined based on the occurrence rate of abnormal cells with smaller on-currents that deviate from the distribution of normal cells. On the other hand, if the number of addresses exceeds the predetermined number m, the controller 20 determines that the erasure process is abnormal, and performs the erasure process and the erasure verification process again. The number of retries of the erasure process is predetermined.

[0037] Note that the controller 20 may be configured in terms of hardware by a computer including a processor, a memory, and other circuits, and may be realized in terms of software by a program loaded into the memory.

[0038] As described above, in the nonvolatile memory system according to the present embodiment, the controller 20 determines whether error correction is possible for an address determined to have failed in the erase verification process. That is, by determining whether error correction can be performed without repeating the erase process, the erase time can be shortened and excessive stress on normal cells due to repeated erase processes can be suppressed.

[0039] Furthermore, in the nonvolatile memory system according to the present embodiment, the controller 20 counts the number of addresses determined to be error-correctable, and if the number of such addresses is less than or equal to a predetermined number, the controller 20 determines that the erasure process is normal. That is, only when the cause of failure determination in the erasure verification process is due to an abnormal cell, the number of error-correctable addresses is limited to allow error correction. Therefore, error correction of normal cells whose on-current does not reach the threshold level of the erasure verification is suppressed, and the data retention margin can be ensured.

[0040] <Nonvolatile Memory Rewrite Control Method>

[0041] Next, refer to Figure 2 , a description will be given of a nonvolatile memory rewrite control method according to a first embodiment. Figure 2 is a flowchart showing a nonvolatile memory rewrite control method according to the first embodiment. Figure 2 A control method for the erase process and the erase verification process is shown. Figure 2 When appropriate, reference will be made to Figure 1 .

[0042] First, if Figure 2 As shown, the controller 20 performs an erasing process (step ST1) on the nonvolatile memory 10. The erasing process (step ST1) is performed on one block or a plurality of blocks consisting of a plurality of addresses. For example, if the nonvolatile memory 10 is a flash memory, in the erasing process (step ST1), all data cells of the erasing target address in the nonvolatile memory 10 are turned on, and the values ​​of all data cells are set to "1".

[0043] Next, if Figure 2 As shown, the controller 20 performs an erase verification process, which determines whether the erase process (step ST1) is passed or failed (step ST2) for each address. For example, the controller 20 reads data from the nonvolatile memory 10 on which the erase process has been performed, and determines whether the values ​​of all data cells of each address are "1".

[0044] If the values ​​of all data units are "1", the controller 20 determines that the erasure verification process is passed ("passed" in step ST2). Figure 2 As shown, if the target address is not the final address, it changes to the next address, returns to step ST2, and performs the erasure verification process for the next address. If the target address is the final address, since the erasure process of all addresses is normal, the controller 20 finally determines that the erasure process is normal and ends the erasure process (by ending).

[0045] On the other hand, if the values ​​of all data cells are not "1" and the values ​​of the data cells include "0", the controller 20 determines that the erasure verification process has failed ("failure" of step ST2). Figure 2 As shown, it is determined whether error correction is possible (step ST3).

[0046] like Figure 2As shown, if it is determined that error correction is impossible ("No" in step ST3), if the number of retries of the erasing process is not the maximum value, it returns to step ST1 and performs the erasing process again. If the number of retries of the erasing process is the maximum, the controller 20 finally determines that the erasing process is abnormal and ends the erasing process (failure end). Failure end means that a failure has occurred in the nonvolatile memory 10.

[0047] On the other hand, Figure 2 As shown, if it is determined that error correction is possible ("Yes" in step ST3), the number of addresses is counted (step ST4). That is, the number of addresses determined to be error correctable in step ST3 is counted.

[0048] Next, if Figure 2 As shown, it is determined whether the number of addresses counted in step ST4 is equal to or less than the predetermined number m (step ST5). If the number of addresses is equal to or less than the predetermined number m ("Yes" in step ST5), if the target address is not the final address, it is changed to the next address, returns to step ST2, and performs the erasure verification process for the next address. If the target address is the final address, the controller 20 finally determines that the erasure process is normal and ends the erasure process (by ending).

[0049] On the other hand, if the number of addresses exceeds the predetermined number m ("No" in step ST5), if the number of retries of the erasing process is not the maximum value, the process returns to step ST1 and the erasing process is performed again. If the number of retries of the erasing process is the maximum, the controller 20 finally determines that the erasing process is abnormal and ends the erasing process (failure end).

[0050] <Nonvolatile Memory Rewrite Control Method According to First Comparative Example>

[0051] Here, reference Figure 3 , a nonvolatile memory rewrite control method according to a first comparative example will be described. Figure 3 1 is a flowchart showing a nonvolatile memory rewrite control method according to a first comparative example. The erasure process (step ST1) and the erasure verification process (step ST2) are Figure 2 The same, so the description will be omitted.

[0052] like Figure 3 As shown, in the case where the judgment in the erasure verification process passes ("pass" of step ST2), if the target address is not the final address, the process moves to the next address and returns to step ST2, and the erasure verification process is performed for the next address. If the target address is the final address, since the erasure process of all addresses is normal, the controller 20 finally determines that the erasure process is normal and ends the erasure process (pass end).

[0053] On the other hand, Figure 3 As shown, in the case of a failure judgment in the erasure verification process ("failure" of step ST2), if the number of retries of the erasure process is not the maximum value, the process returns to step ST1 and performs the erasure process again. If the number of retries of the erasure process is the maximum value, it is determined whether error correction is possible (step ST3).

[0054] like Figure 3 As shown, if it is determined that error correction is possible ("Yes" in step ST3), if the target address is not the final address, the process moves to the next address and returns to step ST2, and the erasure verification process is performed for the next address. If the target address is the final address, since the erasure process of all addresses is normal, the controller 20 finally determines that the erasure process is normal and ends the erasure process (by ending).

[0055] On the other hand, Figure 3 As shown, if it is determined that error correction is impossible ("No" at step ST3), the controller 20 finally determines that the erasing process is abnormal and ends the erasing process (failure end).

[0056] <Problems in Rewrite Control Method of Nonvolatile Memory According to First Comparative Example>

[0057] Next, refer to Figure 4 , problems in the rewrite control method of the nonvolatile memory according to the first comparative example will be explained. Figure 4 is a graph for explaining a problem in a rewrite control method of a nonvolatile memory according to a first comparative example. Figure 4 The horizontal axis represents the number of cells, and the vertical axis represents the on-current Ion of the cell.

[0058] Figure 4 FIG. 4 shows a case where there are abnormal cells having a smaller on-current Ion that deviates from the distribution of normal cells. Figure 4 In the example shown, since the abnormal cell has not exceeded the threshold level of the erase verification, Figure 3 The erasure verification process shown is judged as a failure ("failure" in step ST2), and the erasure process (step ST1) is repeated until the maximum number of retries is reached.

[0059] Therefore, in the rewrite control method of the nonvolatile memory according to the first comparative example, the erasure time increases until the pass judgment by error correction. Figure 4As shown, before the pass judgment by error correction, the distribution of normal cells is excessively shifted toward the side where the on-current Ion increases. Therefore, in the rewrite control method of the nonvolatile memory according to the first comparative example, there is a problem of applying excessive stress to the normal cells.

[0060] <Rewrite Control Method of Nonvolatile Memory According to Second Comparative Example>

[0061] Next, refer to Figure 5 , a rewrite control method of a nonvolatile memory according to a second comparative example will be explained. Figure 5 1 is a flowchart showing a rewrite control method of a nonvolatile memory according to a second comparative example. Figure 2 The same, therefore the description is omitted.

[0062] like Figure 5 As shown, in the case where the judgment in the erasure verification process passes ("pass" of step ST2), if the target address is not the final address, the process moves to the next address and returns to step ST2, and the erasure verification process is performed for the next address. If the target address is the final address, since the erasure process of all addresses is normal, the controller 20 finally determines that the erasure process is normal and ends the erasure process (pass end).

[0063] On the other hand, Figure 5 As shown, in the case of a failure determination in the erasure verification process ("failure" in step ST2), it is immediately determined whether error correction is possible (step ST3). Figure 5 As shown, if it is determined that error correction is possible ("Yes" in step ST3), if the target address is not the final address, the process moves to the next address and returns to step ST2, and the erasure verification process is performed for the next address. If the target address is the final address, since the erasure process of all addresses is normal, the controller 20 finally determines that the erasure process is normal and ends the erasure process (by ending).

[0064] On the other hand, Figure 5 As shown, if it is determined that error correction is impossible ("No" in step ST3), if the number of retries of the erasing process is not the maximum value, the process returns to step ST1 and the erasing process is performed again. If the number of retries of the erasing process is the maximum value, the controller 20 finally determines that the erasing process is abnormal and ends the erasing process (failure end).

[0065] <Problems in Rewrite Control Method of Nonvolatile Memory According to Second Comparative Example>

[0066] Next, refer to Figure 6, problems in the rewrite control method of the nonvolatile memory according to the second comparative example will be explained. Figure 6 is a graph for explaining a problem in a rewrite control method of a nonvolatile memory according to a second comparative example. Figure 6 The horizontal axis represents the number of batteries, and the vertical axis represents the energized ions of the batteries.

[0067] Figure 6 FIG. 4 shows a case where there is no abnormal cell and the on-current Ion of the normal cell distribution is low. Figure 6 In the example shown, the normal cell whose on-current Ion does not reach the threshold level of the erase verification causes Figure 5 The error is determined to fail in the erasure verification process shown ("failure" in step ST2), but can be immediately determined to be correctable in the subsequent step ST3.

[0068] That is, in the rewrite control method of the nonvolatile memory according to the second comparative example, Figure 6 As shown, there is a possibility that not only abnormal cells but also normal cells whose on-current Ion has not reached the threshold level of the erase verification are allowed to be erased by error correction. In this case, there is a problem that the data retention margin is insufficient and the data retention time is shortened.

[0069] <Effect of Nonvolatile Memory Rewrite Control Method>

[0070] Next, refer to Figure 7 , the effects of the nonvolatile memory rewrite control method according to the first embodiment will be explained.

[0071] Figure 7 is a graph for explaining the effect of the nonvolatile memory rewrite control method according to the first embodiment.

[0072] Figure 7 The horizontal axis represents the number of cells, and the vertical axis represents the on-current Ion of the cell.

[0073] Figure 7 and Figure 4 Likewise, a case where there are abnormal cells having a smaller on-current Ion deviating from the distribution of normal cells is shown.

[0074] exist Figure 7 In the example shown, the abnormal cell did not exceed the threshold level of the erase verification, resulting in Figure 2 The failure in the erasure verification process shown is determined ("failure" in step ST2), but is immediately determined to be correctable in the subsequent step ST3.

[0075] Therefore, in the nonvolatile memory rewrite control method according to the first embodiment, the erasure time can be shortened by determining whether the erasure time is error correctable without repeating the erasure process. Figure 4 and Figure 7 It can be seen from the comparison between the two that the excessive stress on the normal cells due to the repeated erasing process can be suppressed.

[0076] On the other hand, Figure 2 As shown, the number of correctable addresses is counted (step ST4), and the number of such addresses is limited to m or less (step ST5). That is, the number of correctable addresses is limited so that error correction is allowed only when the cause of failure in the erase verification process is determined to be due to abnormal cells. Figure 6 and Figure 7 A comparison between the two shows that, for normal cells that do not meet the threshold level of the erase verification on-current, the tolerance due to error correction is suppressed and the data retention margin can also be ensured.

[0077] (Second embodiment)

[0078] <Nonvolatile Memory Rewrite Control Method>

[0079] Next, refer to Figure 8 , a nonvolatile memory rewrite control method according to a second embodiment will be explained. Figure 8 is a flowchart showing a nonvolatile memory rewrite control method according to the second embodiment. Figure 8 A control method for the writing process and the writing verification process is shown.

[0080] Figure 8 The writing process and writing verification process shown in Figure 2 The configuration of the nonvolatile memory system according to the second embodiment is as follows: Figure 1 As shown, it is the same as in the first embodiment. Figure 8 Please refer to Figure 1 .

[0081] First, if Figure 8 As shown, the controller 20 performs a write process on the nonvolatile memory 10 (step ST11). For example, if the nonvolatile memory 10 is a flash memory, in the erase process performed before the write process, all data cells are turned on and all data cell values ​​are set to "1". Then, in Figure 8 In the writing process shown (step ST11), a predetermined data cell is switched from on to off, and the value of the data cell is switched from "1" to "0" based on the write data.

[0082] Next, if Figure 8 As shown, the controller 20 performs a write verification process to determine whether the write process (step ST11) is passed or failed (step ST12). For example, the controller 20 reads data from the nonvolatile memory 10 that has performed the write process and determines whether all data unit values ​​match the write data value.

[0083] If all data unit values ​​match the written data values, the controller 20 determines that the write verification process passes ("pass" in step ST12). Figure 8 As shown, the controller 20 finally determines that the writing process is normal and ends the writing process (via End).

[0084] On the other hand, if the value of the data unit includes a value that does not match the value of the write data, the controller 20 determines a failure in the write verification process ("failure" of step ST12). Figure 8 As shown, it is determined whether the value of a cell that can be rewritten from "1" to "0" (referred to as "rewrite bit") matches the value "0" of the write data (step ST13).

[0085] like Figure 8 As shown, if the value of the rewrite bit includes a value that does not match the value of the write data (step ST13 is "No"), and if the number of retries of the write process is not the maximum value, it returns to step ST11 and performs the write process again. If the number of retries of the write process reaches its maximum value, the controller 20 finally determines that the write process is abnormal and ends the write process (failure end).

[0086] On the other hand, Figure 8 As shown, if all the values ​​of the rewrite bits match the values ​​of the write data and are correct ("YES" at step ST13), it is determined whether error correction is possible (step ST14).

[0087] Here, if it is determined that error correction is possible ("Yes" in step ST14), the controller 20 finally determines that the writing process is normal and ends the writing process (by ending). Figure 8 As shown, if it is determined that error correction is impossible ("No" at step ST14), the controller 20 finally determines that the writing process is abnormal and ends the writing process (failure end).

[0088] here, Fig. 9 It is schematically shown by Figure 8 The value of each data unit of the written data is as shown in FIG. Fig. 9The value of each data unit in the initial (erased) state is shown in the second row. In addition, the value of each data unit after the first write process is shown in Fig. 9 The values ​​after the second writing process are shown in the fourth row. The values ​​after the third writing process are shown at the bottom.

[0089] like Fig. 9 As shown in the second row of FIG. 1 , the value of the third data unit from the left in the figure is "0", which is an erasure error, but is allowed by the error correction in the erasure verification process of the first embodiment.

[0090] Fig. 9 The third row shows the value "10011101" after the first write process. Fig. 9 The value "00101000" of the written data shown at the top does not match, so it is determined as Figure 8 The failure in the write verification process shown ("failure" in step ST12). In addition, since the value of the rewrite bit that should be "0" does not match the value "0" of the rewrite bit in the write data ("No" in step ST13), it returns to step ST11 and executes the write process again.

[0091] Fig. 9 The value "00001101" after the second writing process shown in the fourth row is the same as Fig. 9 The value "00101000" of the write data shown at the top does not match, so it is determined to be Figure 8 The failure in the write verification process shown ("failure" in step ST12). In addition, since the value of the rewrite bit that should be "0" does not match the value "0" of the rewrite bit in the write data ("No" in step ST13), it returns to step ST11 and executes the write process again.

[0092] Fig. 9 The value after the third write process is shown at the bottom of Fig. 9 The value "00101000" of the written data shown at the top does not match, so it is determined as Figure 8 The write verification process shown in FIG. 1 shows a failure (“failure” of step ST12). On the other hand, since the value of the rewrite bit that should be “0” matches the “0” value of the rewrite bit in the write data (“yes” of step ST13), it is determined whether error correction is possible (step ST14). Here, since the error bit is only one bit of an erase error, error correction is possible (“yes” of step ST14). Therefore, the write process is finally determined to be normal.

[0093] Here, according to Figure 2 The erasure process and the erasure verification process of the first embodiment shown are tolerant to erasure errors. Figure 8 In the writing process and writing verification process according to the present embodiment shown, only the erasure error in the initial (erased) state is tolerated, and the error in the rewritten bit during the writing process is not tolerated. The other configurations are the same as the first embodiment, so the description is omitted.

[0094] In the above examples, the program includes a set of instructions (or software codes) that cause the computer to perform one or more functions described in the embodiments when loaded into the computer. The program can be stored in a non-transitory computer-readable medium or a tangible storage medium. Non-limiting examples of computer-readable media or tangible storage media include RAM (random access memory), ROM (read-only memory), flash memory, SSD (solid state drive) or other storage technology, CD-ROM, DVD (digital versatile disk), Blu-ray (registered trademark) disk or other optical disk storage, cassettes, tapes, disk storage or other magnetic storage devices. The program can be transmitted on a transient computer-readable medium or a communication medium. Non-limiting examples of transient computer-readable media or communication media include electrical, optical, acoustic or other forms of propagation signals.

[0095] The invention of the present inventors has been specifically described based on the embodiments, but the present invention is not limited to the embodiments that have been mentioned, and it goes without saying that various changes can be made within the scope that does not depart from the gist thereof.

Claims

1. A semiconductor device, comprising: A nonvolatile memory including a data unit and an error correction code unit corresponding to each address; as well as a controller circuit configured to perform a bulk erase process for a plurality of addresses of the nonvolatile memory and an erase verification process for each address to determine whether the erase process passed or failed; The controller circuit determines the availability of error correction for addresses determined to have failed during the verification process, counts the number of addresses determined to be available for error correction, and determines that the erasure process is normal when the number of addresses available for error correction is equal to or less than a predetermined number.

2. The semiconductor device according to claim 1, Wherein when the number of the addresses exceeds the predetermined number, the controller circuit determines that the erasing process is abnormal and re-executes the erasing process. 3 . The semiconductor device according to claim 2 , wherein the number of times the erasing process is re-executed is predetermined.

4. The semiconductor device according to claim 1, wherein the controller circuit further performs a write process on the nonvolatile memory for which the erase process has been performed, and performs a write verification process for determining whether the write process passes or fails; wherein when it is determined that the write verification process has failed, the controller circuit determines whether all values ​​of the rewrite bits that can be rewritten from the erased state are correct, wherein when all values ​​of the rewrite bits are correct, the controller circuit determines whether error correction is available; Wherein when the error correction is determined to be available, the controller circuit determines that the writing process is normal.

5. The semiconductor device according to claim 4, When the value of the rewrite bit is incorrect, the controller circuit determines that the write process is abnormal, and re-executes the write process and the write verification process.

6. The semiconductor device according to claim 4, When it is determined that error correction is not available, the controller circuit determines that the writing process is ultimately abnormal.

7. A non-volatile memory rewrite control method, comprising: (a) performing a bulk erase process for a plurality of addresses of a non-volatile memory, the non-volatile memory including a data unit and an error correction code unit for each address, and (b) performing an erase verification process that determines whether the erase process passes or fails for each address, (c) determining whether error correction is available for an address determined to have failed during the erase verification process, (d) counting the number of addresses for which error correction is determined to be available, and (e) When the number of the addresses for which the error correction is available is equal to or smaller than a predetermined number, it is determined that the erasing process is normal.

8. The nonvolatile memory rewrite control method according to claim 7, Wherein when the number of the addresses exceeds the predetermined number, the erasing process is determined to be abnormal, and the erasing process is re-executed.

9. The nonvolatile memory rewrite control method according to claim 8, The number of times the erasing process is re-executed is predetermined.

10. The nonvolatile memory rewrite control method according to claim 7, wherein the method further performs a write process on the nonvolatile memory on which the erase process has been performed, and performs a write verification process to determine whether the write process passes or fails, wherein when it is determined that the write verification process has failed, the controller circuit determines whether all values ​​of the rewrite bits that can be rewritten from an erased state are correct; wherein when all values ​​of the rewrite bits are correct, the controller circuit determines whether error correction is available; Wherein when the error correction is determined to be available, the controller circuit determines that the writing process is normal.

11. The nonvolatile memory rewrite control method according to claim 10, When the value of the rewrite bit is incorrect, the controller circuit determines that the write process is abnormal, and re-executes the write process and the write verification process.

12. The nonvolatile memory rewrite control method according to claim 10, When it is determined that the error correction is not available, the controller circuit determines that the writing process is ultimately abnormal.

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