A semiconductor test structure and manufacturing method thereof

Abstract

The present invention discloses a semiconductor test structure and a manufacturing method thereof, belonging to the field of semiconductor technology, wherein the test structure at least comprises: a substrate, comprising a plurality of active regions arranged in parallel; a plurality of gates, arranged in parallel on the plurality of active regions, a gate dielectric layer arranged between the gates and the active regions, the gates and the active regions being perpendicular; a first metal silicide, arranged at least on a portion of the gates and the sidewalls on one side of the gates, and extending to the active regions; at least one test hole group is arranged on a single active region between adjacent gates, the test hole group and the first metal silicide are staggered; a connecting hole is arranged on the active regions on one side of the plurality of gates; at least one first test point is arranged on the test hole group and connected to the test hole group; a second test point is arranged on the connecting hole and connected to the connecting hole. Through the semiconductor test structure and the manufacturing method thereof provided by the present invention, the manufacturing quality of the metal silicide can be fed back in time, and the monitoring efficiency can be improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a semiconductor test structure and a manufacturing method thereof. Background Art

[0002] After preparing the semiconductor device, it is necessary to form a conductive plug to connect the conductive structure on the semiconductor device. In the semiconductor device, the conductive structure may be located in the doped region on the substrate, may be arranged on the gate, or may be arranged on the sidewall structure. When the conductive structure is arranged on the sidewall structure, when the metal silicide is formed, the distance between the gates is insufficient, and the oxide layer of this structure can only be removed by dry etching, resulting in the formed metal silicide penetrating the source and drain regions and lightly doping into the well region and leaking electricity, or the formed metal silicide has poor contact, thereby causing the conductive structure to have high resistance and leakage. However, it is currently impossible to timely monitor and accurately test problems such as metal silicide penetrating the source and drain regions and lightly doping into the well region and leaking electricity or poor contact. Summary of the invention

[0003] The purpose of the present invention is to provide a semiconductor test structure and a method for making the same. Through the semiconductor test structure and the method for making the same provided by the present invention, it is possible to timely feedback problems such as leakage of metal silicide due to penetration of the source and drain regions and light doping to the well region or poor contact of metal silicide, accurately judge problems such as residual oxide layer or over-etching, and improve monitoring efficiency. It is possible to accurately and quickly feedback process conditions, optimize in a timely manner, greatly improve project progress, reduce development cycles and costs, and help improve the manufacturing yield and manufacturing efficiency of semiconductor devices.

[0004] In order to solve the above technical problems, the present invention provides a semiconductor test structure, which at least comprises:

[0005] A substrate including a plurality of active regions arranged in parallel;

[0006] A plurality of gates are arranged in parallel on the plurality of active regions, a gate dielectric layer is arranged between the gates and the active regions, and the gates are perpendicular to the active regions;

[0007] A first metal silicide is disposed on at least a portion of the gate and a sidewall of one side of the gate and extends onto the active region;

[0008] At least one test hole group is provided on a single active area between adjacent gates, wherein the test hole group and the first metal silicide are staggeredly distributed;

[0009] A connection hole is provided on the active area on one side of the plurality of gates;

[0010] at least one first test point, disposed on the test hole group and connected to the test hole group; and

[0011] The second test point is arranged on the connection hole and connected to the connection hole.

[0012] In one embodiment of the present invention, sidewall structures are provided on both sides of the gate, the first metal silicide covers the sidewall structure on one side of the gate, and a blocking layer is provided between the first metal silicide and the gate, the sidewall structure and the substrate.

[0013] In an embodiment of the present invention, the semiconductor test structure further includes a second metal silicide, and the second metal silicide is directly disposed on the gate and the active region.

[0014] In one embodiment of the present invention, a single test hole group includes 3 to 6 test holes, and the test holes are connected to the second metal silicide.

[0015] In one embodiment of the present invention, the semiconductor test structure includes a test metal layer, the test metal layer includes a first test metal layer, the first test metal layer is arranged on the test hole group, and the first test metal layer on the same active area between adjacent gates is spaced apart, adjacent test hole groups in different active areas share the same first test metal layer, and one end of adjacent test hole groups share the same first test metal layer.

[0016] In an embodiment of the present invention, the test metal layer includes a second test metal layer, and the second test metal layer connects all of the connection holes.

[0017] In one embodiment of the present invention, the first test point is set on the first test metal layer, the second test point is set on the second test metal layer, a voltage difference is set between the first test point and the second test point, and the resistance between the first test point and the second test point is tested.

[0018] In one embodiment of the present invention, the number of test holes in the test hole group and the resistance correlation between the first test point and the second test point both present an exponential function relationship: y=k x / n +b; wherein, y is the test resistance, x is the distance from the edge of the gate dielectric layer to the sidewall structure, k and b are coefficients, and n is the number of the test holes.

[0019] The present invention also provides a method for manufacturing a semiconductor test structure, which at least comprises the following steps:

[0020] Providing a substrate, the substrate comprising a plurality of active regions arranged in parallel;

[0021] A plurality of gates are formed and arranged in parallel on the plurality of active regions, a gate dielectric layer is formed between the gates and the active regions, and the gates are perpendicular to the active regions;

[0022] forming a first metal silicide on at least a portion of the gate and a sidewall of one side of the gate, and extending to the active area;

[0023] Forming at least one test hole group on a single active region between adjacent gates, wherein the test hole group and the first metal silicide are staggeredly distributed;

[0024] forming a connection hole on the active area on one side of the plurality of gates;

[0025] forming at least one first test point on the test hole group, wherein the first test point is connected to the test hole group; and

[0026] A second test point is formed on the connection hole, and the second test point is connected to the connection hole.

[0027] In one embodiment of the present invention, the manufacturing method further includes:

[0028] forming the gate dielectric layer on the active area;

[0029] forming a plurality of gates on the gate dielectric layer;

[0030] Forming a sidewall structure on the gate dielectric layer at both sides of the gate;

[0031] Etching the gate dielectric layer to remove the gate dielectric layer outside the gate and the sidewall structure;

[0032] forming a barrier layer and a polysilicon film in sequence on the sidewall structure on one side of the gate, and extending to a portion of the gate and the active area; and

[0033] The polysilicon film, a portion of the gate and the active region are metallized to form metal silicide.

[0034] In summary, the present invention provides a semiconductor test structure and a method for manufacturing the same. The unexpected technical effect of the present application is that it can monitor and test in time, timely feedback the problems such as leakage of metal silicide due to penetration of source and drain regions and light doping to well regions or poor contact of metal silicide, accurately judge the problems such as residual oxide layer or over-etching, and improve the monitoring efficiency. It can accurately and quickly feedback the process status, timely optimize, greatly improve the project progress, reduce the development cycle and cost, and help improve the production yield and production efficiency of semiconductor devices. It can set multiple test structures on the same substrate, and the distances between the gates in different test structures are different, which fully improves the monitoring efficiency, determines the process window, and saves research and development costs. According to the test results, the remaining condition of the gate dielectric layer when the metal silicide is formed is estimated to judge the etching health status of different gate spacings, and it is more intuitive and effective to judge whether it is necessary to adjust the relevant process and process to optimize the process. The test structure is manufactured synchronously with the semiconductor device, which can simplify the manufacturing process of the test structure, timely detect the defects that may be caused by different gate spacings in the semiconductor device when preparing metal silicide, and timely improve the manufacturing process to improve the yield and reliability of the product.

[0035] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0037] Figure 1 FIG. 4 is a top view of a test structure in an embodiment.

[0038] Figure 2 For along Figure 1 A cross-sectional view after the gate and sidewall structures are formed in the XX direction.

[0039] Figure 3 For along Figure 1 Cross-sectional view after etching the gate dielectric layer in the XX direction.

[0040] Figure 4 For along Figure 1 A cross-sectional view of a barrier layer and a polysilicon film formed in the XX direction.

[0041] Figure 5 For along Figure 1 A cross-sectional view of a first metal silicide and a second metal silicide formed in the XX direction.

[0042] Figure 6For along Figure 1 A cross-sectional view of a contact hole etching stop layer and a dielectric layer formed in the XX direction.

[0043] Figure 7 For along Figure 1 A cross-sectional view of the test hole is formed in the XX direction.

[0044] Description of labels:

[0045] 10. Substrate; 101. Active area; 102. Isolation structure; 11. Gate dielectric layer; 12. Gate; 13. Sidewall structure; 131. First sublayer; 132. Second sublayer; 133. Third sublayer; 134. Fourth sublayer; 14. Barrier layer; 15. Polysilicon film; 151. First metal silicide; 152. Second metal silicide; 16. Contact hole etch stop layer; 17. Dielectric layer; 18. Test hole group; 181. Test hole; 182. Connection hole; 191. First test metal layer; 192. Second test metal layer. DETAILED DESCRIPTION

[0046] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0047] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0048] In the present invention, it should be noted that, if the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, if the terms "first" and "second" appear, they are only used for description and distinction purposes, and cannot be understood as indicating or implying relative importance.

[0049] See also Figure 1As shown, in one embodiment of the present invention, the semiconductor test structure includes a substrate 10, a plurality of gates 12, a first metal silicide 151, a plurality of test hole groups 18, a connecting hole 182, at least one first test point and a second test point C. The substrate 10 includes a plurality of active regions 101 arranged in parallel, the active regions 101 are isolated by an isolation structure 102, and the active regions 101 are equidistantly distributed, the gates 12 are arranged in parallel on the plurality of active regions 101, and span the plurality of active regions 101, that is, the gates 12 and the active regions 101 are vertically distributed. The test hole group 18 is arranged on the active region between adjacent gates 12, and at least one test hole group 18 is arranged on a single active region 101 between adjacent gates 12. The first metal silicide 151 is arranged on at least a portion of the gate 12 and the sidewall of the gate 12, and extends to the active region 101, and the first metal silicide 151 on adjacent gates 12 is connected. The connection hole 182 is arranged on the active area 101 on one side of the plurality of gates 12, the first test point is arranged on the test hole group 18 and connected to the test hole group 18, and the second test point is arranged on the connection hole 182 and connected to the connection hole 182. Through this test structure, timely monitoring and testing can be performed, and timely feedback can be given on problems such as leakage of metal silicide due to penetration of the source and drain regions and light doping into the well region or poor contact of the metal silicide, etc., and problems such as residual oxide layer or over-etching can be accurately judged, and monitoring efficiency can be improved, and timely feedback can be given, which is beneficial to improving the manufacturing yield and manufacturing efficiency of semiconductor devices. Specifically, the specific structure and manufacturing method of the semiconductor test structure of the present application are as follows: Figures 1 to 7 As shown, in this embodiment, for example, along Figure 1 The production method is explained using the cross-sectional view in the XX direction as an example.

[0050] See also Figure 1As shown, in one embodiment of the present invention, the semiconductor device on the substrate 10 (not shown in the figure) includes, for example, a field effect transistor (FET), a metal-oxide semiconductor field effect transistor (MOSFET), a complementary metal oxide semiconductor (CMOS), an insulated gate bipolar transistor (IGBT), a fast recovery diode (FRD), a high-speed and high-efficiency rectifier diode (HED), a light-emitting diode (LED), a gate light-closed thyristor (GTO), a light-triggered thyristor (LTT), a thyristor, a charge coupled device (CCD image sensor), a digital signal processor (DSP), a photorelay (PhotoRelay) or a microprocessor and other semiconductor devices or one or more thereof. In the present embodiment, the semiconductor device is, for example, a laterally diffused metal-oxide semiconductor field effect transistor (LDMOS), and the gate spacings on different device regions on the substrate are different. The semiconductor test structure provided in the present application is arranged in the cutting path between adjacent semiconductor devices, and multiple test structures are arranged on the same substrate. The distances between the gates in different test structures are different, corresponding to the gate spacings in different regions in the substrate 10, which fully improves efficiency, shortens R&D time, and saves R&D costs. The test structure is manufactured synchronously with the semiconductor device, which can simplify the manufacturing process of the test structure, timely detect defects that may be caused by different gate spacings in the semiconductor device when preparing metal silicide, timely improve the manufacturing process, improve the yield and reliability of the product, and reduce production costs.

[0051] See also Figure 1As shown, in one embodiment of the present invention, the substrate 10 provided by the present invention is any applicable semiconductor material, such as sapphire, silicon wafer, silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN) or silicon germanium (GeSi) substrates, and also includes a stacked structure composed of these semiconductor materials, or silicon on insulator, stacked silicon on insulator, stacked silicon germanium on insulator, silicon germanium on insulator, and germanium on insulator, etc., which can be selected according to the manufacturing requirements of the semiconductor device. In this embodiment, the substrate 10 is, for example, a silicon wafer semiconductor substrate, and the substrate 10 can be an undoped substrate or a doped substrate, and for example, an N-type substrate or a P-type substrate, and the thickness of the substrate 10 is not specifically limited, and is selected according to the manufacturing requirements. A plurality of isolation structures 102 are formed in the substrate 10, and the substrate 10 is divided into a plurality of active areas 101, wherein the isolation structure 102 is, for example, a shallow trench isolation structure, and is formed by any shallow trench isolation structure manufacturing method, which will not be elaborated here.

[0052] See also Figure 1 to Figure 2 As shown, in one embodiment of the present invention, after forming the isolation structure 102, a gate dielectric layer 11 is formed on the substrate 10. The gate dielectric layer 11 is, for example, a dense silicon oxide or other material. The gate dielectric layer 11 is prepared, for example, by thermal oxidation, in-situ steam growth (ISSG) or chemical vapor deposition (CVD). In this embodiment, the gate dielectric layer 11 is prepared by, for example, in-situ steam growth. Specifically, the substrate 10 is placed in a furnace tube at a temperature of, for example, 900°C to 1150°C, and oxygen mixed with a small amount of hydrogen is introduced. The silicon on the surface of the substrate 10 reacts with oxygen and hydrogen at high temperature to generate a dense gate dielectric layer 11, and the quality of the generated gate dielectric layer 11 is good. Among them, the thickness of the gate dielectric layer 11 is, for example, 5nm to 20nm.

[0053] See also Figure 1 to Figure 2As shown, in one embodiment of the present invention, a gate material layer (not shown in the figure) is formed on the gate dielectric layer 11. The gate material layer is, for example, a polysilicon layer, etc. The gate material layer is formed, for example, by chemical vapor deposition or physical vapor deposition (PVD), and the thickness of the gate material layer can be set according to actual needs. Then, the gate material layer is etched by, for example, a dry etching process, a wet etching process, or a combination of a dry etching process and a wet etching process to form a plurality of gates 12 arranged in parallel, and the distance between adjacent gates is, for example, 200nm~350nm, and the distance between gates in different test structures is different. The present application does not limit the type of semiconductor device, and the test structure can be used to test NMOS transistors or PMOS transistors, etc., and has a wide range of applications.

[0054] See also Figure 1 to Figure 2 As shown, in one embodiment of the present invention, after forming the gate 12, the gate dielectric layer 11 is used as an ion implantation buffer layer, a lightly doped region (not shown in the figure) is formed on both sides of the gate 12, and then a sidewall structure 13 is formed on both sides of the gate 12. Specifically, a sidewall structure dielectric layer (not shown in the figure) is formed on the substrate 10 and the gate, and then the sidewall structure dielectric layer is etched, and only the sidewall structure dielectric layer on both sides of the gate 12 is retained to form the sidewall structure 13. The sidewall structure 13 is, for example, flush with the height of the gate 12, wherein the sidewall structure 13 is, for example, a stacked structure. In this embodiment, the sidewall structure 13, starting from the side close to the gate 12, for example, includes a stacked first sublayer 131, a second sublayer 132, a third sublayer 133 and a fourth sublayer 134, wherein the first sublayer 131 and the third sublayer 133 are, for example, silicon oxide layers, and the second sublayer 132 and the fourth sublayer 134 are, for example, silicon nitride layers. By setting the sidewall structure 13 as a stacked structure, the stress of silicon nitride on the gate is reduced, and the parasitic capacitance is effectively controlled.

[0055] See also Figures 2 to 3As shown, in one embodiment of the present invention, after forming the sidewall structure 13, the gate dielectric layer 11 is used as an ion implantation buffer layer, and ion doping is performed in the substrate on both sides of the gate 12 to form a heavily doped (not shown in the figure) to serve as a source and a drain. Then the gate dielectric layer 11 is etched to the substrate 10, and the gate dielectric layer 11 in the area outside the gate 12 and the sidewall structure 13 is removed to expose the substrate 10, so as to facilitate the formation of metal silicide on the substrate 10 in the subsequent process. Specifically, the photoresist used when forming the sidewall structure 13 is continued as a mask, for example, the gate dielectric layer 11 is etched by dry etching, and the etching gas includes, for example, chlorine (Cl2), trifluoromethane (CHF3), difluoromethane (CH2F2), carbon tetrafluoride (CF4) or hydrogen bromide (HBr), etc., or a mixture of them and oxygen (O2). Through dry etching, the etching time is controlled to reduce the etching of silicon oxide in the sidewall structure 13, which causes the sidewall structure 13 to be lower than the gate 12. During the etching process, the gate dielectric layer 11 between adjacent gates 12 may not be completely etched, and there may be residues, resulting in incomplete metal silicide formed subsequently, or over-etching of the gate dielectric layer 11, resulting in leakage of subsequent devices. The test structure provided in the present application can accurately test the situation where the gate dielectric layer 11 is not completely etched or over-etched, thereby improving the accuracy of the test.

[0056] See also Figure 3 to Figure 4 As shown, in one embodiment of the present invention, after etching the gate dielectric layer 11, a continuous barrier layer 14 and a polysilicon film 15 are sequentially formed on the substrate 10, the gate 12 and the sidewall structure 13, and the polysilicon film 15 is disposed on the barrier layer 14. The barrier layer 14 is, for example, a silicon oxide layer, and the barrier layer 14 is, for example, formed by chemical vapor deposition or atomic layer deposition (ALD) and the like, and the thickness of the barrier layer 14 is, for example, 40nm to 120nm. The polysilicon film 15 is, for example, formed by chemical vapor deposition or physical vapor deposition (PVD) and the like, and the thickness of the polysilicon film 15 is, for example, 20nm to 40nm. After depositing the barrier layer 14 and the polysilicon film 15, for example, by dry etching, the barrier layer 14 and the polysilicon film 15 on the substrate 10, the gate 12 and the sidewall structure 13 are partially removed, and after etching, the edges of the barrier layer 14 and the polysilicon film 15 are aligned. In this embodiment, on each gate 12, the width of the gate 12 covered by the barrier layer 14 is, for example, one third to one half of the width of the gate 12, and the barrier layer 14 has a sidewall structure 13 extending on the gate 12 to cover one side of each gate 12 until it extends to the substrate 10, and between partially adjacent gates 12, the barrier layer 14 is continuously arranged on adjacent portions of the gate 12, the sidewall structure and the substrate 10.

[0057] See also Figures 4 to 5 As shown, in one embodiment of the present invention, after etching the barrier layer 14 and the polysilicon film 15, a metal layer (not shown in the figure) is formed on the substrate 10. The metal layer continuously covers the substrate 10, the gate 12, the sidewall structure 13 and the polysilicon film 15. The material of the metal layer is, for example, at least one of titanium (Ti), cobalt (Co), platinum (Pt) or nickel (Ni), and the thickness of the metal layer is, for example, 20nm~30nm, and the metal layer is formed by, for example, electroplating or sputtering deposition. Then, the substrate 10 is subjected to a first annealing, and the temperature of the first annealing is, for example, 260℃~350℃, so that the metal atoms react with the silicon atoms in the substrate 10, the gate 12 and the polysilicon film 15 to form an intermediate silicide layer, and then the unreacted metal layer is selectively removed by wet etching, and the intermediate silicide layer is subjected to a second annealing, and the temperature of the second annealing is greater than the temperature of the first annealing, and the temperature of the second annealing is, for example, 400℃~900℃. After annealing, the intermediate silicide layer is converted into metal silicide, thereby reducing the source-drain resistance. In this embodiment, the metal silicide includes a first metal silicide 151 and a second metal silicide 152, and the first metal silicide 151 is disposed on a portion of the gate 12 and the sidewall structure 13 on one side of the gate 12, and extends to the active area 101, and the second metal silicide 152 is disposed on the barrier layer 14, and the second metal silicide 152 is disposed on a portion of the substrate 10 and the gate 12, and is in direct contact with the substrate 10 or the gate 12.

[0058] See also Figure 5 to Figure 6 As shown, in one embodiment of the present invention, after forming the metal silicide, a contact hole etch stop layer 16 is formed on the substrate 10. The contact hole etch stop layer 16 covers the first metal silicide 151 and the second metal silicide 152, and the contact hole etch stop layer 16 is, for example, a silicon nitride layer, and the thickness is, for example, 8nm to 20nm. In one embodiment of the present invention, the contact hole etch stop layer 16 is prepared by a low-temperature deposition method such as plasma enhanced chemical vapor deposition (PECVD), and the deposition source includes a nitrogen source and a silicon source, wherein the nitrogen source is selected from one or a combination of nitrogen (N2) or ammonia (NH3), and the silicon source is selected from one or a combination of silane (SiH4), disilane (Si2H6), dichlorosilane (SiH2Cl2), trichlorosilane (SiHCl3), tetrachlorosilane (SiCl4) or hexachlorodisilane (Si2Cl6).

[0059] See also Figure 5 to Figure 6As shown, in one embodiment of the present invention, after forming the contact hole etch stop layer 16, a dielectric layer 17 is formed on the contact hole etch stop layer 16, wherein the dielectric layer 17 is prepared, for example, by silicon dioxide or a low dielectric constant (Low-K) material to improve the reliability of the semiconductor structure. And the dielectric layer 17 is deposited, for example, by a high aspect ratio process to improve the filling capacity of the dielectric layer 17. After forming the dielectric layer 17, the dielectric layer 17 is subjected to a planarization process, for example, by removing part of the dielectric layer 17 through a chemical mechanical polishing (CMP) process to ensure that the surface of the dielectric layer 17 is flat, thereby improving the convenience of subsequent metal connection structure manufacturing. In this embodiment, the remaining thickness of the dielectric layer 17 on the gate 12 is, for example, 60nm~100nm.

[0060] See also Figure 1 , Figure 6 to Figure 7 As shown, in one embodiment of the present invention, after forming the dielectric layer 17, a plurality of openings (not shown in the figure) are formed in the dielectric layer 17. In this embodiment, the openings are, for example, arranged on the substrate 10 between the gates and on the substrate 10 on one side of the plurality of gates, and the openings penetrate the dielectric layer 17 and the contact hole etching stop layer 16 to expose the metal silicide. In this embodiment, the openings are, for example, formed by dry etching. After the openings are formed, a conductive material is deposited in the openings to form a plurality of test hole groups 18 and a connection hole 182. When depositing the conductive material, a barrier layer (not shown in the figure) may be deposited in the openings first, and the barrier layer may be, for example, a material with good adhesion such as tantalum (Ta), titanium (Ti), tantalum nitride (TaN) or titanium nitride (TiN), and the thickness of the barrier layer may be, for example, 1 nm to 5 nm. Among them, the conductive material may be, for example, a low-resistance metal material such as copper, aluminum or tungsten. In this embodiment, the conductive material may be, for example, metal tungsten. The metal tungsten is formed, for example, by physical vapor deposition or electroplating, and the metal tungsten is filled in the opening until it covers the dielectric layer 17 , and then the metal tungsten is planarized so that the metal tungsten is flush with the dielectric layer 17 on both sides of the opening.

[0061] See also Figure 1 and Figure 7As shown, in one embodiment of the present invention, the test hole group 18 is arranged on the active area between adjacent gates 12, and at least one test hole group 18 is arranged on a single active area 101 between adjacent gates 12. In this embodiment, two test hole groups 18 are arranged on a single active area 101 between adjacent gates 12, for example. In each test hole group 18, 3 to 6 test holes 181 are included. If the number of test holes 181 is 1, it is impossible to accurately and truly reflect the process status, and is greatly disturbed by other defects (defects) and other non-related processes. If the number of test holes in the test hole group 18 is too large, the detection and discrimination error of the oxide layer residue will be larger, the sensitivity will be worse, and the tolerance of the fuzzy test will be stronger. When there are less than 3 test holes, the interference factor is amplified and misleads the judgment. Therefore, the number of test holes 181 in the test hole group 18 is controlled to improve the accuracy of the test. The connection holes 182 are arranged on the active area 101 on one side of the plurality of gates 12, and 4 to 8 connection holes 182 are arranged on each active area 101, and the connection holes 182 on the same active area 101 are arranged equidistantly. After forming the test hole group 18 and the connection hole 182, a test metal layer is formed on the test hole group 18, the connection hole 182 and the dielectric layer 17, and the test metal layer includes a first test metal layer 191 and a second test metal layer 192, wherein the first test metal layer 191 is arranged on the test hole group 18, and the first test metal layer 191 on the same active area 101 between adjacent gates 12 is arranged at intervals, adjacent test hole groups 18 of different active areas 101 share the same first test metal layer 191, one end of adjacent test hole groups 18 share the same first test metal layer 191, and the second test metal layer 192 connects all the connection holes 182. The present application does not limit the type of semiconductor device, and can be used to test NMOS transistors or PMOS transistors, etc.

[0062] See also Figure 1 and Figure 7 As shown, in one embodiment of the present invention, through experimental data and simulation, the resistance correlation between the number of test holes 181 in the test hole group 18 and the resistance presents an exponential function relationship: y=k x / n +b. Wherein, y is the test resistance, x is the distance from the edge of the gate dielectric layer 11 to the sidewall structure 13, that is, the remaining amount of the gate dielectric layer 11, k and b are coefficients, and n is the number of test holes 181. When the CT number is less than 3 or greater than 6, the correlation is not obvious, especially when it is less than 3, there is basically no correlation, and when it is greater than 6, there is a certain linear and nonlinear superposition correlation. In this way, the remaining condition of the gate dielectric layer when forming the metal silicide can be estimated according to the test results to judge the etching health of different gate spacings, and it is more intuitive and effective to judge whether relevant process and process adjustments are needed to optimize the formation of the structure with the first metal silicide or the process of simply using dry etching when forming the metal silicide.

[0063] See also Figure 1 and Figure 7 As shown, in one embodiment of the present invention, after forming the test metal layer, a first test point is set on the first test metal layer 191 at A and / or B in 1, and a second test point is set at one end of the second test metal layer 192, such as C. In this embodiment, the first test point is set on the first test metal layer 191 at A and B respectively. During the test process, there is a voltage difference between the first test point and the second test point, such as any first test point is connected to a preset positive voltage, and the second test point is grounded, and the relationship between the resistance between the first test point at A or B and the second test point and the preset value is tested to determine the formation quality of the formed metal silicide. For example, when forming metal silicide, the oxide layer such as the gate dielectric layer 11 remaining between the gate 12 makes the formation window of the metal silicide insufficient, resulting in the test resistance being 2 to 6.5 times the preset value. When the oxide layer such as the gate dielectric layer 11 remaining between the gate 12 makes the metal silicide completely unformed, the test hole is high-resistance, and the test resistance is 6.5 to 60 times the preset value. When there are oxide layers such as the gate dielectric layer 11 remaining between the gates 12, causing some of the test holes to be open, the test resistance is about 600,000 to 10,000 times the preset value. When there are oxide layers such as the gate dielectric layer 11 remaining between the gates 12, causing some of the test holes to be open, the test resistance is infinite. When the test resistance is equivalent to the preset value, that is, there is no residual oxide such as the gate dielectric layer 11, then the leakage current between the two first test points is tested, that is, the leakage current between A and B, and based on the size of the leakage current, it is determined whether the gate dielectric layer 11 has been over-etched. If over-etching has occurred, there is leakage current, and based on the size of the leakage current, the number of over-etched locations is determined. In one embodiment of the present invention, when testing over-etching, A and B can be connected in common and given a high potential, and the size of the leakage current at C is measured. Based on the size of the leakage current, it is determined whether there is a risk of leakage current. Generally, the current tested is less than 10 -8 It is safer if it is below A or close to 0.

[0064] See also Figure 1 and Figure 7 As shown, in one embodiment of the present invention, when a test metal layer is formed, the test can be performed, that is, when the first metal wiring layer is formed on the semiconductor device, the test can be performed, and the device does not need to be completely manufactured. The process status can be accurately and quickly fed back, and timely optimization can be performed, which greatly improves the project progress, reduces the development cycle and cost, and is conducive to improving the production yield and production efficiency of semiconductor devices. Moreover, the test structure is manufactured synchronously with the semiconductor device, and the manufacturing process is the same, which can simplify the manufacturing process, improve the accuracy of detection, monitor in time, and reduce enterprise costs.

[0065] In summary, the present invention provides a semiconductor test structure and a method for making the same. By improving the semiconductor test structure and the method for making the same, the unexpected technical effect of the present application is that it can monitor and test in time, timely feedback the problems such as leakage of metal silicide due to penetration of source and drain regions and light doping to well regions or poor contact of metal silicide, accurately judge the problems such as residual oxide layer or over-etching, and improve the monitoring efficiency. It can accurately and quickly feedback the process status, optimize in time, greatly improve the project progress, reduce the development cycle and cost, and help improve the production yield and production efficiency of semiconductor devices. It can set multiple test structures on the same substrate, and the distances between the gates in different test structures are different, which fully improves the monitoring efficiency, determines the process window, and saves research and development costs. According to the test results, the remaining condition of the gate dielectric layer when forming the metal silicide is estimated to judge the etching health of different gate spacings, and it is more intuitive and effective to judge whether it is necessary to adjust the relevant process and process to optimize the formation of the structure with the first metal silicide or the process of simply using dry etching when forming the metal silicide. The test structure is manufactured simultaneously with the semiconductor device, which can simplify the manufacturing process of the test structure, timely detect defects that may be caused by different gate spacings in the semiconductor device when preparing metal silicide, timely improve the manufacturing process, and improve the yield and reliability of the product.

[0066] References throughout the specification to "one embodiment," "an embodiment," or "a specific embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention, and not necessarily in all embodiments. Thus, various appearances of the phrases "in one embodiment," "in an embodiment," or "in a specific embodiment" in different places throughout the specification do not necessarily refer to the same embodiment. In addition, the particular features, structures, or characteristics of any specific embodiment of the invention may be combined with one or more other embodiments in any suitable manner. It should be understood that other variations and modifications of the embodiments of the invention described and illustrated herein may be possible in light of the teachings herein and are to be considered part of the spirit and scope of the invention.

[0067] It should also be understood that the embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A semiconductor test structure, characterized in that: At least: A substrate including a plurality of active regions arranged in parallel; A plurality of gates are arranged in parallel on the plurality of active regions, a gate dielectric layer is arranged between the gates and the active regions, and the gates are perpendicular to the active regions; A first metal silicide is disposed on at least a portion of the gate and a sidewall of one side of the gate and extends onto the active region; At least one test hole group is provided on a single active area between adjacent gates, wherein the test hole group and the first metal silicide are staggeredly distributed; A connection hole is provided on the active area on one side of the plurality of gates; The test metal layer comprises a first test metal layer and a second test metal layer, wherein the first test metal layer is arranged on the test hole group, and the first test metal layer on the same active area between adjacent gates is arranged at intervals, and adjacent test hole groups in different active areas share the same first test metal layer, and one end of adjacent test hole groups share the same first test metal layer; The second test metal layer connects all the connection holes; At least one first test point, disposed on the first test metal layer and connected to the test hole group; A second test point, disposed on the second test metal layer and connected to the connection hole; A voltage difference is set between the first test point and the second test point, and the resistance between the first test point and the second test point is tested.

2. The semiconductor test structure according to claim 1, characterized in that: Sidewall structures are arranged on both sides of the gate, the first metal silicide covers the sidewall structure on one side of the gate, and a barrier layer is arranged between the first metal silicide and the gate, the sidewall structure and the substrate.

3. The semiconductor test structure according to claim 1, characterized in that: The semiconductor test structure further includes a second metal silicide disposed directly on the gate and the active region.

4. The semiconductor test structure according to claim 3, characterized in that: A single test hole group includes 3 to 6 test holes, and the test holes are connected to the second metal silicide.

5. The semiconductor test structure according to claim 1, characterized in that: The number of test holes in the test hole group and the resistance between the first test point and the second test point both present an exponential function relationship: y=k x / n +b; wherein, y is the test resistance, x is the distance from the edge of the gate dielectric layer to the sidewall structure, k and b are coefficients, and n is the number of the test holes.

6. A method for manufacturing a semiconductor test structure, characterized in that: At least the following steps are included: Providing a substrate, the substrate comprising a plurality of active regions arranged in parallel; A plurality of gates are formed and arranged in parallel on the plurality of active regions, a gate dielectric layer is formed between the gates and the active regions, and the gates are perpendicular to the active regions; forming a first metal silicide on at least a portion of the gate and a sidewall of one side of the gate, and extending to the active area; Forming at least one test hole group on a single active region between adjacent gates, wherein the test hole group and the first metal silicide are staggeredly distributed; forming a connection hole on the active area on one side of the plurality of gates; Forming a test metal layer, the test metal layer comprising a first test metal layer and a second test metal layer, the first test metal layer being formed on the test hole group, and the first test metal layer on the same active area between adjacent gates being arranged at intervals, adjacent test hole groups in different active areas sharing the same first test metal layer, and one end of adjacent test hole groups sharing the same first test metal layer; The second test metal layer connects all the connection holes; forming at least one first test point on the first test metal layer, wherein the first test point is connected to the test hole group; as well as A second test point is formed on the second test metal layer, and the second test point is connected to the connection hole; a voltage difference is set between the first test point and the second test point, and the resistance between the first test point and the second test point is tested.

7. The method for manufacturing a semiconductor test structure according to claim 6, characterized in that: The production method further comprises: forming the gate dielectric layer on the active area; forming a plurality of gates on the gate dielectric layer; Forming a sidewall structure on the gate dielectric layer at both sides of the gate; Etching the gate dielectric layer to remove the gate dielectric layer outside the gate and the sidewall structure; forming a barrier layer and a polysilicon film in sequence on the sidewall structure on one side of the gate, and extending to a portion of the gate and the active area; and The polysilicon film, a portion of the gate and the active region are metallized to form metal silicide.

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