Open-loop and closed-loop mode selection circuit for capacitive negative-voltage charge pump

Abstract

The invention discloses an open-loop and closed-loop mode selection circuit for a capacitive negative voltage charge pump, which comprises a soft start and reference voltage signal generation circuit, a mode control circuit, a differential operational amplifier circuit and a driving voltage adjustable driving circuit, an enable signal end of the soft start and reference voltage generation circuit is externally connected with an excitation signal of an external drive, a signal output end of the soft start and reference voltage generation circuit is connected with the mode control circuit, and the mode control circuit generates a logic signal and feeds back the logic signal to the soft start and reference voltage generation circuit. Meanwhile, a soft start signal and a feedback signal are selected according to a system working mode and then are sequentially transmitted to the differential operational amplifier circuit and the driving voltage adjustable driving circuit, and the output end of the driving voltage adjustable driving circuit is in control connection with a grid electrode of a third switching power tube in the charge pump circuit. The circuit is suitable for charge pump circuits in open and closed loop modes, and can be suitable for different working scenes. The invention is suitable for the capacitive negative voltage charge pump circuit in any one of the open-loop mode and the closed-loop mode.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuits, relates to starting a chip power supply in an integrated circuit, and specifically relates to an open-loop and closed-loop mode selection circuit for a capacitive negative pressure charge pump. Background Art

[0002] In recent years, with the continuous development of integrated circuits, the application of TFT-LCD has become more and more extensive. In order to generate the power supply voltage required by TFT-LCD, the charge pump circuit is one of the keys. The output ripple, current capability, adjustment accuracy and stability of the charge pump directly affect the picture quality of TFT-LCD. Therefore, domestic and foreign scholars are currently conducting research on charge pumps in full swing. Based on the considerations of low power consumption, low cost and low EMI, the application of charge pumps in integrated circuits is becoming more and more extensive.

[0003] A charge pump is a DC / DC voltage conversion circuit and an important driving component in electronic circuits. It is widely used in power supply circuits of integrated circuits in various fields. The principle of a charge pump is to use the charging and discharging of capacitors to increase the voltage. In practical applications, a charge pump can output a positive input voltage as a negative voltage, that is, a positive-to-negative charge pump; or increase or even double the input voltage. At present, the commonly used charge pump circuit in circuit design is a positive-to-negative charge pump. Its circuit principle is as follows: Figure 1 As shown, the core of the circuit is the fast capacitor C FKY , input capacitor C IN , output capacitor C OUT , and an inverter U and a first switch S1 to a fourth switch S4, wherein the first switch S1 to the fourth switch S4 are switch power tubes, and their turning on and off are controlled by the periodically changing square wave signal input by the front stage of the charge pump and the inverter U, and the switch states always appear in pairs, that is, the opening and closing of the first switch S1 and the second switch S2 are consistent, and the opening and closing of the third switch S3 and the fourth switch S4 are consistent. When the input of the current stage is at a high level, the first switch S1 and the second switch S2 are closed, and the third switch S3 and the fourth switch S4 are disconnected, and the input voltage has an effect on the fast capacitor C FKY When the input of the previous stage is at a low level, the first switch S1 and the second switch S2 are disconnected, the third switch S3 and the fourth switch S4 are closed, and the fast capacitor C FKY For output capacitor C OUT Discharge, and repeat this process.

[0004] At present, most of the negative voltage charge pump chips on the market work in an open-loop system, that is, they can only input voltage VIN and output voltage -VIN, and the output voltage will change with the change of load current. However, with the rapid development of large-scale integrated circuits, the requirements for power supply accuracy are getting higher and higher, and the accuracy requirements for negative voltage charge pumps are also getting higher and higher. This type of chip cannot meet the application that requires high-precision negative voltage, nor can it freely set the output voltage. It is limited in many application scenarios and has poor versatility. In order to solve the problem of unadjustable output voltage, some charge pumps work in a closed-loop system. The output voltage of the charge pump can be adjusted by adjusting the feedback resistor. Although this charge pump design can solve the problem of unadjustable output voltage, the application scenario is relatively single and cannot meet the use requirements of various application scenarios. Therefore, it is urgent to design a new circuit to meet the requirements of the charge pump with adjustable output voltage, output voltage does not change with load current, few peripheral devices, low ripple, and easy integration. Summary of the invention

[0005] The purpose of the present invention is to provide an open-loop and closed-loop mode selection circuit for a capacitive negative pressure charge pump, so as to realize corresponding selection of an open-loop mode or a closed-loop mode in different application scenarios.

[0006] In order to achieve the above object, the technical solution adopted by the present invention is:

[0007] An open-loop and closed-loop mode selection circuit for a capacitive negative voltage charge pump comprises a soft start and reference voltage signal generating circuit for providing a soft start voltage from high to low, a mode control circuit, a differential operational amplifier circuit, and an adjustable drive voltage driving circuit. The enable signal terminal of the soft start and reference voltage generating circuit is externally connected to an externally driven excitation signal, and the soft start signal and two reference voltage signals generated by the soft start and reference voltage generating circuit are respectively connected to the mode control circuit. The mode control circuit generates a logic signal by detecting the value of a feedback signal and feeds it back to the soft start and reference voltage generating circuit. At the same time, the mode control circuit selects the soft start signal and the feedback signal according to the system working mode and transmits them to the differential operational amplifier circuit and the adjustable drive voltage driving circuit in sequence. The output terminal of the adjustable drive voltage driving circuit controls the gate of the third switch power tube connected to the charge pump circuit.

[0008] As a limitation of the soft start and reference voltage signal generating circuit in the present invention: the soft start and reference voltage signal generating circuit includes a soft start voltage signal generating circuit and a reference voltage signal generating circuit, wherein the soft start voltage signal generating circuit and the reference voltage signal generating circuit are connected in parallel, and the input end of the first inverter serves as the enable signal end of the open and closed loop mode selection circuit for the capacitive negative voltage charge pump.

[0009] As a limitation of the soft start voltage signal generating circuit in the present invention: the soft start voltage signal generating circuit includes a first N-channel field effect transistor, a first P-channel field effect transistor, a first Schmidt inverter, and a second inverter. The output end of the first inverter is connected to the gate of the first N-channel field effect transistor, the drain of the first N-channel field effect transistor is connected to the gate of the first P-channel field effect transistor through the first Schmidt inverter and the second inverter, the drain of the first P-channel field effect transistor serves as the feedback signal input end of the open-loop and closed-loop mode selection circuit for the capacitive negative voltage charge pump, and its source outputs the soft start voltage; the sources of the first N-channel field effect transistor and the first P-channel field effect transistor are both grounded.

[0010] As a limitation of the reference voltage signal generating circuit in the present invention: the reference voltage signal generating circuit includes a third inverter, a second N-channel field effect transistor, a second P-channel field effect transistor, a third P-channel field effect transistor, and a resistor network composed of a first resistor to a fourth resistor, the signal output end of the first inverter is respectively connected to the gates of the second P-channel field effect transistor and the third P-channel field effect transistor, the source of the second P-channel field effect transistor is connected to the series circuit of the first resistor and the second resistor, the source of the third P-channel field effect transistor is connected to the series circuit of the third resistor and the fourth resistor, and the series circuit of the first resistor and the second resistor is connected in parallel with the series circuit of the third resistor and the fourth resistor;

[0011] The gate of the first P-channel field effect transistor is connected in series with the third inverter and the OR gate in sequence, and then connected to the gate of the second N-channel field effect transistor. The drain of the second N-channel field effect transistor is connected to the external feedback signal, and its source is connected to the middle node of the series circuit of the third resistor and the fourth resistor; the middle node of the series circuit of the first resistor and the second resistor outputs a first reference voltage, and the middle node of the series circuit of the third resistor and the fourth resistor outputs a second reference voltage; the drains of the first N-channel field effect transistor, the second P-channel field effect transistor, and the third P-channel field effect transistor are respectively connected to the external input voltage.

[0012] As a limitation of the resistor network in the present invention: the first resistor: the second resistor: the third resistor: the fourth resistor in the resistor network = 20:21:18:21.

[0013] As a limitation of the control circuit in the present invention: the mode control circuit includes a feedback voltage selection circuit and a soft start voltage selection circuit, the feedback voltage selection circuit includes a first comparator circuit and a first two-select-one circuit, the negative input end of the first comparator circuit is connected to the first reference voltage output end of the reference voltage signal generating circuit, the output end is connected to the first two-select-one circuit, and the output end generates a logic signal connected to the second input end of the OR gate of the reference voltage signal generating circuit, a static contact of a switch of the first two-select-one circuit is respectively connected to the second reference voltage output end of the reference voltage signal generating circuit, Another static contact is connected to an external feedback signal, and the moving contact outputs a feedback signal after the mode control circuit is selected; the soft start voltage selection circuit includes a second comparator circuit and a second two-to-one circuit, the positive input end of the second comparator circuit is connected to the moving contact of the switch of the first two-to-one circuit, the negative input end is used as a reference 0.26V voltage end, and the output end is connected to the second two-to-one circuit, a static contact of the switch of the second two-to-one circuit is respectively connected to the soft start voltage signal output end of the soft start voltage signal generating circuit, the other static contact is used as a reference 0.25V voltage end, and the moving contact outputs the selected soft start voltage.

[0014] As a limitation of the differential operational amplifier circuit and the driving voltage adjustable driving circuit in the present invention:

[0015] The differential operational amplifier circuit is a two-stage differential operational amplifier, whose positive input terminal inputs the feedback signal after the mode control circuit selects, and whose negative input terminal inputs the soft start signal after the mode control circuit selects;

[0016] The drive voltage adjustable driving circuit includes two source followers connected in series, the input end of the series circuit of the two source followers is connected to the output end of the differential operational amplifier circuit, and the output end signal outputs a V-ADJ drive signal. At the same time, the clock signal end of the drive voltage adjustable driving circuit is controlled by a square wave clock signal with a duty cycle of 50%.

[0017] Due to the adoption of the above technical solution, the present invention has the following technical advances compared with the prior art:

[0018] 1. The present invention proposes an open-loop and closed-loop mode selection circuit for a capacitive negative pressure charge pump, which selects a corresponding output voltage according to the working mode of the charge pump, and can meet the working mode of both the open-loop charge pump circuit and the closed-loop charge pump circuit, effectively solving the problem of poor chip versatility;

[0019] 2. The reference voltage signal generating circuit is designed with a resistor network from the first resistor to the fourth resistor, which can control the internal comparator to make corresponding selections for various reference voltages by judging whether there is an external resistor feedback network, thereby achieving the purpose of controlling different working modes;

[0020] 3. The present invention flexibly selects the working mode without adding peripheral devices and PCB routing of the charge pump circuit, and covers all functions of the two modes of similar chips at home and abroad, which is of great help to the current urgent domestic substitution; dual-mode operation and controllable output voltage greatly improve the versatility and convenience of users in chip selection and use.

[0021] In summary, the open-loop and closed-loop mode selection circuit for a capacitive negative pressure charge pump provided by the present invention is applicable to both open-loop and closed-loop mode charge pump circuits and can be applied to different working scenarios.

[0022] The present invention is applicable to a capacitive negative pressure charge pump circuit in either an open-loop or closed-loop mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0024] Figure 1 The functional principle diagram of the capacitive negative pressure charge pump of the present invention;

[0025] Figure 2 is a circuit schematic diagram of an embodiment of the present invention;

[0026] Figure 3 for Figure 2 The circuit schematic diagram of the soft start and reference voltage signal generating circuit;

[0027] Figure 4 for Figure 2 Circuit diagram of the middle mode control circuit;

[0028] Figure 5 for Figure 4 The circuit schematic diagram of the comparator circuit in FIG.

[0029] Figure 6 for Figure 4 The circuit diagram of the two-choice switch circuit;

[0030] Figure 7 for Figure 2 The circuit schematic of the differential operational amplifier circuit in FIG.

[0031] Figure 8 for Figure 2 The circuit schematic diagram of the driving circuit with adjustable driving voltage;

[0032] Fig. 9 It is an application diagram of a chip when an embodiment of the present invention is applied in an open-loop mode;

[0033] Fig.10 This is the startup curve when the embodiment of the present invention is used in an open loop;

[0034] Fig.11 It is a signal variation diagram of the output drive voltage V-ADJ when the embodiment of the present invention is used in an open loop;

[0035] Fig.12 This is a simulation result diagram of an open-loop operation of an embodiment of the present invention;

[0036] Fig.13 It is a partial periodic diagram of normal operation of the system after the system is started up when the embodiment of the present invention is used in an open loop;

[0037] Fig.14 Application diagram of the chip when the embodiment of the present invention is applied in a closed-loop mode;

[0038] Fig.15 This is the startup curve when the embodiment of the present invention is used in a closed loop;

[0039] Fig.16 This is a signal change diagram of the output drive voltage V-ADJ when the embodiment of the present invention is used in a closed loop;

[0040] Fig.17 This is a simulation result diagram of a closed-loop implementation of the present invention;

[0041] Fig.18 This is a partial period diagram of normal operation of the system after startup when the embodiment of the present invention is used in a closed loop. DETAILED DESCRIPTION

[0042] The present invention is further described in detail below by specific examples. It should be understood that the described examples are only used to explain the present invention, and are not intended to limit the present invention.

[0043] Embodiment: Open-loop and closed-loop mode selection circuit for capacitive negative pressure charge pump

[0044] This embodiment is as follows Figure 2 As shown, it includes a soft start and reference voltage signal generating circuit, a mode control circuit, a differential operational amplifier circuit, and a driving circuit with adjustable driving voltage, which are connected in series in sequence.

[0045] 1. The soft start and reference voltage signal generating circuit can provide a soft start voltage from high to low, and can also provide two reference voltages for the subsequent mode control circuit.

[0046] The soft start and reference voltage signal generating circuit in this embodiment is as follows Figure 3 As shown, it includes a soft start voltage signal generating circuit and a reference voltage signal generating circuit, wherein the soft start voltage signal generating circuit and the reference voltage signal generating circuit are connected in parallel, and the output end of the first inverter INV1 is connected to the soft start voltage signal generating circuit and the reference voltage signal generating circuit respectively.

[0047] Specifically: 1. The soft start voltage signal generating circuit includes a first N-channel field effect transistor MN1, a first P-channel field effect transistor MP1, a first Schmidt inverter SMINV1, and a second inverter INV2. The signal output end of the first inverter INV1 is connected to the gate of the first N-channel field effect transistor MN1. The drain of the first N-channel field effect transistor MN1 is connected to the gate of the first P-channel field effect transistor MP1 through the first Schmidt inverter SMINV1 and the second inverter INV2. The drain of the first P-channel field effect transistor MP1 serves as the feedback signal input end FB of this embodiment, and its source outputs the soft start voltage TR-SS, and the sources of the first N-channel field effect transistor MN1 and the first P-channel field effect transistor MP1 are both grounded. In this embodiment, the source of the first N-channel field effect transistor MN1 is also connected in series with the first capacitor C1 and then grounded, and the source of the first P-channel field effect transistor MP1 is also connected in series with the second capacitor C2 and grounded.

[0048] 2. The reference voltage signal generating circuit includes a third inverter INV3, a second N-channel field effect transistor MN2, a second P-channel field effect transistor MP2, a third P-channel field effect transistor MP3, and a resistor network composed of a first resistor R1 to a fourth resistor R4. The signal output end of the first inverter INV1 is respectively connected to the gates of the second P-channel field effect transistor MP2 and the third P-channel field effect transistor MP3, the source of the second P-channel field effect transistor MP2 is connected to the series circuit of the first resistor R1 and the second resistor R2, the source of the third P-channel field effect transistor MP3 is connected to the series circuit of the third resistor R3 and the fourth resistor R4, and the series circuit of the first resistor R1 and the second resistor R2 is connected in parallel with the series circuit of the third resistor R3 and the fourth resistor R4.

[0049] At the same time, the gate of the first P-channel field effect transistor MP1 is connected in series with the third inverter INV3 and the OR gate OR in sequence, and then connected to the gate of the second N-channel field effect transistor MN2. The drain of the second N-channel field effect transistor MN2 is connected to the external feedback signal input terminal FB, and its source is connected to the middle node of the series circuit of the third resistor R3 and the fourth resistor R4; the middle node of the series circuit of the first resistor R1 and the second resistor R2 outputs the first reference voltage VB1, and the middle node of the series circuit of the third resistor R3 and the fourth resistor R4 outputs the second reference voltage VB2; the drains of the first N-channel field effect transistor MN1, the second P-channel field effect transistor MP1, and the third P-channel field effect transistor MP3 respectively serve as the input voltage terminal VIN of this embodiment.

[0050] 2. The mode control circuit generates a logic signal MODE-CTRL by detecting the value of the external feedback signal FB to select a corresponding reference voltage, thereby controlling the operation of the corresponding system working mode.

[0051] The mode control circuit is as follows Figure 4As shown, it includes a feedback voltage selection circuit and a soft start voltage selection circuit. The feedback voltage selection circuit includes a first comparator circuit CMP1 and a first two-select-one circuit 2S1-1. The positive input terminal of the first comparator circuit CMP1 is also used as the feedback signal input terminal FB of this embodiment to connect the external feedback signal, the negative input terminal is connected to the first reference voltage output terminal VB1 of the reference voltage signal generating circuit, the output terminal is connected to the first two-select-one circuit, and at the same time, the output terminal generates a logic signal MODE-CTRL connected to the second input terminal of the OR gate OR of the reference voltage signal generating circuit. The first static contact A1 of the switch of the first two-select-one circuit 2S1-1 is connected to the second reference voltage output terminal VB2 of the reference voltage signal generating circuit, the second static contact B1 is connected to the external feedback signal FB, and the moving contact C1 outputs the first feedback signal FB-1 of the mode control circuit.

[0052] The soft start voltage selection circuit includes a second comparator circuit CPM2 and a second two-to-one circuit 2S1-2. The positive input end of the second comparator circuit CMP2 is connected to the moving contact C1 of the switch of the first two-to-one circuit 2S1-1, the negative input end serves as the reference 0.26V voltage end of this embodiment, the output end is connected to the second two-to-one circuit 2S1-2, the first static contact A2 of the switch of the second two-to-one circuit 2S1-2 is connected to the soft start voltage signal TR-SS of the soft start voltage signal generating circuit, the second static contact B2 serves as the reference 0.25V voltage end of this embodiment, and the moving contact C2 outputs the selected soft start voltage VREF-EA.

[0053] Furthermore, the first comparator circuit has the same structure as the second comparator circuit, specifically: Figure 5 As shown, it includes the first field effect transistor Q1 to the seventh field effect transistor Q7, the second Schmidt inverter SMINV2, and the fourth inverter INV4. The gates of the second field effect transistor Q1 and the second field effect transistor Q2 are connected to the signal VBP, and the drains are connected to the external input voltage VIN. The source of the first field effect transistor Q1 is connected in series with the bridge circuit of the third field effect transistor Q3 to the sixth field effect transistor Q6 and then grounded. The source of the second field effect transistor Q2 is connected in series with the second Schmidt inverter SMINV2 and the fourth inverter INV4 in sequence and then serves as the output OUT of the comparator amplifier circuit. The bridge circuit formed by the third field effect transistor Q3 to the sixth field effect transistor Q6 is connected in series with the seventh field effect transistor Q7 and forms a parallel circuit with the second field effect transistor Q2 and is also connected to the input end of the Schmidt inverter SMINV2.

[0054] The structures of the first switch circuit 2S1-1 and the second switch circuit 2S1-2 are also the same. Figure 6As shown, it includes a fifth inverter INV5, a fourth P-channel field effect transistor MP4, a fifth P-channel field effect transistor MP5, a third N-channel field effect transistor MN3, and a fourth N-channel field effect transistor MN4, wherein the external excitation signal EN is connected to the gates MN3 of the fourth P-channel field effect transistor MP4 and the third N-channel field effect transistor respectively after passing through the fifth inverter INV5, and the drain of the fourth P-channel field effect transistor MP4 is connected to the drain of the third N-channel field effect transistor MN3 as the first / second switch circuit 2S1-1 / The first static contact A1 / A2 of 2S1-2, the drain of the fifth P-channel field effect transistor MP5 and the drain of the fourth N-channel field effect transistor MN4 are connected to serve as the second static contact C1 / C2 of the first / second switch circuit 2S1-1 / 2S1-2, and the source of the fourth P-channel field effect transistor MP4, the third N-channel field effect transistor MN3, the fifth P-channel field effect transistor MP5, and the fourth N-channel field effect transistor MN4 are connected to serve as the moving contact B1 / B2 of the first / second switch circuit 2S1-1 / 2S1-2.

[0055] 3. The differential operational amplifier circuit is a two-stage differential operational amplifier, whose positive input terminal inputs the feedback signal after the mode control circuit is selected, and whose negative input terminal inputs the soft start signal after the mode control circuit is selected. The specific circuit is as follows Figure 7 As shown, it includes the eighth field effect transistor Q8 to the twelfth field effect transistor Q16, the resistor R C , capacitor C C, a third capacitor C3, the eighth field effect transistor Q8 to the eleventh field effect transistor Q11 constitute a first bridge circuit, the twelfth field effect transistor Q12 to the fifteenth field effect transistor Q15 constitute a second bridge circuit, that is, the drain of the eighth field effect transistor Q8 is connected to the drain of the tenth field effect transistor Q10, the drain of the ninth field effect transistor Q9 is connected to the drain of the eleventh field effect transistor Q11 and is grounded, the source of the eighth field effect transistor Q8 is connected to the source of the ninth field effect transistor Q9, the source of the tenth field effect transistor Q10 is connected to the source of the eleventh field effect transistor Q11, the gate of the eighth field effect transistor Q8 inputs the selected soft start voltage VREF-EA, the gate of the tenth field effect transistor Q10 inputs the first feedback signal FB-1, and the gates of the ninth field effect transistor Q9 and the tenth field effect transistor Q10 are both connected to their own sources; the twelfth field effect transistor Q8 in the second bridge circuit is connected to the drain of the tenth field effect transistor Q10 and the drain of the eleventh field effect transistor Q11; The gate of the field effect transistor Q12 is connected to the gate of the fourteenth field effect transistor Q14, the drain of the twelfth field effect transistor Q12 is connected to the drain of the fourteenth field effect transistor Q14, the source of the twelfth field effect transistor Q12 is connected to the drain of the thirteenth field effect transistor Q13, the source of the thirteenth field effect transistor Q13 is connected to the source of the fifteenth field effect transistor Q15 and is grounded, and after the source of the fourteenth field effect transistor Q14 is connected to the drain of the fifteenth field effect transistor Q15, it serves as the output end of the differential operational amplifier circuit and outputs the signal VEA; the gate of the thirteenth field effect transistor Q13 is connected to the middle node where the sources of the eighth field effect transistor Q8 and the ninth field effect transistor Q9 in the first bridge circuit are connected, and the gate of the fifteenth field effect transistor Q15 is connected to the middle node where the sources of the tenth field effect transistor Q10 and the eleventh field effect transistor Q11 in the first bridge circuit are connected. The drain of the sixteenth field effect transistor Q16 is connected to the middle node of the circuit connecting the drain of the twelfth field effect transistor Q12 and the drain of the fourteenth field effect transistor Q14 in the second bridge circuit, the drain of the sixteenth field effect transistor Q16 is connected to the middle node of the drain of the eighth field effect transistor Q8 and the tenth field effect transistor Q10 in the first bridge circuit, and the gate of the sixteenth field effect transistor Q16 is input with the signal VBP. In addition, the resistor R C With capacitor C C After being connected in series, a parallel circuit is formed with the third capacitor C3, and the source of the fourteenth field effect transistor Q14 and the drain of the fifteenth field effect transistor Q15 are grounded.

[0056] When it is detected that the charge pump circuit is in an open-loop working mode, there is no feedback signal FB input in this embodiment. At this time, the input voltage difference between the two ends of the secondary differential operational amplifier is large and has no adjustment function. At this time, the error amplifier is equivalent to a comparator with a large capacitor connected to the output. The output VEA is fixed to a large voltage value. During the working cycle, the switch power tube NPOWER1 of the third switch in the charge pump circuit is operated in the linear region, and the entire system operates in the open-loop mode; when it is detected that the charge pump circuit is in a closed-loop working mode, there is a feedback signal FB input in this embodiment to form a negative feedback system. At this time, the voltage difference between the feedback signal FB and the reference signal is small. The circuit amplifies the voltage difference between the feedback signal and the reference signal, and the output VEA can adjust the size of the driving signal. During the working cycle, the switch power tube NPOWER1 of the third switch in the charge pump circuit is operated in the saturation region, and the VDS of the switch power tube NPOWER1 of the third switch in the charge pump circuit is controlled, thereby achieving the purpose of adjusting the output VOUT, and the entire system operates in the closed-loop mode.

[0057] 4. Driving voltage adjustable driving circuit. The function of the driving voltage adjustable driving circuit in this embodiment is mainly to convert the VEA voltage into the gate voltage when the switching power tube NPOWER1 of the third switch in the driving charge pump circuit is turned on through two source followers and to allow the output signal V-ADJ to have driving capability. At the same time, the clock signal terminal OSC is logically controlled by a square wave clock signal with a duty cycle of 50%, and does not affect the normal operation of the system.

[0058] The specific circuit is as follows Figure 8 As shown, it includes seventeenth field effect transistors Q17 to twenty-third field effect transistors Q23, a sixth P-channel field effect transistor MP6, a seventh P-channel field effect transistor MP7, a fifth N-channel field effect transistor MN5, a sixth N-channel field effect transistor MN6, and a sixth inverter INV6, the gate of the seventeenth field effect transistor Q17 is connected to the gate of the eighteenth field effect transistor Q18, the source of the seventeenth field effect transistor Q17 is connected to the drain of the eighteenth field effect transistor Q18 and then connected to the drains of the fifth N-channel field effect transistor MN5 and the sixth N-channel field effect transistor MN6 respectively; the nineteenth field effect transistor Q17 is connected to the gate of the eighteenth field effect transistor Q18, the source of the seventeenth field effect transistor Q17 is connected to the drain of the eighteenth field effect transistor Q18 and then connected to the drains of the fifth N-channel field effect transistor MN5 and the sixth N-channel field effect transistor MN6 respectively; The gate of the transistor Q19 is connected to the gate of the twentieth field effect transistor Q20, the source of the nineteenth field effect transistor Q19 is connected to the external input signal VIN and is also connected to its own gate, the drain of the twentieth field effect transistor Q20 is connected to the drain of the seventeenth field effect transistor Q17, the drain of the nineteenth field effect transistor Q19, the source of the twentieth field effect transistor Q20, the source of the sixth P-channel field effect transistor MP6, the source of the twenty-first field effect transistor Q21, the source of the twenty-second field effect transistor Q22, the source of the seventh P-channel field effect transistor, and the source of the twenty-third field effect transistor Q23.

[0059] The gate of the sixth P-channel field effect transistor MP6 is connected to the output signal VEA of the differential operational amplifier circuit, and is also connected to the gate of the fifth N-channel field effect transistor MN5. The drain of the sixth P-channel field effect transistor MP6 is connected to the source of the eighteenth field effect transistor Q18, and is also connected to the gate of the sixth N-channel field effect transistor MN6. The source of the fifth N-channel field effect transistor MN5 is connected to the drain of the twenty-first field effect transistor Q21, and is also connected to the gate of the seventh P-channel field effect transistor MP7. The gate of the twenty-first field effect transistor Q21 is connected to the gate of the twentieth field effect transistor Q20. The input end of the sixth inverter INV6 serves as the clock signal end of this embodiment, and a square wave clock signal with a duty cycle of 50% is input during operation. The output end of the sixth inverter INV6 is respectively connected to the gates of the twenty-second field effect transistor Q22 and the twenty-second and third field effect transistor Q23, and the drain of the seventh P-channel field effect transistor MP7, the source of the sixth N-channel field effect transistor, and the drain of the twenty-third field effect transistor Q23 are connected to output a signal V-ADJ for driving the third switch in the charge pump circuit. The signal V-ADJ controls the gate of the third switch power tube connected to the charge pump circuit.

[0060] The working principle of this embodiment is as follows: when the external excitation signal EN in the soft start and reference voltage signal generating circuit is at a high level, the charge pump circuit works normally. When the external excitation signal EN changes from a low level to a high level, the signal ENN is at a low level, the first N-channel field effect transistor MN1 is turned off, the constant current I1 continuously charges the first capacitor C1, and the voltage EN-1 on the first capacitor C1 rises linearly to a high level at a certain slope, so the external excitation signal EN and the signal EN-1 have a delay time of tens of microseconds, and then pass through the first Schmidt inverter SMINV1 and the second inverter INV2 to prevent the signal from having a logic jump at the critical value, and obtain the EN-A signal. When the external excitation signal EN changes from low to high, the EN-A signal is always guaranteed to have a low level of tens of microseconds when the system starts, and this level keeps the second P-channel field effect transistor MP2 on for tens of microseconds when it starts, so that the voltage of the external feedback signal FB is equal to the soft start voltage TR-SS. After the delay time ends, the soft start voltage TR-SS slowly decreases at a fixed slope under the action of the constant current source I2 until it reaches zero. The function of the soft start voltage TR-SS signal is to prevent overshoot current when the system starts. If the overshoot current is too large, it will damage the circuit chip. It is worth noting that the soft start of this embodiment is different from the previous one. Since the output voltage VOUT is from zero to negative, the soft start voltage TR-SS must also be from high to low.

[0061] When the external excitation signal EN changes from low level to high level, ENN is low level, making the second P-channel field effect transistor MP2 and the third P-channel field effect transistor MP3 conductive, and the resistor network composed of the first resistor R1 to the fourth resistor R4 conductive. The value of the second reference voltage VB2 in open-loop mode is defined as VB2open, and the value of the second reference voltage VB2 in closed-loop operation is defined as VB2loop. When the charge pump chip works in open-loop mode, according to the resistance voltage division law:

[0062]

[0063]

[0064] , as shown in formula (4), the external feedback signal FB is not affected by the second reference voltage VB2. Wherein the resistor bridge satisfies R1: R2: R3: R4 = 20: 21: 18: 21. In this embodiment, the circuit takes R1 = 2MΩ, R2 = 2.1MΩ, and R3 = 1.8MΩ. When the charge pump circuit is in closed-loop mode, the first reference voltage VB1 remains unchanged, and the value of the external feedback signal FB is divided into two stages. In the closed-loop mode, the second reference voltage VB2loop and the external feedback signal FB are based on the resistor voltage division law:

[0065]

[0066]

[0067] During the conduction phase of the second N-channel field effect transistor MN2, the external feedback signal FB is affected by VB2. According to formula (3), FB = VB2loop; during the disconnection phase of the second N-channel field effect transistor MN2, R4 = 2.1MΩ. It is known that when the charge pump is in closed-loop operation, VIN = 3.3 ~ 5V, VOUT = -2.5 ~ -4.5, RF1 = 100kΩ, RF2 = 58kΩ ~ 100kΩ (RF1, RF2 are external chip feedback resistors). The resistance values ​​of RF1 and RF2 are much smaller than those of R3 and R4, so VB 2loop ≈FB.

[0068] The above resistor value ratio is to make the first reference voltage VB1 and the second reference voltage VB2 positive voltages; taking a larger resistance value is to reduce power consumption. It is known that the output voltage signal VOUT of the charge pump is a negative voltage, and the absolute value of the output voltage signal VOUT is always less than the input voltage VIN. Therefore, according to the above formula, when the charge pump circuit is open-loop, VB2open>VB1>0, and VB2open>0.26V; when the charge pump circuit is closed-loop, VB1>VB2loop>0, that is, VB1>FB>0.

[0069] Since there is a VIN undervoltage protection circuit in the chip in the prior art, no matter whether the input voltage VIN is powered on first or the external excitation signal EN is powered on first, the chip will wait until the VIN signal end is powered on before it starts to work normally. Figure 2 When the first P-channel field effect transistor MP1 is turned on, the source-drain voltage is very small), so TR-SS≈FB when the charge pump circuit is started.

[0070] When the charge pump circuit is used in an open loop, FB = VIN·R4 / (R3+R4) is always present when the embodiment is started; when the charge pump circuit is used in a closed loop, FB = VIN·RF2 / (RF1+RF2) is always present when the embodiment is started. Regardless of whether the circuit is open-loop or closed-loop, TR-SS≈FB is always present before the chip is started, and is always greater than 1.2V.

[0071] When the charge pump circuit is used in an open loop, there is no external feedback signal FB, so the feedback signal input terminal FB in this embodiment is used as a chip pin and is left floating. When starting, the signal EN-B is always at a high level for tens of microseconds, and the second N-channel field effect transistor MN2 is turned on for a period of time through the OR gate OR, so that FB = VB2open. It is known that VB2open>VB1, so FB>VB1, if Figure 4 The CMP1 comparator outputs the logic signal MODE-CTRL at a high level, further keeping MN2 on and FB = VB2open. Figure 4 The logic signal MODE-CTRL is at a high level to control the first two-selection circuit 2S1-1 to select FB-1=VB2open=FB, and FB-1>0.26V, so the output voltage CMP-OUT of the second comparator circuit CMP2 is always at a high level, so that VREF-EA=TR-SS.

[0072] The soft start signal TR-SS and the external feedback FB signal are respectively selected by two selection circuits as the voltage signal VREF-EA and the selected feedback voltage signal FB-1, and transmitted to the two input terminals of the differential operational amplifier circuit. As the chip starts to work, the soft start voltage TR-SS decreases at a fixed slope, and the feedback signal FB also decreases with the decrease of the output voltage signal VOUT, and the falling slopes of the two signals are almost the same. At this time, the voltage difference between the soft start voltage VREF-EA and the selected feedback voltage FB-1 is small, and the output voltage VEA of the differential operational amplifier circuit will rise slowly, avoiding the startup overshoot current, until the voltage FB-1 drops to VIN-(VIN-VOUT)·R4 / (R3+R4) and no longer decreases, and the soft start voltage VREF-EA will drop to 0V. At this time, the voltage difference at the input terminal of the differential operational amplifier circuit is getting larger and larger. When it cannot meet the virtual short condition, the voltage VEA will be pulled to VIN, completing the soft start and operating the chip normally. Therefore, when the charge pump circuit is used in an open loop, the working curves of the soft start voltage VREF-EA, the voltage FB-1, and the output voltage VEA of the differential operational amplifier circuit in the open loop operation of the charge pump in this embodiment are as follows: Fig.10 shown.

[0073] The output voltage VEA of the differential operational amplifier circuit is converted into a V-ADJ signal with driving capability by the adjustable driving voltage driving circuit. The high level voltage of V-ADJ is VIN-VGSMN5+VGSMP7. Under the control of the charge pump pre-stage input signal OSC signal, V-ADJ will be as follows Fig.11 The square wave signal shown controls the on and off of the third switch power tube NPOWER1 in the charge pump circuit. At this time, during the periodic conduction time of the third switch power tube NPOWER1 in the charge pump circuit, the V-ADJ signal makes the third switch power tube NPOWER1 in the charge pump circuit work in the linear region. The existence of the fifth resistor R5 prevents VEA-1 from being pulled down to 0 when OSC=0, which helps to increase the conduction time of NPOWER1 in the next cycle.

[0074] When used in open loop, the chip application diagram is as follows Fig. 9 , the positive-to-negative charge pump chip input VIN is 5V, Rload = 500Ω, and the output is slightly greater than -5V. The simulation results of this embodiment in open loop are shown in the figure Fig.12 As shown. Fig.13It can be seen that when the external feedback signal FB is floating, the system starts working in 100uS (the external excitation EN level changes from low to high), and the logic signal MODE-CTRL is always high. FB-1 and the soft start voltage VREF-EA signal are used as the input of the differential operational amplifier circuit. They first decrease with the same initial value and the same slope. During this period, the voltage difference between the two ends is small, and the output voltage VEA of the differential operational amplifier circuit rises slowly; until about 220uS, FB-1 drops to about 0.4V and no longer decreases, while the soft start signal VREF-EA will drop to 0V. At this time, the voltage difference is large, making the output voltage VEA of the differential operational amplifier circuit 5V. At this time, the high level voltage of the driving voltage V-ADJ is VIN-VGSMN5+VGSMP7, so that the power tube NPOWER1 of the third switch in the charge pump circuit works in the linear region when it is turned on. At this time, the value of VOUT is determined by the voltage drop caused when switches S1, S2, S3, and S4 are turned on (the voltage drop is related to the on-resistance of the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 in the charge pump circuit and the load current).

[0075] When the charge pump circuit is used in a closed loop, the application diagram of this embodiment is as shown in FIG. Fig.14 As shown, the VOUT value is set by the external feedback resistor network RF1 and RF2. At this time, the charge pump chip input voltage is 5V, RF1 = 100kΩ, RF2 = 74.74kΩ, Rload = 33Ω, and the output is -3.3V. The simulation results used in this embodiment are shown in the figure below. Fig.17 As shown. At this time, FB is used as a chip pin, and FB has a feedback signal input. When starting, it is the same as the open-loop working mode. EN-B is always high for tens of microseconds. The second N-channel field effect transistor MN2 is turned on for a period of time through the OR gate, so that FB=VB2loop. Since VB1>VB2loop, Figure 4 The output MODE-CTRL of the CMP1 comparator is low, MN2 disconnects FB≠VB2loop, VB1>FB, the MODE-CTRL signal is always low, and the 2-to-1 circuit (2S1) is controlled to always select FB-1=FB, and VB2loop is abandoned. When FB-1>0.26V, the output CMP-OUT of CMP2 is high, making VREF-EA=TR-SS; when FB decreases to below 0.26V with VOUT, the output CMP-OUT of CMP2 is low, making VREF-EA=0.25V, and FB-1 is locked at 0.25V under the action of negative feedback and no longer decreases. VOUT will also be locked at the set voltage value and no longer decrease.

[0076] TR-SS, 0.25V and FB signals are selected by two selectors as VREF-EA and FB-1 respectively and transmitted to the two input terminals of the error amplifier. Figure 5 . As the chip starts to work, the TR-SS voltage decreases at a fixed slope, and the FB voltage also decreases as VOUT decreases, and the falling slopes of the two signals are almost the same. At this time, the voltage difference between VREF-EA and FB-1 is small, and the output VEA of the error amplifier will rise slowly, avoiding startup overshoot current, until FB-1 drops below 0.26V, the CMP2 output signal CMP-OUT is low, and VREF-EA will switch from TR-SS to 0.25V reference voltage and no longer change. Under the action of the negative feedback system, FB-1 is locked at around 0.25V and no longer decreases, and the voltage difference between VREF-EA and FB-1 remains very small. The VEA voltage has been maintained at an intermediate value, completing the soft start and operating the chip normally, such as Fig.15 .

[0077] At this time, the output voltage VEA of the differential operational amplifier circuit is converted into a V-ADJ signal with driving capability through the adjustable driving voltage driving circuit. When V-ADJ is at a high level, the voltage is VEA+VGSMP6-VGSMN6. Under the control of the OSC signal, V-ADJ will be as follows Fig.16 The square wave signal shown controls the on and off of the third switch power tube NPOWER1 in the charge pump circuit. At this time, during the periodic conduction time of the third switch power tube NPOWER1 in the charge pump circuit, the V-ADJ signal makes NPOWER1 work in the saturation region. The existence of R5 prevents VEA-1 from being pulled down to 0 when the previous stage input OSC=0, which helps to increase the conduction time of the third switch power tube NPOWER1 in the charge pump circuit in the next cycle.

[0078] Depend on Fig.18It can be seen that when the FB port of this embodiment has a feedback signal provided by the external feedback resistor network RF1 and RF2, the system starts working at 100uS (the external excitation EN level changes from low to high), and the logic signal MODE-CTRL signal is always at a low level. FB-1 and the soft start voltage VREF-EA signal, as the input end of the differential operational amplifier circuit, first decrease with almost the same initial value and the same slope. During this period, the voltage difference between the two ends is small, and the output voltage VEA of the differential operational amplifier circuit rises slowly; until about 700uS, when the external feedback signal FB drops to about 0.26V, the internal comparator will control VREF-EA = 0.25V reference voltage, and the FB-1 voltage will also be fixed at about 0.25V under the action of negative feedback. From the beginning to the end, the voltage difference between the two ends of the input of the differential operational amplifier circuit is small, and the value of the output voltage VEA of the differential operational amplifier circuit is locked at an intermediate value. At this time, the high level voltage of the driving voltage V-ADJ is VEA+VGSMP6-VGSMN6, so that the third switch power NPOWER1 in the charge pump circuit works in the saturation area when it is turned on. At this time, the value of the output voltage VOUT is determined by the ratio of the feedback resistors RF1 and RF2.

Claims

1. An open-loop and closed-loop mode selection circuit for a capacitive negative pressure charge pump, characterized in that: It includes a soft start and reference voltage signal generating circuit that provides a soft start voltage from high to low, a mode control circuit, a differential operational amplifier circuit, and an adjustable drive voltage driving circuit. The enable signal terminal of the soft start and reference voltage generating circuit is externally connected to an externally driven excitation signal, and the soft start signal and two reference voltage signals generated by the soft start and reference voltage generating circuit are respectively connected to the mode control circuit. The mode control circuit generates a logic signal by detecting the value of the feedback signal and feeds it back to the soft start and reference voltage generating circuit. At the same time, the mode control circuit selects the soft start signal and the feedback signal according to the system working mode and transmits them to the differential operational amplifier circuit and the adjustable drive voltage driving circuit in sequence. The output terminal of the adjustable drive voltage driving circuit controls the gate of the third switch power tube connected to the charge pump circuit.

2. The open-loop and closed-loop mode selection circuit for a capacitive negative pressure charge pump according to claim 1, characterized in that: The soft start and reference voltage signal generating circuit includes a soft start voltage signal generating circuit and a reference voltage signal generating circuit, wherein the soft start voltage signal generating circuit and the reference voltage signal generating circuit are connected in parallel, and the input end of the first inverter serves as the enable signal end of the open and closed loop mode selection circuit for the capacitive negative voltage charge pump.

3. The open-loop and closed-loop mode selection circuit for a capacitive negative pressure charge pump according to claim 2, characterized in that: The soft-start voltage signal generating circuit includes a first N-channel field effect transistor, a first P-channel field effect transistor, a first Schmidt inverter, and a second inverter. The output end of the first inverter is connected to the gate of the first N-channel field effect transistor. The drain of the first N-channel field effect transistor is connected to the gate of the first P-channel field effect transistor through the first Schmidt inverter and the second inverter. The drain of the first P-channel field effect transistor serves as the feedback signal input end of the open-loop and closed-loop mode selection circuit for the capacitive negative voltage charge pump, and its source outputs the soft-start voltage. The sources of the first N-channel field effect transistor and the first P-channel field effect transistor are both grounded.

4. The open-loop and closed-loop mode selection circuit for a capacitive negative pressure charge pump according to claim 3, characterized in that: The reference voltage signal generating circuit includes a third inverter, a second N-channel field effect transistor, a second P-channel field effect transistor, a third P-channel field effect transistor, and a resistor network composed of a first resistor to a fourth resistor, wherein the signal output end of the first inverter is respectively connected to the gates of the second P-channel field effect transistor and the third P-channel field effect transistor, the source of the second P-channel field effect transistor is connected to a series circuit of the first resistor and the second resistor, the source of the third P-channel field effect transistor is connected to a series circuit of the third resistor and the fourth resistor, and the series circuit of the first resistor and the second resistor is connected in parallel with the series circuit of the third resistor and the fourth resistor; The gate of the first P-channel field effect transistor is connected in series with the third inverter and the OR gate in sequence, and then connected to the gate of the second N-channel field effect transistor. The drain of the second N-channel field effect transistor is connected to the external feedback signal, and its source is connected to the middle node of the series circuit of the third resistor and the fourth resistor; the middle node of the series circuit of the first resistor and the second resistor outputs a first reference voltage, and the middle node of the series circuit of the third resistor and the fourth resistor outputs a second reference voltage; the drains of the first N-channel field effect transistor, the second P-channel field effect transistor, and the third P-channel field effect transistor are respectively connected to the external input voltage.

5. The open-loop and closed-loop mode selection circuit for a capacitive negative pressure charge pump according to claim 4, characterized in that: In the resistor network, the first resistor: the second resistor: the third resistor: the fourth resistor=20:21:18:

21.

6. The open-loop and closed-loop mode selection circuit for a capacitive negative pressure charge pump according to claim 4 or 5, characterized in that: The mode control circuit includes a feedback voltage selection circuit and a soft start voltage selection circuit. The feedback voltage selection circuit includes a first comparator circuit and a first two-select-one circuit. The negative input terminal of the first comparator circuit is connected to the first reference voltage output terminal of the reference voltage signal generating circuit, and the output terminal is connected to the first two-select-one circuit. At the same time, the output terminal generates a logic signal connected to the second input terminal of the OR gate of the reference voltage signal generating circuit. A static contact of the switch of the first two-select-one circuit is respectively connected to the second reference voltage output terminal of the reference voltage signal generating circuit, and another static contact is connected to the external feedback signal. The moving contact outputs the feedback signal selected by the mode control circuit; the soft start voltage selection circuit includes a second comparator circuit and a second two-select-one circuit. The positive input terminal of the second comparator circuit is connected to the moving contact of the switch of the first two-select-one circuit, the negative input terminal is used as a reference 0.26V voltage terminal, and the output terminal is connected to the second two-select-one circuit. A static contact of the switch of the second two-select-one circuit is respectively connected to the soft start voltage signal output terminal of the soft start voltage signal generating circuit, and another static contact is used as a reference 0.25V voltage terminal. The moving contact outputs the selected soft start voltage.

7. The open-loop and closed-loop mode selection circuit for a capacitive negative pressure charge pump according to claim 6, characterized in that: The differential operational amplifier circuit is a two-stage differential operational amplifier, whose positive input terminal inputs the feedback signal after the mode control circuit selects, and whose negative input terminal inputs the soft start signal after the mode control circuit selects; The driving voltage adjustable driving circuit includes two source followers connected in series, the input end of the series circuit of the two source followers is connected to the output end of the differential operational amplifier circuit, and the output end signal outputs a V-ADJ driving signal. At the same time, the clock signal end source follower of the driving voltage adjustable driving circuit is controlled by a square wave clock signal with a duty cycle of 50%.

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