Crystal oscillation circuit
By designing a crystal oscillation circuit that contains bias current generates circuit, bias circuit, oscillator, detection and adjustment circuit and sampling unit, the problem of high power consumption in low -power application scenarios in low -power application scenarios is solved. A low -power crystal oscillator circuit is achieved.
Patent Information
- Application Number
- CN202411470076.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-21
- Publication Date
- 2025-01-28
AI Technical Summary
Existing crystal oscillators consume high power in low-power application scenarios, making it difficult to meet the needs of applications such as low-power wearable systems and quartz watches.
A crystal oscillating circuit is designed to produce a combination of circuits, bias circuits, oscillations, detection and adjustment circuits and sampling units through bias current to achieve real -time adjustment and reduction of power consumption of bias current.
The bias current is adjusted by negative feedback, and the low -power operation of the crystal oscillator is realized, reducing the power consumption of the crystal oscillator, and suitable for applications such as low -power wearable systems and quartz watches.
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Figure CN119382627A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a crystal oscillator circuit. Background Art
[0002] Crystal Oscillator (XO) uses quartz crystal (Crystal, XTAL) and negative resistance circuit to generate a highly stable periodic low-noise clock. Compared with LC oscillators and ring oscillators, crystal oscillators have the advantages of small frequency drift (temperature drift of tens of ppm in the full temperature range) and good phase noise. Therefore, crystal oscillators are often used as reference clocks for electronic systems.
[0003] In integrated circuits (ICs), the commonly used negative resistance circuit is the Pierce oscillator, such as Figure 1 As shown, IB represents the bias current source, RB is the bias resistor (usually with a large resistance), and VB represents the bias voltage. The Pierce oscillator provides transconductance gm through a single transistor MN, and with load capacitors CL1 and CL2, it can provide negative resistance NR for the quartz crystal XTAL (the capacitor introduced by the crystal XTAL is C1). Through the small signal model, the negative resistance formula can be obtained as follows:
[0004] NR= -gm / (CL1*CL2*ω 2 ) (1)
[0005] Where ω is the oscillation angular frequency. In order to minimize power consumption, CL1 = CL2.
[0006] Since both pins of the quartz crystal XTAL need to be connected to the chip, the Pierce oscillator is usually called a Two-Pin crystal oscillator.
[0007] In many electronic devices, chip area directly affects cost and expenses. Therefore, the fewer pins, the better. One-pin oscillators are born. The JSSC paper published by J. Santos and R. Meyer in 1984 proposed "A One-Pin Oscillator for VLSI Circuits", IEEE J. Solid-State Circuits, vol. SC-19, pp. 228-236, April, 1984." Therefore, this type of crystal oscillator is also called Santos oscillator.
[0008] like Figure 2As shown, the one-pin type Pierce oscillator uses a PMOS transistor MP to provide transconductance gm. It can be seen that one end of the quartz crystal XTAL is grounded (it may not be connected to the chip), and the other end is connected to the gate of the PMOS transistor MP, thereby reducing the use of one pin of the chip. The load capacitor CL1 is connected across the gate and source of the transistor MP, and one end of the load capacitor CL2 is connected to the source and the other end is grounded.
[0009] In order to maintain stability, the absolute value of the negative resistance |NR| must be greater than the equivalent resistance Rs of the quartz crystal XTAL to achieve rapid start-up and ensure oscillation under different process angles. Since the oscillation frequency ω is determined by the system indicators, and CL1 and CL2 are determined by the cutting characteristics of the quartz crystal XTAL, in order to meet the requirements of the negative resistance NR, the transconductance gm can only be increased, and increasing the transconductance gm means increasing the bias current IB, thereby increasing the system power consumption. For example, a 32.768kHz crystal oscillator usually has a current consumption of several uA due to its small oscillation frequency ω, while a 26MHz crystal oscillator usually has a current consumption of mA.
[0010] Reducing the power consumption of crystal oscillators is of great significance, especially for low-power wearable systems and quartz watches. How to reduce the power consumption of crystal oscillators has become a research direction for many years.
[0011] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention
[0012] The object of the present invention is to provide a crystal oscillator circuit which can reduce its own power consumption.
[0013] In order to achieve the above objective, a specific embodiment of the present invention provides a crystal oscillator circuit, including: a bias current generating circuit, a bias circuit, an oscillator, a detection and adjustment circuit, and a sampling unit.
[0014] The bias current generating circuit is used to generate a bias current based on a first control voltage; the bias circuit is used to generate a bias voltage based on the bias current; the oscillator is used to generate an oscillation signal based on the bias voltage and the bias current; the detection and adjustment circuit is used to generate a second control voltage based on the oscillation signal and the bias current; and the sampling unit is used to sample a DC component in the second control voltage to generate a first control voltage.
[0015] In one or more embodiments of the present invention, the bias current generating circuit includes a first transistor, a first resistor and an output unit, wherein the control end of the first transistor is connected to the sampling unit to receive a first control voltage, the first end of the first transistor is connected to the first resistor, and the second end of the first transistor is connected to the output unit, and the output unit is used to output one or more bias currents.
[0016] In one or more embodiments of the present invention, the bias circuit includes a second resistor connected to the bias current generating circuit and the oscillator to generate a bias voltage based on the bias current.
[0017] In one or more embodiments of the present invention, the oscillator includes a first bias resistor, a crystal, a first load capacitor, a second load capacitor and a second transistor; the first end of the first bias resistor is connected to the bias circuit to receive a bias voltage, the second end of the first bias resistor is connected to the control end of the second transistor, the first end of the first load capacitor is connected to the control end of the second transistor, the second end of the first load capacitor is connected to the first end of the second transistor and the bias current generating circuit to receive the bias current, the first end of the second load capacitor is connected to the first end of the second transistor, the second end of the second load capacitor is connected to the second end of the second transistor, the first end of the crystal is connected to the control end of the second transistor and the detection and adjustment circuit to generate an oscillation signal, and the second end of the crystal is connected to the ground voltage.
[0018] In one or more embodiments of the present invention, the detection and adjustment circuit includes: an isolation unit, a second bias resistor and a third transistor, the first end of the isolation unit is connected to the first end of the crystal to receive an oscillation signal, the second end of the isolation unit is connected to the control end of the third transistor and the first end of the second bias resistor to generate a second control voltage, and the second end of the second bias resistor is connected to the second end of the third transistor and the bias current generating circuit.
[0019] In one or more embodiments of the present invention, the detection and regulation circuit further includes a startup unit, and the startup unit is connected to the second end of the third transistor to provide a startup current.
[0020] In one or more embodiments of the present invention, the detection and adjustment circuit further includes a first capacitor, a first end of the first capacitor is connected to the second end of the third transistor, and a second end of the first capacitor is connected to a ground voltage.
[0021] In one or more embodiments of the present invention, the sampling unit includes a third resistor and a second capacitor, the first end of the third resistor is connected to the detection and adjustment circuit to receive the second control voltage, the second end of the third resistor is connected to the first end of the second capacitor and the bias current generating circuit to output the first control voltage, and the second end of the second capacitor is connected to the ground voltage.
[0022] In one or more embodiments of the present invention, the output unit includes a current mirror, which is connected to the second end of the first transistor, the bias circuit, the oscillator and the detection and adjustment circuit, and the current mirror is used to output three bias currents respectively provided to the bias circuit, the oscillator and the detection and adjustment circuit.
[0023] In one or more embodiments of the present invention, the bias current generating circuit includes a third capacitor, a first terminal of the third capacitor is connected to the second terminal of the first transistor, and a second terminal of the third capacitor is connected to the ground voltage.
[0024] Compared with the prior art, the crystal oscillator circuit of the present invention generates a bias current based on a first control voltage through a bias current generating circuit, generates a bias voltage based on the bias current through a bias circuit, generates an oscillation signal based on the bias voltage and the bias current through an oscillator, generates a second control voltage with a superimposed DC component and an AC component based on the oscillation signal and the bias current through a detection and adjustment circuit, and adjusts the DC component in real time based on a fixed bias current, and generates a first control voltage by sampling the DC component in the second control voltage through a sampling unit, thereby adjusting the bias current in the form of negative feedback to achieve low power consumption; the bias voltage generated by the bias circuit can adjust the DC bias point of the oscillator, so that the oscillator is not easy to enter the linear region, and at the same time, the trough of the oscillation signal will not reach a large negative voltage to cause the electrostatic ESD diode to be misconnected. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0026] Figure 1 It is a Two-Pin (dual-pin) Pierce oscillator in the prior art.
[0027] Figure 2 It is a One-Pin (single pin) Pierce oscillator in the prior art.
[0028] Figure 34 is a circuit diagram of a crystal oscillator in one embodiment.
[0029] Figure 4 FIG. 4 is a signal waveform diagram of a crystal oscillator in an embodiment. DETAILED DESCRIPTION
[0030] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.
[0031] "Coupled" or "connected" or "connected" in the specification includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrically conductive medium, which may have parasitic inductance or parasitic capacitance; indirect connection may also include connection through other active or passive devices on the basis of achieving the same or similar functional purposes, such as connection through circuits or components such as switches and follower circuits. In addition, in the invention, words such as "first" and "second" are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply that there is a certain actual relationship, quantity or order between these technical features.
[0032] In the detailed description of the specification, reference is made to the accompanying drawings forming a part thereof, wherein like reference numerals refer to like parts throughout, and wherein are shown by way of exemplary embodiments that may be implemented. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be considered in a limiting sense.
[0033] The various operations in the specification may be described in turn as multiple discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be interpreted as implying that these operations must be order-dependent. Specifically, these operations may not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. Various additional operations may be performed and / or the described operations may be omitted in additional embodiments.
[0034] For purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).
[0035] Various components and devices may be referred to or shown in the singular form herein (e.g., "transistor," "transistor," "switch," etc.), but this is merely for ease of discussion, and any element referred to in the singular form may include multiple such elements in accordance with the teachings herein.
[0036] The specification describes the use of the phrases "in one embodiment" or "in other embodiments" or "in some embodiments", which may each refer to one or more of the same or different embodiments. In addition, the terms "including", "comprising", "having", etc. used in relation to the embodiments of the present disclosure are synonymous.
[0037] like Figure 3 As shown, a crystal oscillator circuit in an embodiment of the present invention includes: a bias current generating circuit 10, a bias circuit 20, an oscillator 30, a detection and adjustment circuit 40 and a sampling unit 50.
[0038] The bias current generating circuit 10 is used to generate a bias current based on a first control voltage V1; the bias circuit 20 is used to generate a bias voltage Vb based on the bias current; the oscillator 30 is used to generate an oscillation signal based on the bias voltage Vb and the bias current; the detection and adjustment circuit 40 is used to generate a second control voltage V2 based on the oscillation signal and the bias current; the sampling unit 50 is used to sample the DC component in the second control voltage V2 to generate the first control voltage V1.
[0039] The bias current generating circuit 10 includes a first transistor M1, a first resistor R1 and an output unit. The control end of the first transistor M1 is connected to the sampling unit 50 to receive the first control voltage V1, the first end of the first transistor M1 is connected to the first resistor R1, and the second end of the first transistor M1 is connected to the output unit, and the output unit is used to output one or more bias currents. In one embodiment, the first transistor M1 is an N-channel MOS transistor, the first end of the first transistor M1 is a source, the second end of the first transistor M1 is a drain, and the control end of the first transistor M1 is a gate. In other embodiments, the first transistor M1 can be a P-channel MOS transistor or a triode.
[0040] Furthermore, the output unit includes a current mirror, which is connected to the second end of the first transistor M1, the bias circuit 20, the oscillator 30 and the detection and adjustment circuit 40, and is used to output three bias currents I1, I2, and I3 provided to the bias circuit 20, the oscillator 30 and the detection and adjustment circuit 40 respectively.
[0041] The current mirror includes a fourth transistor M4, a fifth transistor M5, a sixth transistor M6 and a seventh transistor M7. The first end of the fourth transistor M4, the first end of the fifth transistor M5, the first end of the sixth transistor M6 and the first end of the seventh transistor M7 are all connected to the power supply voltage VDD, the control end of the fourth transistor M4 is connected to the second end of the fourth transistor M4 and the second end of the first transistor M1 to generate a bias current I0, and the control end of the fourth transistor M4, the control end of the fifth transistor M5, the control end of the sixth transistor M6 and the control end of the seventh transistor M7 are connected. The second end of the fifth transistor M5 is connected to the bias circuit 20 to provide the bias circuit 20 with a bias current I1, the second end of the sixth transistor M6 is connected to the oscillator 30 to provide the oscillator 30 with a bias current I2, and the second end of the seventh transistor M7 is connected to the detection and adjustment circuit 40 to provide the detection and adjustment circuit 40 with a bias current I3. The bias current I0 is mirrored by a current mirror to generate bias currents I1, I2, and I3. Based on the width-to-length ratio of the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7, the bias currents I0, I1, I2, and I3 are equal or proportional.
[0042] In one embodiment, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 are P-channel MOS transistors, the first end of the fourth transistor M4, the first end of the fifth transistor M5, the first end of the sixth transistor M6 and the first end of the seventh transistor M7 are sources, the second end of the fourth transistor M4, the second end of the fifth transistor M5, the second end of the sixth transistor M6 and the second end of the seventh transistor M7 are drains, and the control end of the fourth transistor M4, the control end of the fifth transistor M5, the control end of the sixth transistor M6 and the control end of the seventh transistor M7 are gates. In other embodiments, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 may be N-channel MOS transistors or triodes.
[0043] The bias current generating circuit 10 further includes a third capacitor C3, a first terminal of the third capacitor C3 is connected to the second terminal of the first transistor M1, and a second terminal of the third capacitor C3 is connected to the ground voltage VSS. The third capacitor C3 is used for filtering to stabilize the voltage at the second terminal of the first transistor M1.
[0044] like Figure 3 As shown, the bias circuit 20 includes a second resistor R2. A first end of the second resistor R2 is connected to a second end of the fifth transistor M5 of the bias current generating circuit 10 and the oscillator 30 to generate a bias voltage Vb based on the bias current I1, and a second end of the second resistor R2 is connected to the ground voltage VSS.
[0045] like Figure 3As shown, the oscillator 30 includes a first bias resistor Ra, a crystal XTAL, a first load capacitor CL1, a second load capacitor CL2, and a second transistor M2. The first end of the first bias resistor Ra is connected to the first end of the second resistor R2 of the bias circuit 20 to receive the bias voltage Vb, the second end of the first bias resistor Ra is connected to the control end of the second transistor M2, the first end of the first load capacitor CL1 is connected to the control end of the second transistor M2, the second end of the first load capacitor CL1 is connected to the first end of the second transistor M2 and the bias current generating circuit 10 to receive the bias current, the first end of the second load capacitor CL2 is connected to the first end of the second transistor M2, the second end of the second load capacitor CL2 is connected to the second end of the second transistor M2, the first end of the crystal XTAL is connected to the control end of the second transistor M2 and the detection and adjustment circuit 40 to form a node XI to generate an oscillation signal, and the second end of the crystal XTAL is connected to the ground voltage VSS. In one embodiment, the second transistor M2 is a P-channel MOS tube, the first end of the second transistor M2 is a source, the second end of the second transistor M2 is a drain, and the control end of the second transistor M2 is a gate.
[0046] like Figure 3 As shown, the detection and regulation circuit 40 includes: a start-up unit, an isolation unit, a second bias resistor Rb and a third transistor M3. The first end of the isolation unit is connected to the first end (node XI) of the crystal XTAL to receive the oscillation signal, the second end of the isolation unit is connected to the control end of the third transistor M3 and the first end of the second bias resistor Rb to generate the second control voltage V2, the isolation unit is used to isolate the DC signal and transmit the AC signal, and the second end of the second bias resistor Rb is connected to the second end of the third transistor M3 and the second end of the seventh MOS tube M7 of the bias current generating circuit 10.
[0047] The startup unit is connected to the second end of the third transistor M3 to provide a startup current. In one embodiment, the startup unit includes an eighth MOS transistor M8, a first end of the eighth MOS transistor M8 is connected to the power supply voltage VDD, and a control end of the eighth MOS transistor M8 is connected to the second end of the eighth MOS transistor M8 and the second end of the third transistor M3. In other embodiments, the startup unit may also be other devices such as a diode.
[0048] In one embodiment, the third transistor M3 is an N-channel MOS transistor, the first end of the third transistor M3 is a source, the second end of the third transistor M3 is a drain, and the control end of the third transistor M3 is a gate; the eighth MOS transistor M8 is a P-channel MOS transistor, the first end of the eighth MOS transistor M8 is a source, the second end of the eighth MOS transistor M8 is a drain, and the control end of the eighth MOS transistor M8 is a gate. In other embodiments, the third transistor M3 may be a P-channel MOS transistor or a triode, and the eighth MOS transistor M8 may be an N-channel MOS transistor or a triode.
[0049] The isolation unit includes an isolation capacitor Cg. A first end of the isolation capacitor Cg is connected to a first end (node XI) of the crystal XTAL to receive an oscillation signal, and a second end of the isolation capacitor Cg is connected to a control end of the third transistor M3 and a first end of the second bias resistor Rb to generate a second control voltage V2.
[0050] The detection and adjustment circuit 40 further includes a first capacitor C1, a first end of which is connected to the second end of the third transistor M3, and a second end of which is connected to the ground voltage VSS. The first capacitor C1 is used for filtering to stabilize the voltage at the second end of the third transistor M3.
[0051] The sampling unit 50 includes a third resistor R3 and a second capacitor C2, a first end of the third resistor R3 is connected to the detection and adjustment circuit 40 to receive the second control voltage V2, a second end of the third resistor R3 is connected to the first end of the second capacitor C2 and the control end of the first transistor M1 of the bias current generating circuit 10 to output the first control voltage V1, and a second end of the second capacitor C2 is connected to the ground voltage VSS.
[0052] In this embodiment, the second transistor M2 is used to provide a transconductance gm, and the first transistor M1, the first resistor R1, the third transistor M3, the fourth transistor M4 and the seventh transistor M7 form a constant transconductance current source to provide a bias current. The third transistor M3 forms a self-bias through the second bias resistor Rb (that is, the control terminal of the third transistor M3 has a DC first control voltage V1).
[0053] When the oscillation signal generated by the crystal XTAL keeps increasing, the signal after the oscillation signal is isolated and filtered by the isolation capacitor Cg will increase, so that the AC signal output by the isolation capacitor Cg is superimposed on the first control voltage V1, thereby raising the voltage on the control end of the third transistor M3 (forming the second control voltage V2). However, since the bias current I3 remains fixed, the voltage on the control end of the third transistor M3 will in turn be reduced, which is equivalent to reducing the first control voltage V1 as a DC component, so as to ensure that the voltage on the control end of the third transistor M3 remains stable.
[0054] The low-pass filter composed of the third resistor R3 and the second capacitor C2 samples the DC component (i.e., the first control voltage V1) in the second control voltage V2, and transmits the reduced first control voltage V1 to the control end of the first transistor M1, thereby further reducing the bias current I2, forming negative feedback, so that the oscillation amplitude of the crystal XTAL slowly decreases to a stable state, and the bias current I2 is maintained at the minimum current to maintain the oscillation of the crystal XTAL, thereby reducing the power consumption of the crystal XTAL when it is working.
[0055] In addition, during the oscillation phase of the crystal XTAL, the bias current I2 is relatively large, and the voltage Vgs| between the first end and the control end of the second transistor M2 is equal to Vg-Vs|. If the first end of the first bias resistor Ra is connected to the ground voltage VSS, the voltage Vs at the first end of the second transistor M2 will not be too high (compared to when Vs is a fixed voltage greater than 0V). Therefore, the voltage Vds| between the first end and the second end of the second transistor M2 is not high, and the second transistor M2 easily enters the linear region. The entry of the second transistor M2 into the linear region will result in a decrease in its equivalent transconductance and a deterioration in its negative resistance, and when the bias current I2 decreases, the voltage Vs at the first end of the second transistor M2 will further decrease. If during the oscillation process, the oscillation signal swing on the node XI is too large, and the DC bias point of this point is 0, it is easy to form a large negative voltage, causing the diode for electrostatic ESD on the node XI to be mis-conducted.
[0056] By adding the bias circuit 20, the DC bias point on the node XI can be adjusted. The bias current I1 and the second resistor R2 form a dynamic bias voltage Vb. When the oscillation starts, I1*R1=Vb. The value of Vb can be set individually according to the demand, for example, about 500mV. Therefore, the voltage |Vds| between the first end and the second end of the second transistor M2 is raised, and the second transistor M2 is not easy to enter the linear region during the oscillation process; in addition, because the DC bias point on the node XI is raised, for the same oscillation amplitude, the trough of the oscillation signal on the node XI will not reach a large negative voltage, so that the diode for electrostatic ESD on the node XI will not be turned on. In order to meet the requirements of low power consumption, a suitable second resistor R2 and bias current I1 can be selected.
[0057] When the detection and adjustment circuit 40 and the sampling unit 50 work, the bias current I1 is also reduced to about 0uA, and the voltage Vg of the control terminal of the second transistor M2 is also close to 0 potential. The current on the second transistor M2 is reduced, the swing amplitude of the oscillation signal on the node X1 is reduced, and the trough of the oscillation signal will not reach a large negative voltage. Figure 4 The signal waveform simulation result of the crystal oscillator circuit that can generate a 32.768kHz oscillation signal shows that the lowest voltage of the waveform is about -200mV, so there is no reliability problem caused by mis-conduction of the diode for electrostatic ESD on node XI.
[0058] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.
[0059] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.
Claims
1. A crystal oscillator circuit, characterized in that: include: A bias current generating circuit, configured to generate a bias current based on a first control voltage; A bias circuit for generating a bias voltage based on the bias current; an oscillator, for generating an oscillation signal based on a bias voltage and a bias current; A detection and regulation circuit, used for generating a second control voltage based on the oscillation signal and the bias current; as well as The sampling unit is used for sampling the DC component in the second control voltage to generate the first control voltage.
2. The crystal oscillator circuit according to claim 1, characterized in that: The bias current generating circuit includes a first transistor, a first resistor and an output unit, wherein the control end of the first transistor is connected to the sampling unit to receive a first control voltage, the first end of the first transistor is connected to the first resistor, the second end of the first transistor is connected to the output unit, and the output unit is used to output one or more bias currents.
3. The crystal oscillator circuit according to claim 1, characterized in that: The bias circuit includes a second resistor connected to a bias current generating circuit and an oscillator to generate a bias voltage based on a bias current.
4. The crystal oscillator circuit according to claim 1, characterized in that: The oscillator includes a first bias resistor, a crystal, a first load capacitor, a second load capacitor and a second transistor; the first end of the first bias resistor is connected to the bias circuit to receive a bias voltage, the second end of the first bias resistor is connected to the control end of the second transistor, the first end of the first load capacitor is connected to the control end of the second transistor, the second end of the first load capacitor is connected to the first end of the second transistor and the bias current generating circuit to receive a bias current, the first end of the second load capacitor is connected to the first end of the second transistor, the second end of the second load capacitor is connected to the second end of the second transistor, the first end of the crystal is connected to the control end of the second transistor and the detection and adjustment circuit to generate an oscillation signal, and the second end of the crystal is connected to the ground voltage.
5. The crystal oscillator circuit according to claim 1, characterized in that: The detection and adjustment circuit includes: an isolation unit, a second bias resistor and a third transistor, the first end of the isolation unit is connected to the first end of the crystal to receive an oscillation signal, the second end of the isolation unit is connected to the control end of the third transistor and the first end of the second bias resistor to generate a second control voltage, and the second end of the second bias resistor is connected to the second end of the third transistor and a bias current generating circuit.
6. The crystal oscillator circuit according to claim 5, characterized in that: The detection and regulation circuit further includes a startup unit, which is connected to the second end of the third transistor to provide a startup current.
7. The crystal oscillator circuit according to claim 5, characterized in that: The detection and regulation circuit further includes a first capacitor, a first end of the first capacitor is connected to the second end of the third transistor, and a second end of the first capacitor is connected to the ground voltage.
8. The signal processing method according to claim 1, characterized in that: The sampling unit includes a third resistor and a second capacitor, the first end of the third resistor is connected to the detection and adjustment circuit to receive the second control voltage, the second end of the third resistor is connected to the first end of the second capacitor and the bias current generating circuit to output the first control voltage, and the second end of the second capacitor is connected to the ground voltage.
9. The signal processing method according to claim 2, characterized in that: The output unit includes a current mirror, which is connected to the second end of the first transistor, the bias circuit, the oscillator and the detection and regulation circuit. The current mirror is used to output three bias currents respectively provided to the bias circuit, the oscillator and the detection and regulation circuit.
10. The signal processing method according to claim 2, characterized in that: The bias current generating circuit comprises a third capacitor, a first end of the third capacitor is connected to the second end of the first transistor, and a second end of the third capacitor is connected to a ground voltage.