Multi-stage amplifier circuit

Abstract

An amplifier includes: a first stage amplifier circuit configured to receive an input voltage; and a first multi-stage amplifier circuit and a second multi-stage amplifier circuit branched from an output terminal of the first-stage amplifier circuit and each including a second stage and a third stage. Each of the first multi-stage amplifier circuit and the second multi-stage amplifier circuit may be configured to sample a voltage corresponding to a first bias current and a voltage corresponding to a second bias current in a first stage, in the second stage, the second stage is biased with a voltage corresponding to a first bias current corresponding to the second stage and the third stage is biased with a voltage corresponding to a second bias current corresponding to the third stage.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0096904 filed on July 25, 2023, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2024-0028402 filed on February 27, 2024, in the Korean Intellectual Property Office, the disclosure of each of which is incorporated herein by reference in its entirety. Technical Field

[0002] Example embodiments relate to multi-stage amplifier circuits. Background Art

[0003] Various analog-to-digital converters (ADCs), such as pipeline ADCs, pipeline successive approximation register (SAR) ADCs, or cyclic ADCs, may include switched capacitor (SC) amplifiers. For example, SC amplifiers may be implemented using operational transconductance amplifiers (OTAs), but OTAs typically have high power consumption, resulting in low power efficiency. Therefore, it may be advantageous to provide an amplifier with lower power consumption to replace OTAs. Summary of the invention

[0004] Example embodiments provide a multi-stage amplifier circuit for dynamic biasing.

[0005] According to some example embodiments, a multi-stage amplifier circuit includes: a first multi-stage amplifier circuit and a second multi-stage amplifier circuit. The first multi-stage amplifier circuit may include: a second-stage N-type transistor connected to the first stage through a 1-1 capacitor, the 1-1 capacitor connected to a gate of the second-stage N-type transistor, a bias N-type transistor connected to a drain of the second-stage N-type transistor and having a gate connected to the 1-2 capacitor, a third-stage N-type transistor having a gate connected to the drain of the second-stage N-type transistor, a first current circuit configured to supply a first bias current and a second bias current, and a first dynamic switching circuit connected to the second-stage N-type transistor, the bias N-type transistor, the third-stage N-type transistor, and the first current circuit, and configured to: sample a voltage corresponding to a first bias current across the 1-1 capacitor in a first stage, and sample a voltage corresponding to a second bias current across the 1-2 capacitor based on forming a feedback loop including the bias N-type transistor and the third-stage N-type transistor. The second multi-stage amplifier circuit includes: a second-stage P-type transistor connected to the first stage through a 2-1 capacitor, the 2-1 capacitor connected to the gate of the second-stage P-type transistor, a bias P-type transistor connected to the drain of the second-stage P-type transistor and having a gate connected to the 2-2 capacitor, a third-stage P-type transistor having a gate connected to the drain of the second-stage P-type transistor, a second current circuit configured to supply a first bias current and a second bias current, and a second dynamic switching circuit connected to the second-stage P-type transistor, the bias P-type transistor, the third-stage P-type transistor and the second current circuit, and configured to: sample a voltage corresponding to the first bias current across the 2-1 capacitor in the first stage, and sample a voltage corresponding to the second bias current across the 2-2 capacitor based on forming a feedback loop including the second-stage P-type transistor, the bias P-type transistor and the third-stage P-type transistor.

[0006] According to some example embodiments, an amplifier includes: a first-stage amplifier circuit configured to receive an input voltage; and a first multi-stage amplifier circuit and a second multi-stage amplifier circuit branched from an output terminal of the first-stage amplifier circuit and each including a second stage and a third stage. Each of the first multi-stage amplifier circuit and the second multi-stage amplifier circuit may be configured to: sample a voltage corresponding to a first bias current and a voltage corresponding to a second bias current in a first stage, and bias the second stage with a voltage corresponding to the first bias current and bias the third stage with a voltage corresponding to the second bias current in a second stage, the first bias current corresponding to the second stage, and the second bias current corresponding to the third stage.

[0007] According to some example embodiments, a differential amplifier includes: a first-stage amplifier circuit configured to receive a differential input voltage pair; and a plurality of multi-stage amplifier circuits configured to output a differential voltage output pair for the differential input voltage pair. Each of the plurality of multi-stage amplifier circuits may include: a first multi-stage amplifier circuit and a second multi-stage amplifier circuit branched from an output terminal of the first-stage amplifier circuit and each including a second stage and a third stage. Each of the first multi-stage amplifier circuit and the second multi-stage amplifier circuit is configured to: sample a voltage corresponding to a first bias current and a voltage corresponding to a second bias current in a first stage, and bias the second stage with a voltage corresponding to the first bias current and bias the third stage with a voltage corresponding to the second bias current in a second stage, the first bias current corresponding to the second stage, and the second bias current corresponding to the third stage. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects, features and advantages of the inventive concept will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.

[0009] Figure 1 is a diagram illustrating a multi-stage amplifier circuit according to some example embodiments.

[0010] Figure 2 According to some example embodiments Figure 1 Circuit diagram of a multi-stage amplifier circuit.

[0011] Figure 3 is a diagram illustrating an amplifier according to some example embodiments.

[0012] Figure 4 is a circuit diagram of a first stage amplifier circuit according to some example embodiments.

[0013] Figure 5 2 is a diagram illustrating a first multi-stage amplifier circuit and a second multi-stage amplifier circuit according to some example embodiments.

[0014] Figure 6 is a diagram showing some example embodiments Figure 5 A diagram of the first stage operation of the amplifier.

[0015] Figure 7 is a diagram showing some example embodiments Figure 5 A diagram of the second stage operation of the amplifier.

[0016] Figure 8 is a diagram illustrating a differential amplifier according to some example embodiments. DETAILED DESCRIPTION

[0017] Hereinafter, example embodiments will be described with reference to the accompanying drawings.

[0018] Figure 1 is a diagram of a multi-stage amplifier circuit according to some example embodiments.

[0019] Reference Figure 1 , the multi-stage amplifier circuit 100 may be configured to amplify a signal provided from the first stage S1, and output an output voltage Vout based on the amplification. The first stage S1 may be an input stage configured to receive and amplify an input voltage. The multi-stage amplifier circuit 100 may include two stages. For ease of description, the two stages close to the first stage S1 and included in the multi-stage amplifier circuit 100 may be sequentially referred to as the second stage S2 and the third stage S3, respectively. The first stage S1, the second stage S2, and the third stage S3 may be connected in series.

[0020] The multi-stage amplifier circuit 100 according to some example embodiments may include a plurality of transistors, a plurality of capacitors, a current circuit 110, and a dynamic switching circuit 120. The plurality of transistors may include a second-stage transistor T1, a bias transistor TB, and a third-stage transistor T2. The second-stage transistor T1 and the bias transistor TB may correspond to the second stage S2, and the third-stage transistor T2 may correspond to the third stage S3.

[0021] The second stage S2 may be connected to the first stage S1 through the first node n1. A gate of the second stage transistor T1 included in the second stage S2 may be connected to the first capacitor C1 through the first node n1. For example, the second stage transistor T1 may be connected to the first stage S1 through the first capacitor C1 connected to the gate.

[0022] The drain of the second-stage transistor T1 may be connected to the third stage S3 through the second node n2. For example, the drain of the second-stage transistor T1 may be connected to the gate of the third-stage transistor T2 through the second node n2. In some example embodiments, the drain of the second-stage transistor T1 may be connected to the source of the bias transistor TB through the second node n2. In some example embodiments, the source of the second-stage transistor T1 may be grounded or supplied with a power supply voltage (e.g., GND or VDD).

[0023] The bias transistor TB may have a source connected to the drain of the second stage transistor T1 through the second node n2, a gate connected to the second capacitor C2 and the dynamic switching circuit 120 through the third node n3, and a drain connected to the dynamic switching circuit 120. In some example embodiments, the second capacitor C2 may have one end connected to the third node n3 and the other end grounded or supplied with a power supply voltage.

[0024] According to some example embodiments, the multi-stage amplifier circuit 100 may operate in a first stage and a second stage. The first stage may be defined as a stage for biasing each stage (the second stage S2 or the third stage S3) included in the multi-stage amplifier circuit 100, and the second stage may be defined as a stage for amplifying an input voltage and outputting an output voltage Vout based on each stage for which bias preparation has been completed through the first stage. For example, the second stage may be a stage defined as causing the multi-stage amplifier circuit 100 to perform an amplification operation in a biased state. The first stage and the second stage may be non-overlapping stages.

[0025] In the first stage, the bias transistor TB and the dynamic switching circuit 120 are operable to sample a voltage (hereinafter referred to as a "first bias voltage") corresponding to the first bias current IB1 provided from the current circuit 110 for biasing to be described later. The second stage transistor T1 can operate based on the voltage biased in the second stage to perform an amplification operation.

[0026] The third-stage transistor T2 included in the third stage S3 connected to the second stage may have a gate connected to "the drain of the second-stage transistor T1, the source of the bias transistor TB, and the dynamic switching circuit 120" through the second node n2 and a drain connected to "the dynamic switching circuit 120 and the current circuit 110". In some example embodiments, the third-stage transistor T2 may have a source that is grounded or supplied with a power supply voltage. According to the operation of the bias transistor TB and the dynamic switching circuit 120, the third-stage transistor T2 may be biased with a voltage (hereinafter referred to as a "second bias voltage") corresponding to the second bias current IB2 provided from the current circuit 110. The third-stage transistor T2 may operate based on the voltage biased in the second stage to perform an amplification operation.

[0027] The current circuit 110 may be configured to supply a first bias current IB1 and a second bias current IB2. The term "supply" may refer not only to the operation of a current source that provides a bias current to the dynamic switching circuit 120, but also to the operation of providing a negative bias current to the dynamic switching circuit 120 (e.g., the operation of a current sink (also referred to as a current absorber, current sink)). For example, according to some example embodiments, the current circuit 110 may operate as a current source or a current sink. The first bias current IB1 may have a value for a steady-state operation of the second stage S2, and the second bias current IB2 may have a value for a steady-state operation of the third stage S3.

[0028] According to some example embodiments, the current circuit 110 may be disposed inside the multi-stage amplifier circuit 100 or outside the multi-stage amplifier circuit 100. The phrase “disposed outside the multi-stage amplifier circuit 100” may refer to the phrase “disposed outside an amplifier including the multi-stage amplifier circuit 100”. For example, when the current circuit 110 is disposed outside the multi-stage amplifier circuit 100, the current circuit does not affect the amplification operation of the multi-stage amplifier circuit 100, and thus may be made into a large element to solve the mismatch problem of the current circuit 110.

[0029] The dynamic switching circuit 120 may be configured to perform a dynamic switching operation according to the first stage and the second stage described above. The dynamic switching circuit 120 may be connected to the second stage transistor T1, the bias transistor TB, the third stage transistor T2, and the current circuit 110. The dynamic switching circuit 120 may receive the first bias current IB1 and the second bias current IB2 from the current circuit 110, and may sample the bias voltage so that each stage may operate with the bias voltage in the first stage for biasing.

[0030] In the first stage, the dynamic switching circuit 120 may be configured to sample the first bias voltage generated by the bias current to the first capacitor C1. For example, in the first stage, the dynamic switching circuit 120 may sample the voltage required by the first bias current IB1 for biasing the second-stage transistor T1 to one end of the second-stage transistor T1 (e.g., the first node n1 side).

[0031] In some example embodiments, in the first stage, the dynamic switching circuit 120 may be configured to sample the second bias voltage to the second capacitor C2 based on forming a feedback loop including the bias transistor TB, the second-stage transistor T1, and the third-stage transistor T2 and causing the second bias current to flow through the third-stage transistor T2. For example, the dynamic switching circuit 120 may form a feedback loop including the bias transistor TB, the second-stage transistor T1, and the third-stage transistor T2 through the third node n3 according to the switching. The second bias voltage may be sampled through the feedback loop "across the second capacitor C2 connected to the third node n3".

[0032] In the second phase, the dynamic switching circuit 120 may be switched so that the biased second and third stages operate as amplifiers. The second and third stages may output an output voltage Vout based on the amplification operation.

[0033] For example, the dynamic switching circuit 120 may be configured to bias the second-stage transistor T1 with the first bias voltage and bias the third-stage transistor T2 with the second bias voltage in the second stage. For example, the dynamic switching circuit 120 may bias the gate voltage (e.g., the voltage at the second node n2) of the third-stage transistor T2 to a voltage lower than the second bias voltage by a "gate-source voltage of the bias transistor TB" through the bias transistor TB. In some example embodiments, the biasing may be performed based on the voltage sampled through the first stage.

[0034] According to some example embodiments, the dynamic switching circuit 120 may be configured to operate the bias transistor TB as a flip voltage follower based on short-circuiting the drain of the bias transistor TB and the gate of the second-stage transistor T1 in the first stage. The bias transistor TB may be operated as a flip voltage follower through the dynamic switching circuit 120. In some example embodiments, the bias transistor TB may output a voltage through the second node n2 that is lower than the second bias voltage sampled across the second capacitor C2 by the "gate-source voltage of the bias transistor TB", and the gate of the third-stage transistor T2 may be applied with a voltage that is lower than the second bias voltage sampled across the second capacitor C2 by the "gate-source voltage of the bias transistor TB". Therefore, the third-stage transistor T2 may then be biased with the second bias current IB2 in the second stage.

[0035] According to the above-described example embodiments, the multi-stage amplifier circuit 100 can dynamically bias each stage using transistors included in the second stage S2 and the third stage S3 through the dynamic switching circuit 120. For example, according to some example embodiments, operating current biasing required for or advantageous for each stage can be performed using transistors provided for amplification and the dynamic switching circuit 120 without additional calibration for biasing.

[0036] In some example embodiments, even when characteristics of transistors provided in the multi-stage amplifier circuit 100 vary due to process variations, operating current biasing required for or advantageous for each stage may be performed.

[0037] Figure 2 According to some example embodiments Figure 1 Circuit diagram of a multi-stage amplifier circuit.

[0038] Reference Figure 2 , the current circuit 110 may include a plurality of current sources IS1, IS2, and IS3. The plurality of current sources IS1, IS2, and IS3 may be connected to a power supply voltage or may be grounded. The plurality of current sources IS1, IS2, and IS3 may be connected to the dynamic switching circuit 120 to supply bias current. The dynamic switching circuit 120 may receive a first bias current IB1 and a second bias current IB2 from the current circuit 110.

[0039] According to some example embodiments, the dynamic switching circuit 120 may include first to seventh switches SW1 to SW7. The first switch SW1 may be connected to the gate of the second-stage transistor T1 and the drain of the bias transistor TB. For example, one end of the first switch SW1 may be connected to one end of the first capacitor C1 and the gate of the second-stage transistor T1 through the first node n1, and the other end of the first switch SW1 may be connected to the first current source IS1 supplying a portion of the first bias current IB1 through the fourth node n4. For example, the first current source IS1 may supply αIB1 (where 0<α<1) as a portion of the first bias current IB1.

[0040] The second switch SW2 may be connected to the drain of the second-stage transistor T1, the gate of the third-stage transistor T2, the source of the bias transistor TB, and the current circuit 110. For example, one end of the second switch SW2 may be connected to the source of the bias transistor TB and the drain of the second-stage transistor T1 through the second node n2, and the other terminal (or the other end) of the second switch SW2 may be connected to the second current source IS2 that supplies a portion of the first bias current IB1. For example, the second current source IS2 may supply (1-α)IB1 as a portion of the first bias current IB1. For example, when α=1 / 2, each of the first current source IS1 and the second current source IS2 may supply half of the first bias current IB1.

[0041] The third switch SW3 may be connected to the gate of the bias transistor TB, the second capacitor C2, and the drain of the third-stage transistor T2. For example, one end of the third switch SW3 may be connected to the gate of the bias transistor TB and one end of the second capacitor C2 through the third node n3, and the other terminal (or other end) of the third switch SW3 may be connected to the third current source IS3 and the drain of the third-stage transistor T2 through the fifth node n5 and the fifth switch SW5. In some example embodiments, the other end of the third switch SW3 may be connected to the output terminal (e.g., the terminal where the output voltage Vout is output) through the seventh switch SW7.

[0042] The fourth switch SW4 may be connected to the first switch SW1, the drain of the bias transistor TB, and the first current source IS1. For example, one end of the fourth switch SW4 may be connected to the drain of the bias transistor TB and the first switch SW1 through the fourth node n4, and the other terminal of the fourth switch SW4 may be connected to the first current source IS1. In some example embodiments, one end of the fourth switch SW4 may be connected to a multi-stage amplifier circuit (not shown) on the other side.

[0043] The fifth switch SW5 may be connected to the drain of the third stage transistor T2 and the third current source IS3. For example, one end of the fifth switch SW5 may be connected to the drain of the third switch SW3, the seventh switch SW7 and the third stage transistor T2 through the fifth node n5, and the other end of the fifth switch SW5 may be connected to the third current source IS3.

[0044] One end of the sixth switch SW6 can be connected to the second switch SW2 and connected to the drain of the second-stage transistor T1, the source of the bias transistor TB and the gate of the third-stage transistor T2 through the second node n2, and the other end of the sixth switch SW6 can be connected to the multi-stage amplifier circuit (not shown) on the other side.

[0045] One end of the seventh switch SW7 may be connected to the third switch SW3 , the fifth switch SW5 , and the drain of the third stage transistor T2 through the fifth node n5 , and the other end of the seventh switch SW7 may be connected to the output terminal (eg, a terminal to which the output voltage Vout is output).

[0046] The first to fifth switches SW1 to SW5 may be configured to be turned on in the first phase and turned off in the second phase.

[0047] The first switch SW1 and the third switch SW3 may be configured to sample the bias voltage across the first capacitor C1 and the second capacitor C2 while dynamically operating in the first phase and the second phase.

[0048] The second switch SW2 may be turned on in the first phase and turned off in the second phase. The second switch SW2 may supply a portion (eg, (1-α)IB1) of the first bias current to the second node n2 based on being turned on in the first phase.

[0049] The fourth switch SW4 and the fifth switch SW5 may be turned on in the first phase and turned off in the second phase. The fourth switch SW4 may supply a portion of the first bias current (e.g., αIB1) to the fourth node n4 based on being turned on in the first phase. The fifth switch SW5 may supply the second bias current (e.g., IB2) to the fifth node n5 based on being turned on in the first phase.

[0050] When the first to fifth switches SW1 to SW5 are turned on, the first node n1 and the fourth node n4 may be connected to each other, and a portion of the first bias current (e.g., αIB1) may be supplied to the fourth node n4 through the first current source IS1 and a portion of the first bias current (e.g., (1-α)IB1) may be supplied to the second node n2 through the second current source IS2. In some example embodiments, the third node n3 and the fifth node n5 may be connected to each other, and the second bias current IB2 may be supplied to the fifth node n5.

[0051] The second-stage transistor T1 may have a drain connected to the first node n1 through the bias transistor TB and the first switch SW1, and may receive a portion of the first bias current from each of the first current source IS1 and the second current source IS2, and the third-stage transistor T2 may receive the second bias current IB2. Therefore, the first bias voltage may be sampled across the first capacitor C1 connected to the second-stage transistor T1, and the second bias voltage may be sampled across the second capacitor C2 connected to the third-stage transistor T2.

[0052] The fourth switch SW4 and the fifth switch SW5 may be disconnected in the second stage to block the supply of current from the first current source IS1 and the third current source IS3. Similarly, the second switch SW2 may also be disconnected in the second stage to block the supply of current from the second current source IS2. For example, an unused current circuit may be disconnected in the second stage by the second switch SW2, the fourth switch SW4, and the fifth switch SW5 to reduce current consumption. In some example embodiments, the current circuit may be implemented outside the multi-stage amplifier circuit 100 by the second switch SW2, the fourth switch SW4, and the fifth switch SW5, so that the current circuit does not affect the amplification operation of the multi-stage amplifier circuit 100, and thus may be made into a large element to reduce mismatch problems.

[0053] The sixth switch SW6 to the seventh switch SW7 may be turned off in the first stage and turned on in the second stage. When the sixth switch SW6 to the seventh switch SW7 are turned on in the second stage, the multi-stage amplifier circuit 100 may be connected to another multi-stage amplifier circuit not shown to perform an amplification operation and output the output voltage Vout.

[0054] The plurality of current sources included in the current circuit 110 may include first to third current sources IS1 to IS3 to supply bias current to the dynamic switching circuit 120 including the first to seventh switches SW1 to SW7. The first current source IS1 may be connected to one end of the fourth switch SW4 and may supply a portion of the first bias current (e.g., αIB1). The second current source IS2 may be connected to one end of the second switch SW2 and may also supply a portion of the first bias current (e.g., (1-α)IB1). The third current source IS3 may be connected to one end of the fifth switch SW5 and may supply a second bias current (e.g., IB2).

[0055] Hereinafter, operations of the first stage and the second stage of the multi-stage amplifier circuit 100 according to some example embodiments will be described in more detail based on components included in the above-described multi-stage amplifier circuit 100 .

[0056] According to some example embodiments, the multi-stage amplifier circuit 100 may be implemented to ensure stability of an amplifier that may include the multi-stage amplifier circuit 100 , and to operate at low power.

[0057] The multi-stage amplifier circuit 100 may be configured to operate as a one-pole system to achieve stability. For example, the one-pole system may be implemented using a Miller compensation capacitor. When a compensation capacitor is formed in the second stage, a main pole may be formed at the output node of the first stage, and the poles of the output nodes of the second and third stages close to the first stage may be moved to a higher frequency. Therefore, the stability of the amplifier may be improved, but high power consumption may be required because of the "increase in load due to the compensation capacitors formed in the second and third stages and the load capacitors formed in the third stage."

[0058] Therefore, the multi-stage amplifier circuit 100 according to some example embodiments may be configured to significantly reduce the load on the output nodes of the first and second stages, and instead form a dominant pole at the output node of the third stage. In some example embodiments, the amplifier may ensure stability and operate at low power.

[0059] According to some example embodiments, it may be advantageous to reduce the sizes of the second stage transistor T1 , the bias transistor TB, and the third stage transistor T2 to significantly reduce the load on the output nodes of the first stage S1 and the second stage S2 .

[0060] According to some example embodiments, it may be advantageous to increase the output impedance of the third stage S3 to form a main pole in the third stage S3. For example, it may be advantageous to bias the third stage transistor T2 so that the third stage transistor T2 operates in the subthreshold region so that the output impedance of the third stage S3 increases. In order to bias the subthreshold region of the third stage transistor T2, the source of the bias transistor TB may be connected to the drain of the second stage transistor T1, and the bias transistor TB and the dynamic switching circuit 120 may be used to bias the transistor of each stage to an appropriate voltage of the subthreshold region. In some example embodiments, the first bias current IB1 and the second bias current IB2 for biasing may also have values ​​for operating the third stage transistor T2 in the subthreshold region.

[0061] When the first to fifth switches SW1 to SW5 are turned on in the first stage, the first node n1 and the fourth node n4 may be connected to each other, the second current source IS2 may be connected to the second node n2, and the third node n3 and the fifth node n5 may be connected to each other. For example, the drain of the bias transistor TB and the gate of the second stage transistor T1 may be short-circuited by the first switch SW1. The first current source IS1 may supply a portion of the first bias current to the fourth node n4, and the second current source IS2 may supply a portion of the first bias current to the second node n2.

[0062] Then, in some example embodiments, the drain and gate of the second-stage transistor T1 may be connected through the bias transistor TB, and may receive a portion of the first bias current from each of the first current source IS1 and the second current source IS2. A voltage required for the second-stage transistor T1 to flow the first bias current may be sampled across the first capacitor C1 connected to the first node n1 and the fourth node n4. Therefore, the voltage sampling for biasing the second-stage transistor T1 may be performed through the first stage.

[0063] When the fifth switch SW5 is turned on, the third current source IS3 may supply the second bias current IB2 to the drain of the third-stage transistor T2 through the fifth node n5. In some example embodiments, when the third switch SW3 is turned on, the voltage required for the third-stage transistor T2 to flow the second bias current may be sampled across the second capacitor C2 connected to the fifth node n5 (and the third node n3). Therefore, the voltage sampling for biasing the third-stage transistor T2 may also be performed through the first stage.

[0064] According to some example embodiments, in the first stage, the bias transistor TB may be operated as a flip voltage follower by the dynamic switching circuit 120. For example, the bias transistor TB may be operated as a flip voltage follower that uses a portion of the first bias current supplied to the drain as a reference current source and uses the first bias current IB1 flowing through the source as a current sink. In some example embodiments, when the first switch SW1 is turned on, the bias transistor TB and the second-stage transistor T1 may be operated as a flip voltage follower. Therefore, the bias transistor TB may output to the second node n2 a voltage that is a "gate-source voltage of the bias transistor TB" reduced from the second bias voltage sampled across the second capacitor C2.

[0065] For example, when the first switch SW1 to the fifth switch SW5 included in the dynamic switching circuit 120 are turned on, a feedback loop including the second-stage transistor T1, the bias transistor TB, and the third-stage transistor T2 may be formed, and the second bias voltage may be sampled across the second capacitor C2. At the same time, the bias transistor TB and the second-stage transistor T1 may operate as a flip voltage follower to output the sampled second bias voltage to the second node n2 (e.g., the gate of the third-stage transistor T2). The third-stage transistor T2 may be applied with a voltage lower than the second bias voltage by the "gate-source voltage of the bias transistor TB", and the third-stage transistor T2 may flow the second bias current IB2 based on the bias. In some example embodiments, when the third-stage transistor T2 is biased with the second bias current IB2, the third-stage transistor T2 may operate in the subthreshold region.

[0066] Then, in some example embodiments, when the first switch SW1 to the fifth switch SW5 are disconnected in the second stage, the second stage S2 and the third stage S3 may perform an amplification operation based on the bias. In some example embodiments, the second stage transistor T1 may flow through the first bias current IB1 based on the bias, and the third stage transistor T2 may flow through the second bias current IB2 based on the bias. As a result, according to the above-described example embodiments, the multi-stage amplifier circuit 100 may operate across the first stage and the second stage as a current mirror that operates dynamically in the first stage. In the first stage, the multi-stage amplifier circuit 100 may sample a bias voltage corresponding to the mirror current for each capacitor. In the second stage, the multi-stage amplifier circuit 100 may bias the second stage transistor T1, the bias transistor TB, and the third stage transistor T2 with the sampled bias voltage. Therefore, the mirrored first bias current may flow through the second stage transistor T1, and the mirrored second bias current may flow through the third stage transistor T2.

[0067] According to the above-described example embodiment, when the first to fifth switches SW1 to SW5 connected to the second-stage transistor T1, the bias transistor TB, and the third-stage transistor T2 are turned on in the first stage, the multi-stage amplifier circuit 100 can bias each of the second and third stages. For example, the third-stage transistor T2 can be biased to operate in the subthreshold region, and thus the multi-stage amplifier circuit 100 can operate stably at low power.

[0068] In some example embodiments, the multi-stage amplifier circuit 100 may be biased by operating as a dynamically operated current mirror without an element being added to, for example, the third stage. When an element for mirroring is added to the third stage, the frequency of the pole corresponding to the output node of the second stage may be reduced, but the above problem may be prevented or reduced according to example embodiments.

[0069] Figure 3 is a diagram illustrating an amplifier according to some example embodiments.

[0070] Reference Figure 3 The amplifier 200 may include a first-stage amplifier circuit 210 , a first multi-stage amplifier circuit 220 , and a second multi-stage amplifier circuit 230 .

[0071] The first stage amplifier circuit 210 may be applied with an input voltage Vin. For example, the first stage amplifier circuit 210 may be configured to receive the input voltage Vin. The first stage amplifier circuit 210 may amplify the input voltage Vin based on a gain. For example, the first stage amplifier circuit 210 may be implemented as an inverter. The first stage amplifier circuit 210 may be connected to the first multi-stage amplifier circuit 220 and the second multi-stage amplifier circuit 230.

[0072] The first multi-stage amplifier circuit 220 and the second multi-stage amplifier circuit 230 may be branched from the output stage of the first stage amplifier circuit 210, and may each include a second stage S2 and a third stage S3. As will be described later, the first multi-stage amplifier circuit 220 and the second multi-stage amplifier circuit 230 may be connected to each other through a dynamic switching circuit. For example, the first multi-stage amplifier circuit 220 and the second multi-stage amplifier circuit 230 may be connected to each other in the second stage so that a portion of the first bias current flows through each of the two paths. In some example embodiments, the first multi-stage amplifier circuit 220 and the second multi-stage amplifier circuit 230 may output the output voltage Vout through the output node no in the second stage.

[0073] According to some example embodiments, each of the first multi-stage amplifier circuit 220 and the second multi-stage amplifier circuit 230 may sample a voltage corresponding to a first bias current IB1 corresponding to the second stage S2 and a voltage corresponding to a second bias current IB2 in a first stage. In some example embodiments, each of the first multi-stage amplifier circuit 220 and the second multi-stage amplifier circuit 230 may be configured to bias the second stage S2 with a voltage corresponding to the first bias current IB1 and bias the third stage S3 with a voltage corresponding to the second bias current IB2.

[0074] In the following, reference will be made to Figures 4 to 7 describe Figure 3 Various example embodiments of amplifiers.

[0075] Figure 4 is a circuit diagram of a first stage amplifier circuit according to some example embodiments.

[0076] Reference Figure 4 , the first stage amplifier circuit 210 may include an amplifying element AE, a first input switch ISW1 and a second input switch ISW2.

[0077] The input terminal of the amplification element AE may be connected to the first input switch ISW1 and the second input switch ISW2 through the node x (nx), and the output terminal of the amplification element AE may be connected to the input node i (ni). The amplification element AE may amplify the input voltage Vin applied from the node x (nx) through the second input switch ISW2 by as much as the “gain required in the first stage”, and may output the amplified voltage to the input node i (ni). For example, the amplification element AE may be implemented as an operational transconductance amplifier (OTA) or an inverter type OTA.

[0078] The first input switch ISW1 may be connected to the node x(nx) to apply the common mode voltage VCM to the node x(nx). The first input switch ISW1 may be turned on in the first stage to apply the common mode voltage VCM to the amplification element AE. Since the input node i(ni) is connected to the first multi-stage amplifier circuit and the second multi-stage amplifier circuit as described above, the output common mode voltage of the first stage amplifier circuit 210 and the output offset of the first stage amplifier circuit 210 itself may be applied to the first multi-stage amplifier circuit 220 and the second multi-stage amplifier circuit 230 in the first stage. The first input switch ISW1 may be turned off in the second stage.

[0079] The second input switch ISW2 may be connected to the node x (nx) and may apply the input voltage Vin to the node x (nx). The second input switch ISW2 may be turned off in the first stage. The second input switch ISW2 may be turned on in the second stage to apply the input voltage Vin to the amplification element AE. Therefore, in the second stage for amplification, the amplification element AE may amplify the applied input voltage Vin by the "gain" and output the amplified input voltage to the input node i (ni).

[0080] Figure 5 is a diagram illustrating a first multi-stage amplifier circuit 220 and a second multi-stage amplifier circuit 230 according to some example embodiments.

[0081] Reference Figure 5 The first multi-stage amplifier circuit 220 and the second multi-stage amplifier circuit 230 may each be based on Figures 1 to 3 The multi-stage amplifier circuit according to some example embodiments described in is implemented.

[0082] For example, the first multi-stage amplifier circuit 220 may include a second-stage N-type transistor TN1, a third-stage N-type transistor TN2, and a bias N-type transistor TBN. The term "N-type" is used to distinguish elements included in the first multi-stage amplifier circuit 220, but "N-type transistor" may refer to a transistor configured so as to form an N-channel.

[0083] The gate of the second-stage N-type transistor TN1 may be connected to the 1-1th capacitor C1-1 through the first node n1, and the 1-1th capacitor C1-1 is connected to the output terminal of the first-stage amplifier circuit 210. The drain terminal of the second-stage N-type transistor TN1 may be connected to the gate of the third-stage N-type transistor TN2 and the source of the bias N-type transistor TBN through the second node n2. In some example embodiments, the source of the second-stage N-type transistor TN1 may be grounded.

[0084] The source of the bias N-type transistor TBN can be connected to the drain of the second-stage N-type transistor TN1 through the second node n2, the gate of the bias N-type transistor TBN can be connected to the 1-2 capacitor C1-2 and the 1-3 switch SW1-3 through the third node n3, and the drain of the bias N-type transistor TBN can be connected to the 1-1 switch SW1-1, the 1-4 switch SW1-4 and the 2-6 switch SW2-6 through the fourth node n4.

[0085] The second-stage N-type transistor TN1 and the bias N-type transistor TBN may correspond to the second stage S2 of the first multi-stage amplifier circuit 220 .

[0086] The gate of the third-stage N-type transistor TN2 may be connected to the drain of the second-stage N-type transistor TN1 through the second node n2, and the drain of the third-stage N-type transistor TN2 may be connected to the 1-3 switch SW1-3, the 1-5 switch SW1-5, and the 1-7 switch SW1-7 through the fifth node n5. In some example embodiments, the source of the third-stage N-type transistor TN2 may be grounded.

[0087] The first multi-stage amplifier circuit 220 may include 1-1th switch SW1-1 to 1-7th switch SW1-7 which may correspond to the above-mentioned dynamic switching circuit. In some example embodiments, the dynamic switching circuit of the stage of the first multi-stage amplifier circuit 220 including the 1-1th switch SW1-1 to the 1-7th switch SW1-7 may be defined as a first dynamic switching circuit.

[0088] The 1-1 switch SW1-1 may have one end “connected to one end of the 1-1 capacitor C1-1 and the gate of the second-stage N-type transistor TN1” through the first node n1 and the other end “connected to the 1-1 current source IS1-1 and to the drain of the bias N-type transistor TBN” through the fourth node n4 and the 1-4 switch SW1-4. The 1-2 switch SW1-2 may have one end “connected to the drain of the second-stage N-type transistor TN1, the gate of the third-stage N-type transistor TN2, and the source of the bias N-type transistor TBN” through the second node n2 and the other end connected to the 1-2 current source IS1-2. The 1-3 switch SW1-3 may have one end connected to the gate of the bias N-type transistor TBN and the 1-2 capacitor C1-2 through the third node n3 and the other end connected to the drain of the third-stage N-type transistor TN2 through the fifth node n5.

[0089] The 1-1 switch SW1-1 and the 1-3 switch SW1-3 may sample the bias voltage across the 1-1 capacitor C1-1 and the 1-2 capacitor C1-2 while dynamically operating in the first phase and the second phase.

[0090] The 1-4th switch SW1-4 may have one end connected to the drain of the bias N-type transistor TBN through the fourth node n4 and the other end connected to the 1-1st current source IS1-1. The 1-5th switch SW1-5 may have one end connected to the drain of the third-stage N-type transistor TN2 through the fifth node n5 and the other end connected to the 1-3rd current source IS1-3.

[0091] The 1-2 switch SW1-2 and the 1-4 to 1-5 switches SW1-4 to SW1-5 may supply the bias current from the 1-1 to 1-3 current sources IS1-3 or block the supply of the bias current while dynamically operating in the first and second phases.

[0092] The 1-6th switch SW1-6 may be included in the first multi-stage amplifier circuit 220, and may have one end connected to the drain of the second-stage N-type transistor TN1 through the second node n2 and the other end connected to the second multi-stage amplifier circuit 230. For example, the other end of the 1-6th switch SW1-6 may be connected to the drain of the bias P-type transistor TBP included in the second multi-stage amplifier circuit 230.

[0093] The 1-7th switch SW1-7 may be included in the first multi-stage amplifier circuit 220 and may have one end connected to the drain of the third-stage N-type transistor TN2 through the fifth node n5 and the other end connected to the output terminal of the first multi-stage amplifier circuit 220 and the second multi-stage amplifier circuit 230 (for example, the output node no where the output voltage Vout is output).

[0094] The 1-6th switch SW1-6 to the 1-7th switch SW1-7 may allow the first multi-stage amplifier circuit 220 and the second multi-stage amplifier circuit 230 to perform an amplification operation while dynamically operating in the first stage and the second stage.

[0095] The second multi-stage amplifier circuit 230 may be configured to be symmetrical with respect to the first multi-stage amplifier circuit 220 .

[0096] For example, the second multi-stage amplifier circuit 230 may include a second-stage P-type transistor TP1, a third-stage P-type transistor TP2, and a bias P-type transistor TBP. The term "P-type" is used to distinguish elements included in the second multi-stage amplifier circuit 230, but a "P-type transistor" may refer to a transistor configured so as to form a P channel.

[0097] The gate of the second-stage P-type transistor TP1 may be connected to the 2-1st capacitor C2-1 through the sixth node n6, and the 2-1st capacitor C2-1 is connected to the output terminal of the first-stage amplifier circuit 210. The drain of the second-stage P-type transistor TP1 may be connected to the gate of the third-stage P-type transistor TP2 and the source of the bias P-type transistor TBP through the seventh node n7. In some example embodiments, a power supply voltage may be supplied to the source of the second-stage P-type transistor TP1.

[0098] The source of the bias P-type transistor TBP can be connected to the drain of the second-stage P-type transistor TP1 through the seventh node n7, the gate of the bias P-type transistor TBP can be connected to the 2-2 capacitor C2-2 and the 2-3 switch SW2-3 through the eighth node n8, and the drain of the bias P-type transistor TBP can be connected to the 2-1 switch SW2-1, the 2-4 switch SW2-4 and the 1-6 switch SW1-6 through the ninth node n9.

[0099] The second-stage P-type transistor TP1 and the bias P-type transistor TBP may correspond to the second stage of the second multi-stage amplifier circuit 230 .

[0100] The gate of the third-stage P-type transistor TP2 may be connected to the drain of the second-stage P-type transistor TP1 through the seventh node n7, and the drain of the third-stage P-type transistor TP2 may be connected to the 2-7th switch SW2-7 through the tenth node n10. In some example embodiments, a power supply voltage may be supplied to the source of the third-stage P-type transistor TP2.

[0101] The second multi-stage amplifier circuit 230 may include 2-1st switch SW2-1 to 2-7th switch SW2-7 which may correspond to the above-mentioned dynamic switching circuit. In some example embodiments, the dynamic switching circuit of the stage of the second multi-stage amplifier circuit 230 including the 2-1st switch SW2-1 to the 2-7th switch SW2-7 may be defined as a second dynamic switching circuit.

[0102] The 2-1st switch SW2-1 may have one end “connected to one end of the 2-1st capacitor C2-1 and the gate of the second-stage P-type transistor TP1” through the sixth node n6 and the other end connected to the 2-1st current source IS2-1 through the ninth node n9 and the 2-4th switch SW2-4. The 2-2nd switch SW2-2 may have one end “connected to the drain of the second-stage P-type transistor TP1, the gate of the third-stage P-type transistor TP2 and the source of the bias P-type transistor TBP” through the seventh node n7 and the other end connected to the 2-2nd current source IS2-2. The 2-3rd switch SW2-3 may have one end connected to the gate of the bias P-type transistor TBP and the 2-2nd capacitor C2-2 through the eighth node n8 and the other end connected to the drain of the third-stage P-type transistor TP2 through the tenth node n10.

[0103] The 2-1st switch SW2-1 and the 2-3rd switch SW2-3 may sample the bias voltage across the 2-1st capacitor C2-1 and the 2-2nd capacitor C2-2 while dynamically operating in the first phase and the second phase.

[0104] The 2-4th switch SW2-4 may have one end connected to the drain of the bias P-type transistor TBP through the ninth node n9 and the other end connected to the 2-1st current source IS2-1. The 2-5th switch SW2-5 may have one end connected to the drain of the third-stage P-type transistor TP2 through the tenth node n10 and the other end connected to the 2-3rd current source IS2-3.

[0105] The 2-2nd switch SW2-2, the 2-4th switch SW2-4, and the 2-5th switch SW2-5 may supply the bias current from the 2-1st current source IS2-1 to the 2-3rd current source IS2-3 or block the supply of the bias current while dynamically operating in the first phase and the second phase.

[0106] The 2-6th switch SW2-6 may be included in the second multi-stage amplifier circuit 230, and may have one end connected to the drain of the second-stage P-type transistor TP1 through the seventh node n7 and the other end connected to the first multi-stage amplifier circuit 220. For example, the other end of the 2-6th switch SW2-6 may be connected to the drain of the bias N-type transistor TBN included in the first multi-stage amplifier circuit 220 through the fourth node n4.

[0107] The 2-7th switch SW2-7 may be included in the second multi-stage amplifier circuit 230, and may have one end connected to the drain of the third-stage P-type transistor TP2 through the tenth node n10 and the other end connected to the output node no.

[0108] The 2-6th switch SW2-6 and the 2-7th switch SW2-7 may allow the first multi-stage amplifier circuit 220 and the second multi-stage amplifier circuit 230 to perform an amplification operation while dynamically operating in the first phase and the second phase.

[0109] Figure 6 is a diagram showing some example embodiments Figure 5 A diagram of the first stage operation of the amplifier.

[0110] Reference Figure 6 , in the first stage for biasing, the 1-1th switch SW1-1 to the 1-5th switch SW1-5 included in the first multi-stage amplifier circuit 220 may be turned on, and the 1-6th switch SW1-6 to the 1-7th switch SW1-7 included in the first multi-stage amplifier circuit 220 may be turned off. Similarly, the 2-1st switch SW2-1 to the 2-5th switch SW2-5 included in the second multi-stage amplifier circuit 230 may be turned on, and the 2-6th switch SW2-6 to the 2-7th switch SW2-7 included in the second multi-stage amplifier circuit 230 may be turned off.

[0111] Each of the first multi-stage amplifier circuit 220 and the second multi-stage amplifier circuit 230 may operate as a current mirror to allow a bias current to flow to each stage. In the first stage, when the 1-1 switch SW1-1, the 1-2 switch SW1-2, the 1-4 switch SW1-4, the 2-1 switch SW2-1, the 2-2 switch SW2-2, and the 2-4 switch SW2-4 are turned on, the first node n1 and the fourth node n4 may be short-circuited and the sixth node n6 and the ninth node n9 may also be short-circuited. A portion of the first bias current (e.g., (1-α)IB1) from the 1-1 current source IS1-1 may be supplied to the drain of the second-stage N-type transistor TN1 through the fourth node n4 and a portion of the first bias current (αIB1) from the 1-2 current source IS1-2 may be supplied to the drain of the second-stage N-type transistor TN1 through the second node n2. Therefore, a first bias voltage VBN1 corresponding to the first bias current may be sampled across one end of the 1-1 capacitor C1-1.

[0112] Similarly, a portion of the first bias current (e.g., αIB1) may be output to the first current source IS2-1 through the ninth node n9, and a portion of the first bias current (e.g., (1-α)IB1) may be output to the second current source IS2-2 through the seventh node n7. A first bias voltage VBP1 corresponding to the first bias current IB1 may be sampled across one end of the 2-1st capacitor C2-1.

[0113] Return to Figure 4In the first stage, the common mode voltage VCM may be applied to the node nx of the first stage amplifier circuit 210 to generate the output common mode voltage and output offset of the first stage amplifier circuit 210 at the input node i (ni). Therefore, the 1-1 capacitor C1-1 and the 2-1 capacitor C2-1 may sample the output common mode voltage and output offset of the first stage amplifier circuit 210, so that the output offset of the first stage amplifier circuit 210 may be eliminated in the second stage amplification operation.

[0114] return Figure 6 , the 1-3rd current source IS1-3 may supply the second bias current (e.g., IB2) to the drain of the third-stage N-type transistor TN2 through the fifth node n5, and the second bias voltage VBN2 corresponding to the second bias current may be sampled across the 1-2nd capacitor C1-2. Similarly, the 2-3rd current source IS2-3 may supply the second bias current (e.g., IB2) to the drain of the third-stage P-type transistor TP2 through the tenth node n10, and the second bias voltage VBP2 corresponding to the second bias current may be sampled across the 2-2nd capacitor C2-2.

[0115] According to some example embodiments, in the first stage, the bias N-type transistor TBN and the second-stage N-type transistor TN1 and the bias P-type transistor TBP and the second-stage P-type transistor TP1 may be operated as a flip voltage follower by a dynamic switching circuit. For example, the bias N-type transistor TBN and the bias P-type transistor TBP may be operated as a flip voltage follower that uses a portion of the first bias current as a reference current source and uses the second-stage N-type transistor TN1 as feedback. For example, the first dynamic switching circuit may be configured to operate the bias N-type transistor TBN as a flip voltage follower based on short-circuiting the drain of the bias N-type transistor TBN and the gate of the second-stage N-type transistor TN1 in the first stage. The second dynamic switching circuit may be configured to operate the bias P-type transistor TBP as a flip voltage follower based on short-circuiting the drain of the bias P-type transistor TBP and the gate of the second-stage P-type transistor TP1 in the first stage.

[0116] Therefore, the bias N-type transistor TBN can output to the second node n2 a voltage obtained by reducing the "gate-source voltage of the bias N-type transistor TBN" from the second bias voltage VBN2 sampled across the 1-2 capacitor C1-2. The bias P-type transistor TBP can output to the seventh node n7 a voltage obtained by increasing the "source-gate voltage of the bias P-type transistor TBP" higher than the second bias voltage VBP2 sampled across the 2-2 capacitor C2-2. As a result, the bias N-type transistor TBN and the second-stage N-type transistor TN1 and the bias P-type transistor TBP and the second-stage P-type transistor TP1 can form a feedback loop through the third-stage N-type transistor TN2 and the third-stage P-type transistor TP2 operating as a common source amplifier when operating as a flip voltage follower, and can sample the second bias voltages VBN2 and VBP2 across the 1-2 capacitor C1-2 and the 2-2 capacitor C2-2.

[0117] In one embodiment, in the second stage, the second-stage N-type transistor TN1 and the second-stage P-type transistor TP1 may be biased with a voltage corresponding to the first bias current, and the bias N-type transistor TBN, the bias P-type transistor TBP, the third-stage N-type transistor TN2, and the third-stage P-type transistor TP2 may be biased with a voltage corresponding to the second bias current. According to sampling, the second-stage N-type transistor TN1 and the second-stage P-type transistor TP1 may be biased with the first bias voltages VBN1 and VBP1, the bias N-type transistor TBN and the bias P-type transistor TBP may be biased with the second bias voltages VBN2 and VBP2, the third-stage N-type transistor TN2 may be biased with a voltage that reduces the "gate-source voltage of the bias N-type transistor TBN" from the second bias voltage VBN2, and the third-stage P-type transistor TP2 may be biased with a voltage that increases the "source-gate voltage of the bias P-type transistor TBP" from the second bias voltage VBP2. Therefore, when the third-stage N-type transistor TN2 and the third-stage P-type transistor TP2 are biased with the second bias current IB2, the third-stage N-type transistor TN2 and the third-stage P-type transistor TP2 may operate in a subthreshold region.

[0118] Figure 7 is a diagram showing some example embodiments Figure 5 For ease of description, the description will be made without distinguishing between N-type and P-type unless necessary. Figure 7 Example embodiments of the present invention.

[0119] Reference Figure 7, in the second stage for amplification, the first switches SW1-1 and SW2-1 to the fifth switches SW1-5 and SW2-5 included in the first multi-stage amplifier circuit 220 and the second multi-stage amplifier circuit 230 may be turned off, and the sixth switches SW1-6 and SW2-6 to the seventh switches SW1-7 and SW2-7 may be turned on.

[0120] Based on the first to third switches SW1-1 to SW1-3 being turned off in the second stage, the second-stage transistors TN1 and TP1 may be biased with a voltage corresponding to the first bias current IB1, and the third-stage transistors TN2 and TP2 may be biased with a voltage corresponding to the second bias current IB2. For example, when each multi-stage amplifier circuit reaches a steady state in the second stage, the gate voltages of the second-stage transistors TN1 and TP1 may be biased with the first bias voltage sampled in the first stage. Each of the biased second-stage transistors TN1 and TP1 may flow the first bias current IB1.

[0121] In some example embodiments, each of the bias N-type transistor TBN and the bias P-type transistor TBP may operate as a floating current source that causes a portion (1-α)IB1 or αIB1 of the first bias current IB1 to flow. With respect to each multi-stage amplifier circuit, based on the sixth switches SW1-6 and SW2-6 being turned on in the second phase, the second node n2 may be connected to the ninth node n9 and the fourth node n4 may be connected to the seventh node n7. Each of the biased bias transistors TBN and TBP may cause a portion of the first bias current IB1 to flow through a path along which the multi-stage amplifier is connected through the second node n2 or the fourth node n4.

[0122] In addition to the sampled second bias voltage, each of the third-stage transistors TN2 and TP2 may be biased with a gate and source voltage of a biased N-type transistor TBN or a source and gate voltage of a biased P-type transistor TBP. As described above, in some example embodiments, when the 1-7th switch SW1-7 and the 2-7th switch SW2-7 are turned on in the second phase, each of the third-stage transistors TN2 and TP2 may flow a second bias current IB2. Each of the biased third-stage transistors TN2 and TP2 may be operated in a subthreshold region by biasing.

[0123] exist Figures 5 to 7In the above-described exemplary embodiment, each current source is shown to be included in each multi-stage amplifier circuit, but may be provided outside the multi-stage amplifier circuit. Each current source may be disconnected in the second stage by a switch (e.g., 1-2nd switch SW1-2, 1-4th switch SW1-4, 1-5th switch SW1-5, 2-2nd switch SW2-2, 2-4th switch SW2-4, and 2-5th switch SW2-5) connected to each current source, thereby reducing power consumption.

[0124] According to the above-described exemplary embodiments, the amplifier can form a dominant pole in the third stage, for example, by biasing each of the second stage and the third stage through a dynamic switching operation. Therefore, the amplifier can ensure stability and operate at low power.

[0125] In some example embodiments, the third-stage transistor may operate in the subthreshold region based on biasing by a bias transistor in the second stage of each multi-stage amplifier circuit. When the third-stage transistor operates in the subthreshold region using a resistor between the second-stage transistors through a voltage-resistor drop caused by the resistor, the amplifier may oscillate or the bandwidth of the amplifier may decrease depending on the resistance value. In some example embodiments, the above problem may be solved by using a bias transistor instead of a resistor and biasing a desired current.

[0126] In some example embodiments, the mismatch between the elements may be resolved by providing switches for dynamically operating the current mirror in the second stage transistor and the third stage transistor instead of replicating the current mirror. Through the dynamic current mirror operation, the amplifier according to some example embodiments may perform process-voltage-temperature (PVT) tracking without calibration.

[0127] Figure 8 is a diagram illustrating a differential amplifier according to some example embodiments.

[0128] Reference Figure 8 , the differential amplifier 300 according to some example embodiments may include a first-stage amplifier circuit 310 and a plurality of multi-stage amplifier circuits 320 .

[0129] The first stage amplifier circuit 310 may receive a differential input voltage pair Vin+ and Vin−, and may amplify the differential input voltage pair Vin+ and Vin− with a gain required by the first stage, and provide the amplified voltage pair to the plurality of multi-stage amplifier circuits 320 .

[0130] The first stage amplifier circuit 310 may include an amplifying element AE, a 1-1th input switch ISW1-1, a 1-2th input switch ISW1-2, a 2-1th input switch ISW2-1, and a 2-2nd input switch ISW2-2.

[0131] An input terminal of the amplification element AE may be connected to the 1-1th input switch ISW1-1, the 1-2th input switch ISW1-2, the 2-1th input switch ISW2-1, and the 2-2nd input switch ISW2-2 through the node x1 (nx1) and the node x2 (nx2), and an output terminal of the amplification element AE may be connected to an input node of the multi-stage amplifier circuit 320. The amplification element AE may amplify an applied differential input voltage pair Vin+ and Vin-, and may output the amplified voltage pair to the plurality of multi-stage amplifier circuits 320.

[0132] The 1-1st input switch ISW1-1 may be connected to the node x1 (nx1), and the 2-1st input switch ISW2-1 may be connected to the node x2 (nx2) to apply the common mode voltage VCM to the amplification element AE. The 1-1st input switch ISW1-1 and the 2-1st input switch ISW2-1 may be turned on in the first stage. As a result, the output common mode voltage and the output offset of the first stage amplifier circuit 310 may be applied to each of the plurality of multi-stage amplifier circuits 320 through the amplification element AE.

[0133] The 1-2nd input switch ISW1-2 may be connected to the node x1 (nx1), and the 2-2nd input switch ISW2-2 may be connected to the node x2 (nx2) to apply the differential input voltage pair Vin+ and Vin- to the amplification element AE. The 1-2nd input switch ISW1-2 and the 2-2nd input switch ISW2-2 may be turned off in the first phase and turned on in the second phase to apply the differential input voltage pair Vin+ and Vin- for the amplification operation to the amplification element AE.

[0134] Each of the plurality of multi-stage amplifier circuits 320 may be configured according to the above Figures 5 to 7 The differential output voltage pair Vout+ and Vout− of the differential input voltage pair Vin+ and Vin− may be output from each of the plurality of multi-stage amplifier circuits 320 .

[0135] For example, each of the plurality of multi-stage amplifier circuits 320 may be branched from the output terminal of the first-stage amplifier circuit 310, and may include a first multi-stage amplifier circuit and a second multi-stage amplifier circuit, the first multi-stage amplifier circuit and the second multi-stage amplifier circuit respectively including a second stage and a third stage. Each of the first multi-stage amplifier circuit and the second multi-stage amplifier circuit may be configured to sample a voltage corresponding to a first bias current corresponding to the second stage and a voltage corresponding to a second bias current corresponding to the third stage in a first stage, and bias the second stage with a voltage corresponding to the first bias current and bias the third stage with a voltage corresponding to the second bias current in a second stage.

[0136] The multistage amplifier circuits, amplifiers and / or differential amplifiers according to the above-described example embodiments may be used in an analog-to-digital converter (ADC) using a switched capacitor (SC) amplifier, such as a pipeline ADC, a pipeline successive approximation register (SAR) ADC or a cyclic ADC.

[0137] The multi-stage amplifier circuits, amplifiers, and / or differential amplifiers according to the above-described example embodiments may also be used in an ADC (such as a discrete-time delta signal ADC) using an SC integrator.

[0138] In some example embodiments, the multistage amplifier circuit, amplifier and / or differential amplifier according to some example embodiments may be arranged in at least two amplifier units. The at least two amplifier units may be connected in parallel. The at least two amplifier units connected in parallel may operate in opposite phases. The at least two amplifier units may be used as error amplifiers of a low voltage dropout regulator.

[0139] As described above, according to some example embodiments, a multi-stage amplifier circuit for dynamic biasing may be provided.

[0140] As described herein, any device, electronic device, module, unit and / or part thereof and / or any part thereof according to any of the example embodiments may include one or more instances of a processing circuit system (such as hardware including logic circuits; hardware / software combinations (such as processors that execute software); or combinations thereof), may be included in one or more instances of a processing circuit system (such as hardware including logic circuits; hardware / software combinations (such as processors that execute software); or combinations thereof), and / or may be implemented by one or more instances of a processing circuit system (such as hardware including logic circuits; hardware / software combinations (such as processors that execute software); or combinations thereof). For example, the processing circuit system may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a graphics processor (GPU), an application processor (AP), a digital signal processor (DSP), a microcomputer, a field programmable gate array (FPGA) and a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), a neural network processor (NPU), an electronic control unit (ECU), an image signal processor (ISP), and the like. In some example embodiments, the processing circuit system may include a non-transitory computer-readable storage device (e.g., memory) storing a program of instructions (e.g., a solid-state drive (SSD)) and a processor (e.g., CPU) configured to execute the program of instructions to implement the functions and / or methods performed by some or all of any device, electronic device, module, unit and / or part thereof according to any of the example embodiments.

[0141] While certain example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A multi-stage amplifier circuit comprising: a first multi-stage amplifier circuit and a second multi-stage amplifier circuit, The first multi-stage amplifier circuit comprises: The second stage N-type transistor is connected to the first stage through the 1-1 capacitor, and the 1-1 capacitor is connected to the gate of the second stage N-type transistor. a biasing N-type transistor connected to the drain of the second-stage N-type transistor and having a gate connected to the 1-2nd capacitor, A third-stage N-type transistor having a gate connected to the drain of the second-stage N-type transistor, a first current circuit configured to supply a first bias current and a second bias current, and a first dynamic switching circuit connected to the second-stage N-type transistor, the bias N-type transistor, the third-stage N-type transistor, and the first current circuit, and configured to: sample a voltage corresponding to the first bias current across the 1-1 capacitor in the first stage, and sample a voltage corresponding to the second bias current across the 1-2 capacitor based on forming a feedback loop including the bias N-type transistor and the third-stage N-type transistor, and The second multi-stage amplifier circuit comprises: The second-stage P-type transistor is connected to the first stage through the 2-1 capacitor, and the 2-1 capacitor is connected to the gate of the second-stage P-type transistor. a biasing P-type transistor connected to the drain of the second-stage P-type transistor and having a gate connected to the 2-2nd capacitor, A third-stage P-type transistor having a gate connected to the drain of the second-stage P-type transistor, a second current circuit configured to supply a first bias current and a second bias current, and A second dynamic switching circuit is connected to the second-stage P-type transistor, the bias P-type transistor, the third-stage P-type transistor and the second current circuit, and is configured to: sample a voltage corresponding to the first bias current across the 2-1 capacitor in the first stage, and sample a voltage corresponding to the second bias current across the 2-2 capacitor based on forming a feedback loop including the second-stage P-type transistor, the bias P-type transistor and the third-stage P-type transistor.

2. The multi-stage amplifier circuit according to claim 1, wherein: In order that the multi-stage amplifier circuit is configured to perform an amplification operation: The first dynamic switching circuit is configured to bias the second-stage N-type transistor with a voltage corresponding to the first bias current and bias the bias N-type transistor and the third-stage N-type transistor with a voltage corresponding to the second bias current in a second stage defined for the multi-stage amplifier circuit, and The second dynamic switching circuit is configured to bias the second-stage P-type transistor with a voltage corresponding to the first bias current and bias the bias P-type transistor and the third-stage P-type transistor with a voltage corresponding to the second bias current in the second phase.

3. The multi-stage amplifier circuit according to claim 2, wherein: The second-stage N-type transistor and the second-stage P-type transistor are configured to flow a first bias current based on a bias; and The third-stage N-type transistor and the third-stage P-type transistor are configured to flow a second bias current based on a bias.

4. The multi-stage amplifier circuit according to claim 1, wherein: The first dynamic switching circuit comprises: The 1-1st switch is connected to the gate of the second-stage N-type transistor, the 1-1st capacitor and the drain of the bias N-type transistor, The 1-2 switch is connected to the drain of the second-stage N-type transistor, the source of the bias N-type transistor and the first current circuit, The 1st-3rd switch is connected to the gate of the bias N-type transistor, the 1st-2nd capacitor and the drain of the third-stage N-type transistor, The 1-4 switch is connected to the drain of the bias N-type transistor and the first current circuit, The 1-5th switch is connected to the drain of the third-stage N-type transistor and the first current circuit, a 1-6 switch connected to the drain of the second-stage N-type transistor and the second multi-stage amplifier circuit, and The 1-7th switch is connected to the drain of the third-stage N-type transistor and the output terminal of the first multi-stage amplifier circuit and the second multi-stage amplifier circuit, and The second dynamic switching circuit comprises: The 2-1st switch is connected to the gate of the second-stage P-type transistor, the 2-1st capacitor and the drain of the bias P-type transistor, The 2-2 switch is connected to the drain of the second-stage P-type transistor, the source of the bias P-type transistor and the second current circuit, The 2-3 switch is connected to the gate of the bias P-type transistor, the 2-2 capacitor and the drain of the third-stage P-type transistor, The 2-4 switch is connected to the drain of the bias P-type transistor and the second current circuit, The 2-5th switch is connected to the drain of the third-stage P-type transistor and the second current circuit, a 2-6th switch connected to the drain of the second-stage P-type transistor and the first multi-stage amplifier circuit, and The 2-7th switch is connected to the drain of the third-stage P-type transistor and the output terminals of the first multi-stage amplifier circuit and the second multi-stage amplifier circuit.

5. The multi-stage amplifier circuit according to claim 4, wherein: The 1-1st to 1-5th switches and the 2-1st to 2-5th switches are configured to be turned on in the first phase, and The 1-6th switch and the 1-7th switch and the 2-6th switch and the 2-7th switch are configured to be opened in the first phase.

6. The multi-stage amplifier circuit according to claim 4, wherein: The first current circuit comprises: a 1-1th current source connected to the first terminal of the 1-1th switch and the drain of the bias N-type transistor and configured to supply a first part of the first bias current; a 1-2 th current source connected to the first end of the 1-2 th switch and configured to supply a second portion of the first bias current; and The 1-3rd current source is connected to the first end of the 1-5th switch and the drain of the third-stage N-type transistor and is configured to supply a second bias current.

7. The multi-stage amplifier circuit according to claim 4, wherein: The 1-1st to 1-5th switches and the 2-1st to 2-5th switches are configured to be turned off in a second stage defined for the multi-stage amplifier circuit, so that the multi-stage amplifier circuit is configured to perform an amplification operation, and The 1-6th switch and the 1-7th switch and the 2-6th switch and the 2-7th switch are configured to be turned on in the second phase.

8. The multi-stage amplifier circuit according to claim 6, wherein: The second current circuit comprises: a 2-1st current source connected to the first terminal of the 2-1st switch and the drain of the bias P-type transistor and configured to supply a second portion of the first bias current; a 2-2nd current source connected to the first end of the 2-2nd switch and configured to supply a first portion of the first bias current; and The 2-3rd current source is connected to the first terminal of the 2-5th switch and the drain of the third-stage P-type transistor and is configured to supply a second bias current.

9. The multi-stage amplifier circuit according to claim 8, wherein: The second end of the 1-1 switch is connected to the first end of the 1-1 capacitor and the gate of the second-stage N-type transistor through the first node; The second end of the 1-2 switch is connected to the source of the bias N-type transistor and the drain of the second-stage N-type transistor through the second node; The second end of the 1-3 switch is connected to the gate of the bias N-type transistor and the first end of the 1-2 capacitor through a third node; A first end of the 1-1 switch is connected to the 1-1 current source via the fourth node and the 1-4 switch; A first end of the 1-2 switch is connected to a 1-2 current source; A first end of the 1-3 switch is connected to the 1-3 current source via the fifth node and the 1-5 switch; The second end of the 2-1st switch is connected to the first end of the 2-1st capacitor and the gate of the second-stage P-type transistor through a sixth node; The second end of the 2-2 switch is connected to the source of the bias P-type transistor and the drain of the second-stage P-type transistor through the seventh node; The second end of the 2-3 switch is connected to the gate of the bias P-type transistor and the first end of the 2-2 capacitor through an eighth node; A first end of the 2-1st switch is connected to the 2-1st current source via the ninth node and the 2-4th switch; A first terminal of the 2-2nd switch is connected to a 2-2nd current source; and A first end of the 2-3rd switch is connected to the 2-3rd current source via the tenth node and the 2-5th switch.

10. The multi-stage amplifier circuit according to any one of claims 1 to 9, wherein: The first dynamic switching circuit is configured to operate the bias N-type transistor as a flipped voltage follower in the first stage based on shorting the drain of the bias N-type transistor and the gate of the second-stage N-type transistor, and The second dynamic switching circuit is configured to operate the bias P-type transistor as a flipped voltage follower based on shorting the drain of the bias P-type transistor and the gate of the second-stage P-type transistor in the first stage.

11. An amplifier, comprising: A first stage amplifier circuit is configured to receive an input voltage; as well as a first multi-stage amplifier circuit and a second multi-stage amplifier circuit branching from an output terminal of the first-stage amplifier circuit and each including a second stage and a third stage, Each of the first multi-stage amplifier circuit and the second multi-stage amplifier circuit is configured to sample a voltage corresponding to a first bias current and a voltage corresponding to a second bias current in a first stage, and bias the second stage with a voltage corresponding to the first bias current and bias the third stage with a voltage corresponding to the second bias current in a second stage.

12. The amplifier according to claim 11, wherein Each of the first multi-stage amplifier circuit and the second multi-stage amplifier circuit includes: a second-stage transistor having a gate connected to a first capacitor connected to an output terminal of the first-stage amplifier circuit; a bias transistor having a source connected to the drain of the second stage transistor and a gate connected to the second capacitor; and The third stage transistor has a gate connected to the drain of the second stage transistor.

13. The amplifier according to claim 12, wherein Each of the first multi-stage amplifier circuit and the second multi-stage amplifier circuit includes: a first switch having a first terminal connected to a first terminal of the first capacitor and a gate of the second stage transistor; a second switch having a first terminal connected to the drain of the second stage transistor and the source of the bias transistor and a second terminal connected to the second current source; a third switch having a first end connected to the gate of the bias transistor and the second capacitor and a second end connected to the drain of the third stage transistor; a fourth switch having a first end connected to the drain of the bias transistor and the second end of the first switch and a second end connected to the first current source; and The fifth switch has a first terminal connected to the drain of the third-stage transistor and a second terminal connected to the third current source.

14. The amplifier according to claim 13, wherein The bias transistor and the second stage transistor are configured to operate as a flip-flop voltage follower when the first switch is configured to be turned on.

15. The amplifier according to claim 13, wherein Each of the first multi-stage amplifier circuit and the second multi-stage amplifier circuit further includes: a sixth switch included in one of the first multi-stage amplifier circuit and the second multi-stage amplifier circuit and having a first end connected to the drain of the second-stage transistor and a second end connected to the other of the first multi-stage amplifier circuit and the second multi-stage amplifier circuit; and The seventh switch is included in one of the first multi-stage amplifier circuit and the second multi-stage amplifier circuit and has a first end connected to the drain of the third-stage transistor and a second end connected to the output terminal of the first multi-stage amplifier circuit and the second multi-stage amplifier circuit.

16. The amplifier according to claim 13, wherein The first to fifth switches are configured to be turned on in the first phase and turned off in the second phase.

17. The amplifier according to claim 15, wherein The sixth switch and the seventh switch are configured to be turned off in the first phase and turned on in the second phase.

18. An amplifier according to any one of claims 13 to 17, wherein Based on the first and fifth switches being configured to be turned on in the first phase, the first to fifth switches are configured to sample a voltage corresponding to the first bias current across the first capacitor and to sample a voltage corresponding to the second bias current across the second capacitor.

19. An amplifier according to any one of claims 13 to 17, wherein Based on the first to fifth switches being configured to be opened in the second stage, the first to fifth switches are configured to bias the second stage transistor with a voltage corresponding to the first bias current and bias the third stage transistor with a voltage corresponding to the second bias current.

20. A differential amplifier comprising: A first stage amplifier circuit is configured to receive a differential input voltage pair; as well as a plurality of multi-stage amplifier circuits configured to output a pair of differential voltage outputs for a pair of differential input voltages, Each of the plurality of multi-stage amplifier circuits comprises: a first multi-stage amplifier circuit and a second multi-stage amplifier circuit branching from an output terminal of the first-stage amplifier circuit and each including a second stage and a third stage, and Each of the first multi-stage amplifier circuit and the second multi-stage amplifier circuit is configured to sample a voltage corresponding to a first bias current and a voltage corresponding to a second bias current in a first stage, and bias the second stage with a voltage corresponding to the first bias current and bias the third stage with a voltage corresponding to the second bias current in a second stage.

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