Semiconductor device

Abstract

The purpose of the present invention is to provide a technique capable of suppressing heat generation of a first semiconductor switching element and a second semiconductor switching element. The semiconductor device includes a gate drive circuit that drives each of a first semiconductor switching element and a second semiconductor switching element on the basis of an input signal. When a first gate voltage applied to the first gate in order to turn on the first semiconductor switching element is lower than a first threshold value, the gate drive circuit turns off the first semiconductor switching element after turning off the second semiconductor switching element regardless of an input signal.

Description

Technical Field

[0001] The present invention relates to semiconductor devices. Background Art

[0002] At present, as power elements for inverter devices for driving motors, IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) made of cheap Si (silicon) are generally used. On the other hand, in recent years, more and more high-efficiency power elements made of WBG (Wide Band Gap) semiconductors, such as SiC (silicon carbide) or GaN (gallium nitride), are used.

[0003] However, since WBG semiconductors are expensive, they are not popular in cost-conscious civilian equipment. Therefore, it is proposed to use a parallel circuit composed of a small-sized SiC-MOSFET and a Si-IGBT in parallel in a product for a long time of use at low current, such as a drive motor for a compressor of a household air conditioner (for example, Patent Document 1). With such a product, it is expected that the cost reduction brought by the small size of the SiC-MOSFET and the efficiency improvement (i.e., loss reduction) brought by the good DC characteristics of the SiC-MOSFET at low current will be achieved.

[0004] Patent Document 1: Japanese Patent No. 6544316

[0005] If the gate voltage applied to the gate to turn on the power element is reduced, the turn-on voltage increases (i.e., the DC characteristics deteriorate). As a result, the loss increases, the heat generated by the power element increases, and sometimes the power element fails. Therefore, a structure is proposed in which a protection circuit is provided, which is used to suppress the heat generation of the power element by turning off the power element when the gate voltage becomes less than or equal to a specified value.

[0006] However, for example, in the above-mentioned parallel circuit, the gate voltage of the Si-IGBT is reduced. When the Si-IGBT of the power element is disconnected, if the SiC-MOSFET connected in parallel is in the on state, there is a problem that the heat generated due to the flow of all currents increases, and the SiC-MOSFET fails. Summary of the invention

[0007] Therefore, the present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a technology capable of suppressing heat generation of a first semiconductor switch element such as a Si element and a SiC element and a second semiconductor switch element.

[0008] The semiconductor device involved in the present invention comprises: a first semiconductor switch element, which has a first gate; a second semiconductor switch element, which is connected in parallel with the first semiconductor switch element, the second semiconductor switch element has a second gate, the band gap of the second semiconductor switch element is larger than that of the first semiconductor switch element, and the current carrying capacity is lower than that of the first semiconductor switch element; and a gate drive circuit, which drives each of the first semiconductor switch element and the second semiconductor switch element based on an input signal, and the gate drive circuit turns off the first semiconductor switch element after turning off the second semiconductor switch element regardless of the input signal when the first gate voltage applied to the first gate to turn on the first semiconductor switch element is lower than a first threshold value.

[0009] Effects of the Invention

[0010] According to the present invention, when the first gate voltage is lower than the first threshold value, the gate drive circuit turns off the first semiconductor switch element after turning off the second semiconductor switch element, regardless of the input signal. With such a structure, the heat generation of the first semiconductor switch element and the second semiconductor switch element can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a perspective view showing the outer structure of the semiconductor device according to the first embodiment.

[0012] Figure 2 It is a plan view showing the internal structure of the semiconductor device according to the first embodiment.

[0013] Figure 3 This is a diagram showing an application example of the semiconductor device according to the first embodiment.

[0014] Figure 4 This is a diagram showing the structure of a semiconductor device according to the first embodiment.

[0015] Figure 5 It is a timing chart showing the operation of the related semiconductor device.

[0016] Figure 6 This is a timing chart showing the operation of the semiconductor device according to the first embodiment.

[0017] Figure 7 This is a diagram showing a change in current when the first gate voltage does not change but the second gate voltage decreases.

[0018] Figure 8 It is a timing diagram that shows a specific situation.

[0019] Fig. 9This is a diagram showing the structure of a semiconductor device according to the second embodiment.

[0020] Fig.10 This is a timing chart showing the operation of the semiconductor device according to the second embodiment.

[0021] Fig.11 It is a diagram showing the structure of a semiconductor device according to a third embodiment.

[0022] Fig.12 It is a diagram showing the structure of a semiconductor device according to a fourth embodiment.

[0023] Fig.13 This is a diagram showing an example of a waveform output from the semiconductor device according to the fourth embodiment.

[0024] Fig.14 This is a diagram showing a change in current when the first gate voltage does not change but the second gate voltage increases.

[0025] Fig.15 This is a diagram showing the structure of a semiconductor device according to a fifth embodiment.

[0026] Fig.16 This is a timing chart showing the operation of the semiconductor device according to the fifth embodiment.

[0027] Fig.17 This is a diagram showing the structure of a semiconductor device according to a fifth embodiment.

[0028] Fig.18 This is a timing chart showing the operation of the semiconductor device according to the fifth embodiment. DETAILED DESCRIPTION

[0029] Below, while referring to the attached Figure 1 The embodiments are described. The features described in the following embodiments are only examples, and not all features are required. In addition, in the description shown below, the same structural elements are marked with the same or similar reference numerals in multiple embodiments, and the different structural elements are mainly described.

[0030] <Implementation Method 1>

[0031] Figure 1 is a perspective view showing the outer structure of the semiconductor device according to the first embodiment. Figure 2 FIG. 2 is a top view showing the internal structure of the semiconductor device. Figure 2 As shown, the semiconductor device according to the first embodiment includes a parallel circuit 1 , a gate drive circuit 2 , a lead frame 6 , and a package component 7 .

[0032] The parallel circuit 1 includes a first semiconductor switch element having a first gate and a second semiconductor switch element having a second gate, and the first semiconductor switch element and the second semiconductor switch element are connected in parallel.

[0033] In the first embodiment, the first semiconductor switching element is a Si element 1a made of Si (silicon). The following description assumes that the Si element 1a is an IGBT, but is not limited to an IGBT and may be a RC-IGBT (Reverse Conducting-IGBT) or a MOSFET.

[0034] In the first embodiment, the second semiconductor switch element is a SiC element 1b made of SiC (silicon carbide). However, the second semiconductor switch element is not limited to this as long as it has a larger band gap than the first semiconductor switch element, is small in size and has a low current carrying capacity. For example, the second semiconductor switch element may also be an element made of a WBG (Wide Band Gap) semiconductor such as GaN or diamond. The SiC element 1b made of SiC can improve efficiency, that is, reduce loss.

[0035] In the following, the SiC element 1 b is described as a MOSFET, which has low loss and is easy to obtain effects at low currents, but the present invention is not limited to this and may be an IGBT or the like.

[0036] In addition, the fact that the current carrying capacity of SiC element 1b is lower than that of Si element 1a corresponds to, for example, the following situation, that is, the saturation current value of SiC element 1b is smaller than the saturation current value of Si element 1a relative to the applied gate voltage. By making the current carrying capacity of SiC element 1b lower, the size of SiC element 1b can be made smaller than that of Si element 1a, so that the cost of semiconductor device can be expected to be reduced. In addition, when the current carrying capacity is set low, the on-voltage of SiC element 1b composed of WBG semiconductor at low current can also be made lower than the on-voltage of Si element 1a, so that loss can be reduced.

[0037] The gate drive circuit 2 is connected to the first gate of the Si element 1a and the second gate of the SiC element 1b, and drives each of the Si element 1a and the SiC element 1b as described later. The lead frame 6 is electrically connected to the parallel circuit 1 and the gate drive circuit 2. Figure 1 and Figure 2 As shown, the packaging member 7 covers the parallel circuit 1 , the gate driving circuit 2 , and the lead frame 6 in a state where a part of the lead frame 6 is exposed.

[0038] also, Figure 2 The number of parallel circuits 1 is 6, and the number of gate drive circuits 2 is 2, but it is not limited thereto. Figure 3As shown, a three-phase motor drive circuit can also be formed by connecting six parallel circuits 1 and six gate drive circuits 2 to a drive motor 8 that drives a compressor of a household appliance such as an air conditioner. For the sake of convenience, the following is an example of a structure in which one gate drive circuit 2 is provided for one parallel circuit 1.

[0039] Figure 4 The diagram shows the structure of the semiconductor device according to the first embodiment, and more specifically, shows the structures of the parallel circuit 1 and the gate drive circuit 2 according to the first embodiment in detail.

[0040] The collector and emitter of the Si element 1a are connected to the drain and source of the SiC element 1b, respectively, to form a parallel circuit 1. The first gate of the Si element 1a and the second gate of the SiC element 1b are connected to a gate drive circuit 2.

[0041] Before describing the details of the gate drive circuit 2 , an overview thereof will be described. An input signal selectively having on and off functions is input to the gate drive circuit 2 from an external controller such as a microcomputer (not shown).

[0042] The gate drive circuit 2 drives each of the Si element 1a and the SiC element 1b based on the input signal. In the first embodiment, as a principle, the gate drive circuit 2 turns on the Si element 1a and the SiC element 1b when the input signal is on, and turns off the Si element 1a and the SiC element 1b when the input signal is off.

[0043] However, as an exception to the above operation, when the first gate voltage is lower than the first threshold value, the gate drive circuit 2 turns off the Si element 1a after turning off the SiC element 1b, regardless of the input signal. In addition, the first gate voltage is a voltage applied to the first gate of the Si element 1a in order to turn on the Si element 1a. In addition, the second gate voltage described later is a voltage applied to the second gate of the SiC element 1b in order to turn on the SiC element 1b.

[0044] Next, the gate drive circuit 2 is described in detail. The gate drive circuit 2 includes a buffer circuit 2a, a control circuit 2b, a first buffer circuit 2c, a second buffer circuit 2d, and a power supply voltage drop protection circuit 2e. The buffer circuit 2a, the control circuit 2b, the first buffer circuit 2c, the second buffer circuit 2d, and the power supply voltage drop protection circuit 2e are each a logic circuit.

[0045] The buffer circuit 2a outputs an input signal while maintaining the input logic value.

[0046] When the input signal inputted via the buffer circuit 2a is switched on, the control circuit 2b turns on the Si element 1a and the SiC element 1b, and when the input signal is switched off, the Si element 1a and the SiC element 1b are turned off. As an example, the control circuit 2b may turn on the Si element 1a after turning on the Si element 1b when the input signal is switched on, and when the input signal is switched off, the control circuit 2b turns off the Si element 1a after turning off the SiC element 1b. That is, the control circuit 2b may also be configured to set a time difference between the turning on of the Si element 1a and the SiC element 1b, and to set a time difference between the turning off of the Si element 1a and the SiC element 1b. Thus, the current that originally flows only in the Si element 1a that is turned on first is diverted to the SiC element 1b at a ratio corresponding to the difference in DC characteristics between the elements.

[0047] When the control circuit 2b turns on the Si element 1a, the first buffer circuit 2c applies the voltage V1 supplied from the outside to the first gate of the Si element 1a. As a result, the first gate voltage is substantially the same as the voltage V1, and therefore is also referred to as the first gate voltage V1 in the following description. The first gate voltage V1 uses a voltage of about 15V, for example, but a voltage of a different value may be used depending on the characteristics of the Si element 1a.

[0048] When the control circuit 2b turns on the SiC device 1b, the second buffer circuit 2d applies the voltage V2 supplied from the outside to the second gate of the SiC device 1b. As a result, the second gate voltage is substantially the same as the voltage V2, and is therefore also referred to as the second gate voltage V2 in the following description. For example, a voltage of about 15V is used as the second gate voltage V2, but a voltage of a different value may be used depending on the characteristics of the SiC device 1b.

[0049] In the above structure in which voltages V1 and V2 are supplied from the outside, if voltages V1 and V2 are reduced due to some reasons such as abnormality, the on-voltage of Si element 1a and SiC element 1b rises (i.e., DC characteristics deteriorate). As a result, the loss increases, the heat generated by these elements increases, and sometimes Si element 1a and SiC element 1b fail. Therefore, the control circuit 2b and the power supply voltage drop protection circuit 2e have a protection function for suppressing the heat generated by Si element 1a and SiC element 1b. Next, the protection function is described.

[0050] The power supply voltage drop protection circuit 2e involved in the present embodiment 1 includes a first comparator 2e1. The first comparator 2e1 compares the first gate voltage V1 with a threshold voltage Vth1 corresponding to a predetermined first threshold. The threshold voltage Vth1 is, for example, a voltage lower than the standard first gate voltage V1 by a certain voltage (for example, 2 to 3V) in normal times, and is a voltage higher than the gate threshold of the Si element 1a, and can also be changed to a voltage of an appropriate value to match the characteristics of the Si element 1a. The first comparator 2e1 outputs different output signals to the control circuit 2b when the first gate voltage V1 is greater than or equal to the threshold voltage Vth1 and when it is lower than the threshold voltage Vth1. In addition, the first comparator 2e1 uses, for example, a comparator.

[0051] When receiving an output signal from the first comparator 2e1 indicating that the first gate voltage V1 is lower than the threshold voltage Vth1, the control circuit 2b turns off the Si element 1a after turning off the SiC element 1b regardless of the input signal.

[0052] Figure 5 1 is a timing diagram showing the operation of the semiconductor device according to the first embodiment. When the first gate voltage V1 is lower than the threshold voltage Vth1, the semiconductor device turns off the Si element 1a and keeps the SiC element 1b on. According to such a configuration, the Si element 1a, whose loss increases due to the decrease in the first gate voltage V1, is stopped, so that the heat generation of the Si element 1a can be suppressed.

[0053] However, if the Si element 1a is stopped, the current that originally flowed in the Si element 1a flows to the SiC element 1b, and the heat of the SiC element 1b increases, and the SiC element 1b may fail. This possibility is particularly high in compressor driving motors for household appliances such as home air conditioners, where the size of the SiC element 1b is reduced to reduce the cost of semiconductor devices and the DC characteristics of the SiC element 1b are improved to reduce losses.

[0054] Figure 6 1 is a timing diagram showing the operation of the semiconductor device according to the first embodiment. The semiconductor device according to the first embodiment turns off the Si element 1a after turning off the SiC element 1b, regardless of the input signal, when the first gate voltage V1 is lower than the threshold voltage Vth1. With such a structure, it is possible to suppress not only the heat generation of the Si element 1a but also the heat generation of the SiC element 1b. In addition, Figure 6 , reflecting the fact that the SiC element 1 b has a lower current carrying capacity than the Si element 1 a , the on-current of the SiC element 1 b is smaller than the on-current of the Si element 1 a .

[0055] However, the semiconductor device according to the first embodiment protects the Si element 1a and the SiC element 1b by monitoring the decrease of the first gate voltage V1 through the power supply voltage drop protection circuit 2e and the control circuit 2b, but does not monitor the decrease of the second gate voltage V2. The reason for this is described below.

[0056] Figure 7 This is a diagram showing the change in current flowing through the Si element 1a and the SiC element 1b when the first gate voltage V1 does not change and the second gate voltage V2 decreases. The horizontal axis represents the voltage applied between the collector and the emitter of the Si element 1a and between the drain and the source of the SiC element 1b (hereinafter referred to as "voltage across the two ends"), and the vertical axis represents the on-current of the Si element 1a and the SiC element 1b.

[0057] Figure 7 The dotted line represents the relationship between the voltage across the Si element 1a (i.e., the on-state voltage) and the on-state current. Figure 7 The thin solid line and the two-dot chain line show the relationship between the voltage across both ends of the SiC element 1b and the on-current. Figure 7 The thick solid line and the double-dashed line show the relationship between the voltage across the parallel circuit 1 and the on-current, which is substantially equivalent to the relationship between the voltage across the Si element 1a and the on-current and the relationship between the voltage across the SiC element 1b. The double-dashed line shows the relationship between the voltage across the second gate voltage V2 before it is reduced and the solid line shows the relationship between the voltage across the second gate voltage V2 and the on-current after it is reduced.

[0058] The voltage across each of the Si device 1a and the SiC device 1b before the second gate voltage V2 is reduced is V on1 , the on-current of Si element 1a is I A1 , the on-current of SiC element 1b is I B1 , the on-current of parallel circuit 1 is I T (=I A1 +I B1 ). In addition, the on-current of the Si element 1a and the on-current of the SiC element 1b are Figure 6 and Figure 7 is significantly different in that Figure 6 The figure shows I T For high current conditions, Figure 7 For convenience, I T This is the relationship for small current.

[0059] If the second gate voltage V2 decreases, it becomes difficult for current to flow through the SiC element 1b, so the slope of the thin line from the double-dashed line becomes smaller like the thin solid line. on1Change to a large V on2 , so that even if the second gate voltage V2 decreases, the on-current (I T As a result, the on-current of Si element 1a increases from I A1 Enlarge to I A2 , but the on-current of SiC element 1b is from I B1 Reduce to I B2 , I T =I A2 +I B2 Established.

[0060] Since the current carrying capacity of the Si element 1a is higher than that of the SiC element 1b, the allowable current of the Si element 1a has a margin compared to the allowable current of the SiC element 1b, and therefore, even if the on-current of the Si element 1a increases slightly, there will be no problem with the Si element 1a. Therefore, although the efficiency deteriorates slightly, even if the decrease of the second gate voltage V2 is not monitored, the operation of the system can be continued as long as the decrease of the on-current of the parallel circuit 1 is monitored.

[0061] <Summary of Implementation Method 1>

[0062] According to the semiconductor device of the first embodiment as described above, when the first gate voltage is lower than the first threshold value, the gate drive circuit 2 turns off the Si element 1a after turning off the SiC element 1b, regardless of the input signal. According to such a structure, the heat generation of the Si element 1a and the SiC element 1b can be suppressed, so the failure of the Si element 1a and the SiC element 1b caused by the heat can be suppressed. In addition, in the first embodiment, since the circuit for monitoring the decrease of the second gate voltage V2 is not required, the simplification, miniaturization and cost reduction of the semiconductor device can be expected.

[0063] <Implementation Method 2>

[0064] In the first embodiment, since a decrease in the second gate voltage V2 does not cause a problem in system operation, the gate drive circuit 2 only monitors a decrease in the first gate voltage V1 to protect the Si element 1 a and the SiC element 1 b .

[0065] However, the reduction of the second gate voltage V2 may cause undesirable specific conditions. The specific conditions include the following conditions, that is, Figure 8As shown in FIG. 1 , the second gate voltage V2 drops to the gate threshold of the SiC element 1b, and repeatedly rises and falls in a short time period near the gate threshold, thereby the SiC element 1b repeatedly switches on and off insufficiently. In this case, gate oscillation occurs, which may cause malfunction of the semiconductor device. Therefore, the semiconductor device according to the second embodiment is configured to monitor the decrease of the second gate voltage V2 and protect the Si element 1a and the SiC element 1b in order to avoid a specific situation, as described below.

[0066] Fig. 9 The diagram shows the structure of the semiconductor device according to the second embodiment, and more specifically, shows the structures of the parallel circuit 1 and the gate drive circuit 2 according to the second embodiment in detail. Fig. 9 The structure and Figure 4 The power supply voltage drop protection circuit 2e has the same structure as that of the power supply voltage drop protection circuit 2e except that a second comparator 2e2 is added.

[0067] The second comparator 2e2 compares the second gate voltage V2 with a threshold voltage Vth2 corresponding to a predetermined second threshold. The threshold voltage Vth2 is, for example, a voltage lower than the normal standard second gate voltage V2 by a certain voltage (for example, 2 to 3V), and is a voltage higher than the gate threshold of the SiC element 1b, and can also be changed to a voltage of an appropriate value to match the characteristics of the SiC element 1b. The second comparator 2e2 outputs different output signals to the control circuit 2b when the second gate voltage V2 is greater than or equal to the threshold voltage Vth2 and when it is lower than the threshold voltage Vth2. In addition, the second comparator 2e2 uses, for example, a comparator.

[0068] like Fig.10 As shown, when the control circuit 2b receives an output signal from the second comparator 2e2 that the second gate voltage V2 is lower than the threshold voltage Vth2, the SiC element 1b is disconnected regardless of the input signal. In addition, in the present embodiment 2, the control circuit 2b disconnects the SiC element 1b when the second gate voltage V2 is lower than the threshold voltage Vth2, but continues to drive the Si element 1a based on the input signal. In this case, the current that originally flows through the SiC element 1b flows through the Si element 1a. However, matching the fact that the current-carrying capacity of the Si element 1a is higher than the current-carrying capacity of the SiC element 1b, the allowable current of the Si element 1a has a margin compared to the allowable current of the SiC element 1b, so even if the on-current of the Si element 1a is slightly increased, there will be no problem with the Si element 1a.

[0069] <Summary of Implementation Method 2>

[0070] According to the semiconductor device according to the second embodiment as described above, when the second gate voltage is lower than the second threshold value, the gate drive circuit 2 turns off the SiC element 1b regardless of the input signal. Figure 8 That specific situation.

[0071] <Implementation Method 3>

[0072] In the first embodiment, the gate drive circuit 2 continues the operation of the system even when the second gate voltage V2 decreases. However, when the second gate voltage V2 decreases, the efficiency of the system deteriorates, so it is preferable to notify the user of the occurrence of abnormality and prompt repairs, etc. Therefore, the semiconductor device according to the third embodiment is configured to perform such notification as described below.

[0073] Fig.11 1 is a diagram showing a structure of a semiconductor device according to the third embodiment, and more specifically, is a diagram showing in detail the structures of a parallel circuit 1 and a gate drive circuit 2 according to the third embodiment. Fig.11 The structure and Figure 4 The gate driving circuit 2 has the same structure as that of the gate driving circuit 2 except that a power supply voltage drop detection circuit 2f is added.

[0074] The power supply voltage drop detection circuit 2f outputs a first abnormality signal to the outside, i.e., an external controller, from the output terminal 2g1 when the second gate voltage V2 is lower than a threshold voltage Vth2 corresponding to a predetermined second threshold. The power supply voltage drop detection circuit 2f is configured to include, for example, a comparator similar to the second comparator 2e2 described in the second embodiment.

[0075] When the control circuit 2b detects an abnormality different from the first abnormality signal in the semiconductor device and stops the operation of the system, the control circuit 2b outputs a second abnormality signal indicating an abnormality different from the first abnormality signal to the external controller from the output terminal 2g2.

[0076] <Summary of Implementation Method 3>

[0077] According to the semiconductor device involved in the third embodiment as described above, when the second gate voltage is lower than the second threshold value, the gate drive circuit 2 outputs the first abnormal signal to the external controller. According to such a structure, the operation of the system is continued, and the external controller is notified of the low second gate voltage, thereby urging the user to perform repairs, etc.

[0078] <Implementation Method 4>

[0079] Fig.121 is a diagram showing a structure of a semiconductor device according to the fourth embodiment, and more specifically, is a diagram showing in detail the structures of a parallel circuit 1 and a gate drive circuit 2 according to the fourth embodiment. Fig.12 The structure and Fig.11 The gate driving circuit 2 has the same structure as that in which an abnormal signal output circuit 2h is added.

[0080] The abnormal signal output circuit 2h outputs the first abnormal signal from the power supply voltage drop detection circuit 2f and the second abnormal signal from the control circuit 2b from one output terminal 2g3 in waveforms that can be distinguished from each other.

[0081] Fig.13 2 is a diagram showing an example of a waveform output from the abnormal signal output circuit 2h. Fig.13 (1) shows the waveform when the power supply voltage drop detection circuit 2f does not detect the first abnormality and the control circuit 2b detects the second abnormality (for example, the first gate voltage V1 is reduced). In this case, the second abnormality signal of the output level L2 is output. In addition, although not shown in the figure, when the power supply voltage drop detection circuit 2f does not detect the first abnormality and the control circuit 2b does not detect the second abnormality, a stable signal of the output level L0 is output to the external controller.

[0082] Fig.13 (2) and (3) show waveforms when the control circuit 2b does not detect the second abnormality and the power supply voltage drop detection circuit 2f detects the first abnormality (the second gate voltage V2 lower than the threshold voltage Vth2).

[0083] exist Fig.13 In (2), when the power supply voltage drop detection circuit 2f detects the first abnormality, the first abnormality signal of the output level L1 different from the output level L2 of the second abnormality signal is output. In this case, the external controller can distinguish the first abnormality signal from the second abnormality signal based on the difference in output levels.

[0084] exist Fig.13 In (3), when the power supply voltage drop detection circuit 2f detects the first abnormality, the first abnormality signal having the same output level as the output level L2 of the second abnormality signal is intermittently output for an output time T1. In this case, the external controller can distinguish the first abnormality signal from the second abnormality signal based on the difference in output time.

[0085] exist Fig.13 (4) shows waveforms when the power supply voltage drop detection circuit 2f and the control circuit 2b detect the first abnormality and the second abnormality, respectively. Fig.13In case (4), since the second abnormality is detected after the first abnormality, the abnormality signal is changed from the first abnormality signal having the output level L1 indicating the first abnormal state to the second abnormality signal having the output level L2 indicating the second abnormal state. The second abnormality is an abnormality in which both the Si element 1a and the SiC element 1b are disconnected and the system stops, so the output of the second abnormality signal is continued with priority over the output of the first abnormality signal. In addition, although not shown here, in the case where the first abnormality is detected after the second abnormality, the output of the second abnormality signal is continued with priority over the output of the first abnormality signal.

[0086] <Summary of Implementation Method 4>

[0087] According to the semiconductor device involved in the fourth embodiment as described above, the gate drive circuit 2 outputs the first abnormal signal and the second abnormal signal to the outside from an output terminal 2g3 in waveforms that can be identified from each other. According to such a structure, the number of output terminals of the gate drive circuit 2 can be reduced, so the miniaturization of the gate drive circuit 2 can be expected.

[0088] <Implementation method 5>

[0089] In the first embodiment, the gate drive circuit 2 continues the operation of the system even when the second gate voltage V2 decreases. On the other hand, when the second gate voltage V2 increases, the heat generation of the SiC element 1b increases. This case will be described below.

[0090] Fig.14 is a graph showing changes in the current flowing through the Si element 1a and the SiC element 1b when the first gate voltage V1 does not change and the second gate voltage V2 increases, and is similar to Figure 7 Same figure. However, in Fig.14 In FIG. 1 , the two-dot chain line indicates the relationship between the voltage across both ends and the on-current before the second gate voltage V2 rises, and the solid line indicates the relationship between the voltage across both ends and the on-current after the second gate voltage V2 rises.

[0091] The voltage across each of the Si device 1a and the SiC device 1b before the second gate voltage V2 rises is V on1 , the on-current of Si element 1a is I A1 , the on-current of SiC element 1b is I B1 , the on-current of parallel circuit 1 is I T (=I A1 +I B1 ).

[0092] When the second gate voltage V2 increases, current easily flows through the SiC element 1b, so the slope of the thin line from the double-dashed line increases like the thin solid line.on1 Change to a smaller V on3 , so that even if the second gate voltage V2 rises, the on-current (I T As a result, the on-current of Si element 1a increases from I A1 Reduce to I A3 , but the on-current of SiC element 1b is from I B1 Enlarge to I B3 , I T =I A3 +I B3 Established.

[0093] As the on-current of SiC element 1b increases, the heat generated by SiC element 1b increases, and SiC element 1b may fail. Therefore, the semiconductor device according to the fifth embodiment is configured to protect when the second gate voltage V2 increases, as described below.

[0094] Fig.15 1 is a diagram showing a structure of a semiconductor device according to the fifth embodiment, and more specifically, is a diagram showing in detail the structures of a parallel circuit 1 and a gate drive circuit 2 according to the fifth embodiment. Fig.15 The structure and Fig. 9 However, the second comparator 2e2 outputs different output signals to the control circuit 2b when the second gate voltage V2 is higher than a threshold voltage Vth3 corresponding to a predetermined third threshold and when it is lower than the threshold voltage Vth3.

[0095] like Fig.16 As shown, when the control circuit 2b receives an output signal from the second comparator 2e2 indicating that the second gate voltage V2 is higher than the threshold voltage Vth3, the SiC element 1b is disconnected regardless of the input signal. In addition, in the fifth embodiment, the control circuit 2b disconnects the SiC element 1b, but drives the Si element 1a based on the input signal. In this case, the current that originally flows through the SiC element 1b flows through the Si element 1a. However, in accordance with the fact that the current-carrying capacity of the Si element 1a is higher than that of the SiC element 1b, the allowable current of the Si element 1a has a margin compared to the allowable current of the SiC element 1b, so even if the on-current of the Si element 1a is slightly increased, there will be no problem with the Si element 1a.

[0096] Fig.17 It is a diagram showing another structure of the semiconductor device according to the fifth embodiment. Fig.17 The structure and Fig.15 The gate driving circuit 2 has the same structure as that of the gate driving circuit 2 except that a voltage reducing circuit 2i is added.

[0097] like Fig.18 As shown, when the voltage reduction circuit 2i receives an output signal from the second comparator 2e2 via the control circuit 2b indicating that the second gate voltage V2 is higher than the threshold voltage Vth3, the second gate voltage V2 is reduced in such a manner that the second gate voltage V2 is within a range greater than or equal to the gate threshold of the SiC element 1b.

[0098] <Summary of Implementation Method 5>

[0099] According to the semiconductor device according to the fifth embodiment as described above, when the second gate voltage V2 is higher than the third threshold value, the gate drive circuit 2 turns off the SiC element 1b or reduces the second gate voltage V2. According to such a structure, even if the second gate voltage V2 rises, the heat generation of the SiC element 1b can be suppressed, so the failure of the SiC element 1b caused by the heat can be suppressed. In addition, the fifth embodiment can be combined with any of the first to fourth embodiments.

[0100] In addition, the embodiments and modifications may be freely combined, and the embodiments and modifications may be appropriately modified or omitted.

[0101] The aspects of the present invention are summarized below as supplementary notes.

[0102] (Note 1)

[0103] A semiconductor device comprising:

[0104] A first semiconductor switch element having a first gate;

[0105] a second semiconductor switch element connected in parallel with the first semiconductor switch element, the second semiconductor switch element having a second gate, the second semiconductor switch element having a larger band gap than the first semiconductor switch element and a lower current carrying capacity than the first semiconductor switch element; and

[0106] a gate driving circuit that drives each of the first semiconductor switch element and the second semiconductor switch element based on an input signal,

[0107] When a first gate voltage applied to the first gate for turning on the first semiconductor switch element is lower than a first threshold value, the gate drive circuit turns off the first semiconductor switch element after turning off the second semiconductor switch element regardless of the input signal.

[0108] (Note 2)

[0109] The semiconductor device according to Supplementary Note 1, wherein:

[0110] The gate drive circuit turns off the second semiconductor switch element regardless of the input signal when a second gate voltage applied to the second gate for turning on the second semiconductor switch element is lower than a second threshold value.

[0111] (Note 3)

[0112] The semiconductor device according to Supplement 1 or 2, wherein:

[0113] The gate drive circuit outputs a first abnormal signal to the outside when a second gate voltage applied to the second gate for turning on the second semiconductor switch element is lower than a second threshold value.

[0114] (Note 4)

[0115] The semiconductor device according to Supplementary Note 3, wherein:

[0116] The gate drive circuit outputs the first abnormality signal and a second abnormality signal indicating an abnormality different from the first abnormality signal to the outside from one output terminal in waveforms that are distinguishable from each other.

[0117] (Note 5)

[0118] The semiconductor device according to Supplementary Note 1, wherein:

[0119] The gate drive circuit turns off the second semiconductor switch element or reduces the second gate voltage when a second gate voltage applied to the second gate in order to turn on the second semiconductor switch element is higher than a third threshold value.

[0120] (Note 6)

[0121] A semiconductor device according to any one of Supplementary Notes 2 to 4, wherein:

[0122] The gate driving circuit turns off the second semiconductor switch element or reduces the second gate voltage when the second gate voltage is higher than a third threshold value.

[0123] Description of the label

[0124] 1a Si element, 1b SiC element, 2 gate drive circuit, 2g3 output terminal.

Claims

1. A semiconductor device comprising: A first semiconductor switch element having a first gate; a second semiconductor switch element connected in parallel with the first semiconductor switch element, the second semiconductor switch element having a second gate, the second semiconductor switch element having a larger band gap than the first semiconductor switch element and a lower current carrying capacity than the first semiconductor switch element; and a gate driving circuit that drives each of the first semiconductor switch element and the second semiconductor switch element based on an input signal, When a first gate voltage applied to the first gate for turning on the first semiconductor switch element is lower than a first threshold value, the gate drive circuit turns off the first semiconductor switch element after turning off the second semiconductor switch element regardless of the input signal.

2. The semiconductor device according to claim 1, wherein The gate drive circuit turns off the second semiconductor switch element regardless of the input signal when a second gate voltage applied to the second gate for turning on the second semiconductor switch element is lower than a second threshold value.

3. The semiconductor device according to claim 1 or 2, wherein: The gate drive circuit outputs a first abnormal signal to the outside when a second gate voltage applied to the second gate for turning on the second semiconductor switch element is lower than a second threshold value.

4. The semiconductor device according to claim 3, wherein: The gate drive circuit outputs the first abnormality signal and a second abnormality signal indicating an abnormality different from the first abnormality signal to the outside from one output terminal in waveforms that are distinguishable from each other.

5. The semiconductor device according to claim 1, wherein The gate drive circuit turns off the second semiconductor switch element or reduces the second gate voltage when a second gate voltage applied to the second gate in order to turn on the second semiconductor switch element is higher than a third threshold value.

6. The semiconductor device according to any one of claims 2 to 4, wherein: The gate driving circuit turns off the second semiconductor switch element or reduces the second gate voltage when the second gate voltage is higher than a third threshold value.

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