Signal receiving method and chip

Abstract

The invention discloses a signal receiving method and a chip, and the method comprises the steps: generating an anti-interference detection signal based on a received first initial signal and a first external signal when the chip is in a non-anti-interference mode, and the anti-interference detection signal comprises an anti-interference enable signal, a receiving initial signal and a receiving end signal; after the anti-interference generation signal is received, an anti-interference processing signal is generated based on the receiving starting signal and the receiving ending signal; when the chip is in the anti-interference mode, based on the first anti-interference processing signal, the received second external signal is used as a complete signal, and the anti-interference mode is set when the anti-interference enable signal is effective, and the first anti-interference processing signal is an effective anti-interference processing signal. Compared with receiving the external signal based on the initial signal, the probability that the received external signal is an incomplete signal due to a time sequence error of the initial signal caused by interference can be reduced, so that the stability and the accuracy of signal transmission of the chip are improved.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a signal receiving method and a chip. Background Art

[0002] With the rapid development of information technology, chips have become an indispensable core component in modern electronic devices. Chips play a vital role in many fields such as military, civilian, communications, and finance. In addition, as the foundation of the information technology industry, chips play a fundamental and supporting role in the development of all walks of life. In particular, in the development of high-tech industries such as artificial intelligence, the Internet of Things, and 5G, chips have played a leading role.

[0003] However, when receiving external signals, the chip is susceptible to various interferences, such as electromagnetic interference (EMI) and radio frequency interference (RFI). Since there is no response mechanism for some signal transmissions, these interferences may cause signal quality degradation and even cause abnormal chip operation. For example, although the serial peripheral interface (SPI) communication protocol has the advantages of high-speed, full-duplex, and synchronous communication, it lacks a response mechanism. For example, during video data transmission, the chip usually receives the frame synchronization signal and starts to receive the SPI signal. If the chip encounters an unreasonable frame synchronization (Vsync) signal when receiving a frame of image data due to interference, it will cause image display errors and affect the normal operation of the chip's internal logic. Summary of the invention

[0004] The present application provides a signal receiving method and a chip, which are used to solve the problem that when the chip receives a signal, the normal operation of the internal logic of the chip is affected by interference.

[0005] In a first aspect, the present application provides a signal receiving method, comprising:

[0006] When the chip is in a non-anti-interference mode, an anti-interference detection signal is generated based on the received first start signal and the first external signal, wherein the anti-interference detection signal includes an anti-interference enable signal, a receiving start signal, and a receiving end signal;

[0007] After receiving the anti-interference generation signal, generating an anti-interference processing signal based on the reception start signal and the reception end signal in the anti-interference detection signal;

[0008] When the chip is in anti-interference mode, based on the first anti-interference processing signal, the received second external signal is regarded as a complete signal, wherein the anti-interference mode is set when the anti-interference enable signal is valid, and the first anti-interference processing signal is a valid anti-interference processing signal.

[0009] In a possible implementation, the step of generating an anti-interference detection signal based on the received first start signal and the first external signal includes:

[0010] At the end time of the first start signal, generating the receiving start signal;

[0011] At the end moment of the first external signal, generating the reception end signal;

[0012] and generating the anti-interference enable signal after receiving the first start signal and / or the first external signal;

[0013] Wherein, the receiving start signal and the receiving end signal include communication signals of a communication protocol.

[0014] In a possible implementation manner, the generating the anti-interference processing signal based on the receiving start signal and the receiving end signal in the anti-interference detection signal includes:

[0015] When the receiving start signal is received, the original level signal is flipped to obtain a first level signal;

[0016] When the receiving end signal is received, the first level signal is flipped to obtain the anti-interference processing signal.

[0017] In a possible implementation, if the original level signal is a low level signal, the moment of receiving the receiving start signal is used as the rising edge of the anti-interference processing signal, and the moment of receiving the receiving end signal is used as the falling edge of the anti-interference processing signal;

[0018] If the original level signal is a high level signal, the moment of receiving the receiving start signal is used as the falling edge of the anti-interference processing signal, and the moment of receiving the receiving end signal is used as the rising edge of the anti-interference processing signal.

[0019] In a possible implementation, based on the first anti-interference processing signal, treating the received second external signal as a complete signal includes:

[0020] treating a signal received between a rising edge of the first anti-interference processing signal and a falling edge of the first anti-interference processing signal as a complete signal; or

[0021] The signal received between the falling edge of the first anti-interference processing signal and the rising edge of the first anti-interference processing signal is regarded as a complete signal.

[0022] In a possible implementation manner, before treating the received second external signal as a complete signal based on the first anti-interference processing signal, the method further includes:

[0023] The anti-interference processing signal is controlled to be effective periodically, or after receiving a second start signal, the anti-interference processing signal is controlled to be effective.

[0024] In a possible implementation, the method further includes:

[0025] In the process of treating the received second external signal as a complete signal based on the first anti-interference processing signal, if a second anti-interference processing signal is received, the second anti-interference processing signal is ignored, wherein the second anti-interference processing signal is a valid anti-interference processing signal.

[0026] In a second aspect, the present application provides a chip, including: an anti-interference processing module, a signal receiving module and an anti-interference detection module;

[0027] The anti-interference processing module is configured to send the received first start signal and the first external signal to the signal receiving module in a non-anti-interference mode, and send the received second external signal to the signal receiving module based on the received first anti-interference processing signal in an anti-interference mode, wherein the anti-interference mode is set after receiving an anti-interference enable signal, and the first anti-interference processing signal is a valid anti-interference processing signal;

[0028] The signal receiving module is used to generate an anti-interference detection signal based on the received first start signal and the first external signal after receiving the anti-interference generation signal, and in the anti-interference mode, regard the received second external signal as a complete signal, wherein the anti-interference detection signal includes an anti-interference enable signal, a receiving start signal and a receiving end signal;

[0029] The anti-interference detection module is used to generate the anti-interference processing signal based on the received receiving start signal and the received end signal after receiving the anti-interference generation signal, and send the anti-interference enable signal to the anti-interference processing module.

[0030] In a possible implementation, the signal receiving module is specifically used to:

[0031] At the end time of the first start signal, generating the receiving start signal;

[0032] At the end moment of the first external signal, generating the reception end signal;

[0033] and generating the anti-interference enable signal after receiving the first start signal and / or the first external signal;

[0034] Wherein, the receiving start signal and the receiving end signal include communication signals of a communication protocol.

[0035] In a possible implementation, the anti-interference detection module is specifically used to:

[0036] When the receiving start signal is received, the original level signal is flipped to obtain a first level signal;

[0037] When the receiving end signal is received, the first level signal is flipped to obtain the anti-interference processing signal.

[0038] In a possible implementation, the anti-interference detection module is specifically used to:

[0039] If the original level signal is a low level signal, the moment of receiving the receiving start signal is used as the rising edge of the anti-interference processing signal, and the moment of receiving the receiving end signal is used as the falling edge of the anti-interference processing signal;

[0040] If the original level signal is a high level signal, the moment of receiving the start signal is used as the falling edge of the anti-interference processing signal, and the moment of receiving the end signal is used as the rising edge of the anti-interference processing signal.

[0041] In a possible implementation, the anti-interference detection module is specifically used to:

[0042] treating a signal received between a rising edge of the first anti-interference processing signal and a falling edge of the first anti-interference processing signal as a complete signal; or

[0043] The signal received between the falling edge of the first anti-interference processing signal and the rising edge of the first anti-interference processing signal is regarded as a complete signal.

[0044] In a possible implementation, the signal receiving module is further used for:

[0045] periodically sending the first anti-interference processing signal to the anti-interference detection module; or

[0046] After receiving the second start signal, the first anti-interference processing signal is sent to the anti-interference detection module.

[0047] In a possible implementation, the anti-interference processing module is further used to:

[0048] In the process of receiving the second external signal based on the first anti-interference processing signal, if a second anti-interference processing signal is received, the second anti-interference processing signal is ignored, wherein the second anti-interference processing signal is a valid anti-interference processing signal.

[0049] The beneficial effects of the present invention are as follows:

[0050] The present application discloses a signal receiving method and chip, when the chip is in a non-anti-interference mode, based on the received first start signal and the first external signal, an anti-interference detection signal is generated, wherein the anti-interference detection signal includes an anti-interference enable signal, a receiving start signal and a receiving end signal; after receiving the anti-interference generation signal, an anti-interference processing signal is generated based on the receiving start signal and the receiving end signal; when the chip is in the anti-interference mode, based on the first anti-interference processing signal, the received second external signal is regarded as a complete signal, wherein the anti-interference mode is set when the anti-interference enable signal is valid, and the first anti-interference processing signal is a valid anti-interference processing signal. Since when the chip is in the anti-interference mode, based on the first anti-interference processing signal, the received second external signal is regarded as a complete signal, compared with receiving the external signal based on the start signal, the timing error of the start signal caused by interference can be reduced, resulting in the probability that the received external signal is an incomplete signal, thereby improving the stability and accuracy of the chip transmission signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0052] Figure 1 A schematic diagram of image data transmission provided in an embodiment of the present application;

[0053] Figure 2 A schematic diagram of another image data transmission provided by an embodiment of the present application;

[0054] Figure 3a A schematic diagram of an image data transmission display provided in an embodiment of the present application;

[0055] Figure 3b A schematic diagram of an image data transmission display provided in an embodiment of the present application;

[0056] Figure 4A schematic diagram of a flow chart of a signal receiving method provided in an embodiment of the present application;

[0057] Figure 5 A schematic diagram of generating an anti-interference detection signal provided in an embodiment of the present application;

[0058] Figure 6 A schematic diagram of generating an anti-interference processing signal provided in an embodiment of the present application;

[0059] Figure 7 A schematic diagram of another method for generating an anti-interference processing signal provided in an embodiment of the present application;

[0060] Figure 8 A schematic diagram of the structure of a chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0061] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0062] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the attached claims.

[0063] The communication between chips is achieved through signal transmission, such as the SPI communication protocol, which is a high-speed, full-duplex, synchronous communication bus. The advantages of the SPI communication protocol are that it supports full-duplex communication, the communication method is relatively simple, and the data transmission rate is relatively fast; the disadvantages are that there is no specified flow control, no response mechanism, and there are certain defects in data reliability.

[0064] In the field of image display, video images have a refresh rate attribute. The refresh rate of a video refers to the number of times the screen is refreshed per second, measured in Hertz (Hz). When using SPI signals for video data transmission, a vertical synchronization signal (Vsync signal) needs to be added. VSync is a technology used to synchronize the display refresh rate and graphics rendering frame rate in order to avoid screen tearing and reduce power consumption.

[0065] The principle of the Vsync signal is to limit the graphics rendering frame rate to a fixed frequency according to the refresh rate of the display, so that each refresh is completed at the moment when the display scan line is refreshed. The Vsync signal is generally the first signal that the chip needs to recognize in the overall signal transmission process. When the chip recognizes the signal, it will recognize the SPI signal, which is the data of a frame of image.

[0066] In specific implementation, when the chip is receiving data of a frame of image, if a Vsync signal with unreasonable timing appears, it may be sent incorrectly or it may be a signal caused by interference. At this time, after receiving the Vsync signal, the chip will fill the data in the middle of the image into the first data, resulting in image display errors. In severe cases, the internal logic of the chip cannot work normally.

[0067] For example, Figure 1 As shown, one frame of image has 4096 data. Under normal circumstances, after the chip receives the Vsync signal, it will receive 4096 signals transmitted by the SPI signal, and fill the 4096 signals in sequence from the first position to the 4096th position in the display area.

[0068] If the chip has an unreasonable Vsync signal during the transmission of these 4096 signals, for example, Figure 2 As shown, an unreasonable Vsync signal appears at the position of the 2048th image data transmitted by the SPI signal, which will cause the 2049th image data to be filled into the position of the 1st image data in the display area, and the 2050th image data to be filled into the position of the 2nd image data in the real area..., and there is no image data to be filled after the 2049th position. The filling of the wrong position of the image data will cause incorrect display on the screen.

[0069] like Figure 3a As shown in the figure, it is a schematic diagram of the normal display of the display area. Figure 3b As shown, the upper half of the display area displays the image of the lower half, while the lower half of the display area does not display the image.

[0070] By adopting the signal receiving method and chip provided in the embodiments of the present application, when the chip is in the anti-interference mode, the chip treats the received external signal as a complete signal based on the anti-interference processing signal. Compared with receiving the external signal based on the start signal, the probability of the received external signal being an incomplete signal due to the timing error of the start signal caused by interference can be reduced, thereby improving the stability and accuracy of the chip transmission signal.

[0071] A signal receiving method and chip provided in an embodiment of the present application are described in detail below with reference to the accompanying drawings.

[0072] like Figure 4 FIG. 1 is a flow chart of a signal receiving method provided in an embodiment of the present application, which specifically includes the following steps:

[0073] S401: When the chip is in a non-anti-interference mode, generate an anti-interference detection signal based on a received first start signal and a first external signal, wherein the anti-interference detection signal includes an anti-interference enable signal, a receiving start signal, and a receiving end signal;

[0074] S402: after receiving the anti-interference generation signal, generating an anti-interference processing signal based on the receiving start signal and the receiving end signal in the anti-interference detection signal;

[0075] S403: When the chip is in an anti-interference mode, based on a first anti-interference processing signal, the received second external signal is regarded as a complete signal, wherein the anti-interference mode is set when the anti-interference enable signal is valid, and the first anti-interference processing signal is a valid anti-interference processing signal.

[0076] The present application discloses a signal receiving method, when the chip is in a non-anti-interference mode, based on the received first start signal and the first external signal, an anti-interference detection signal is generated, wherein the anti-interference detection signal includes an anti-interference enable signal, a receiving start signal and a receiving end signal; after receiving the anti-interference generation signal, an anti-interference processing signal is generated based on the receiving start signal and the receiving end signal; when the chip is in the anti-interference mode, based on the first anti-interference processing signal, the received second external signal is regarded as a complete signal, wherein the anti-interference mode is set when the anti-interference enable signal is valid, and the first anti-interference processing signal is a valid anti-interference processing signal. Since when the chip is in the anti-interference mode, based on the first anti-interference processing signal, the received second external signal is regarded as a complete signal, compared with receiving the external signal based on the start signal, the timing error of the start signal caused by interference can be reduced, resulting in the probability that the received external signal is an incomplete signal, thereby improving the stability and accuracy of the chip transmission signal.

[0077] It should be noted that, in a specific implementation, the first external signal, the second external signal, the first start signal and the second start signal may be communication signals of various types of communication protocols, i.e., communication protocol signals, for example, communication signals of the SPI communication protocol, MIPI communication protocol signals, etc. When the first external signal and the second external signal are both SPI signals, the first start signal and the second start signal are both frame synchronization signals.

[0078] In a specific implementation, after the chip is powered on, it is in an initial state and then enters a working state. When the chip does not receive an anti-interference enable signal, the chip is in a non-anti-interference mode. In the non-anti-interference mode, the chip generates an anti-interference detection signal based on the received first start signal and the first external signal, wherein the anti-interference detection signal includes a receiving start signal, a receiving end signal and an anti-interference enable signal.

[0079] Among them, the first external signal and the second external signal can be a single signal or a group of signals. That is to say, when there is only one signal that needs to be processed for anti-interference, the first external signal and the second external signal are both single signals; when there are multiple signals that need to be processed for anti-interference, the first external signal and the second external signal are both a group of signals.

[0080] Specifically, the chip generates a receiving start signal at the end moment of receiving the first start signal, generates a receiving end signal at the moment of receiving the last signal in the first external signal, and generates an anti-interference enable signal after receiving the first start signal and / or the first external signal, wherein the receiving start signal and the receiving end signal include communication signals of the communication protocol, that is, communication protocol signals, such as communication protocol signals between multiple devices and communication protocol signals between multiple modules in a single device. The communication protocols here include, for example, SPI communication protocol, MIPI communication protocol, etc.

[0081] like Figure 5 As shown, it is a schematic diagram of generating an anti-interference detection signal provided in an embodiment of the present application. When the Vsync signal (first start signal) is received, a receiving start signal S1 is generated, and at the same time, the SPI signal (first external signal) is also transmitted; at the moment when the SPI signal transmission is completed, that is, when the last signal transmission of the SPI signal is completed, a receiving end signal E1 is generated.

[0082] In the embodiment of the present application, the anti-interference enable signal is a switch signal of the anti-interference function. After the anti-interference enable signal is generated, the operator can judge whether to enable the anti-interference function according to the interference enable signal. For example, when the structure of the external signal received by the chip is simple, the operator can set the anti-interference enable signal to 0, that is, the anti-interference function of the chip is not turned on; when the structure of the external signal received by the chip is complex and the timing requirement is high, the anti-interference enable signal is 1, that is, the anti-interference function of the chip is turned on, and the anti-interference enable signal is 1, that is, the anti-interference enable signal generated after receiving the start signal and / or the first external signal.

[0083] In one embodiment, after receiving the anti-interference generation signal, an anti-interference processing signal is generated based on the reception start signal and the reception end signal in the anti-interference detection signal. Specifically, the moment of receiving the reception start signal is used as the rising edge of the anti-interference processing signal, and the moment of receiving the reception end signal is used as the falling edge of the anti-interference processing signal.

[0084] refer to Figure 6 , the moment when the receiving start signal S1 is generated is used as the rising edge of the anti-interference processing signal A1; the moment when the receiving end signal E1 is generated is used as the falling edge of the anti-interference processing signal A1.

[0085] In a specific implementation, after generating a valid anti-interference enable signal and an anti-interference processing signal, the chip switches the chip from a non-anti-interference mode to an anti-interference mode. When the chip is in the anti-interference mode, based on the anti-interference processing signal, the received second external signal is regarded as a complete signal. The anti-interference processing signal here is an effective anti-interference processing signal.

[0086] In a specific implementation, the anti-interference processing signal may be controlled to be effective periodically, or the anti-interference processing signal may be controlled to be effective after receiving the second start signal.

[0087] For example, the second external signal is an SPI signal. If the screen refresh rate remains unchanged, the anti-interference processing signal can be periodically controlled to be effective. If the screen refresh rate changes, the anti-interference processing signal can be controlled to be effective after receiving the frame synchronization signal.

[0088] In the embodiment of the present application, the anti-interference enable signal is valid, that is, the anti-interference enable signal is 1.

[0089] Specifically, when the chip is in the anti-interference mode, the signal received between the rising edge of the anti-interference processing signal and the falling edge of the anti-interference processing signal is regarded as a complete signal.

[0090] For example, a signal received between a rising edge of the anti-interference processing signal and a falling edge of the anti-interference processing signal is used as one frame of image data.

[0091] In a specific implementation, after receiving the second start signal, the anti-interference processing signal is controlled to be valid, that is, the first anti-interference processing signal, and the second external signal received between the rising edge of the first anti-interference processing signal and the falling edge of the first anti-interference processing signal is regarded as a complete signal. If, during the process of the second external signal received between the rising edge of the first anti-interference processing signal and the falling edge of the first anti-interference signal being regarded as a complete signal, a valid anti-interference processing signal, that is, the second anti-interference processing signal, is received, the second anti-interference processing signal is ignored.

[0092] For example, Figure 7 As shown, when the chip is in anti-interference mode, after the first Vsync signal triggers the anti-interference processing signal A1, the chip uses the SPI signal received at the rising edge of the anti-interference processing signal A1 and the falling edge of the anti-interference processing signal A1 as a frame of image data, and between the rising edge of the anti-interference processing signal A1 and the falling edge of the anti-interference processing signal A1, the second Vsync signal triggers the anti-interference processing signal A2, at this time, the anti-interference processing signal A2 is ignored.

[0093] Since the anti-interference processing signal A2 is ignored, and the anti-interference processing signal A2 is triggered after receiving the second Vsync signal, the second Vsync signal is also ignored. The second Vsync signal is an unreasonable Vsync signal in terms of timing. Therefore, the unreasonable Vsync signal in terms of timing will not affect the transmission of normal signals.

[0094] Based on the same inventive concept, an embodiment of the present application also provides a chip, the principle of which to solve the technical problem is similar to that of the above-mentioned signal receiving method. The implementation of the chip can refer to the implementation of the signal receiving method, and the repeated parts will not be repeated.

[0095] like Figure 8 , which is a schematic diagram of the structure of a chip provided in an embodiment of the present application, including: an anti-interference processing module 81, a signal receiving module 82 and an anti-interference detection module 83;

[0096] The first input end of the anti-interference processing module 81 is used to input the start signal and the external signal, the output end of the anti-interference processing module 81 is electrically connected to the input end of the signal receiving module 82, the first output end of the signal receiving module 82 is electrically connected to the input end of the anti-interference detection module 83, and the output end of the anti-interference detection module 83 is electrically connected to the second input end of the anti-interference processing module 81.

[0097] an anti-interference processing module 81, configured to send the received first start signal and the first external signal to the signal receiving module in a non-anti-interference mode, and to send the received second external signal to the signal receiving module based on the received first anti-interference processing signal in an anti-interference mode, wherein the anti-interference mode is set after receiving an anti-interference enabling signal, and the first anti-interference processing signal is a valid anti-interference processing signal;

[0098] A signal receiving module 82, configured to generate an anti-interference detection signal based on the received first start signal and the first external signal after receiving the anti-interference generation signal, and in the anti-interference mode, regard the received second external signal as a complete signal, wherein the anti-interference detection signal includes an anti-interference enable signal, a receiving start signal and a receiving end signal;

[0099] The anti-interference detection module 83 is used to generate the anti-interference processing signal based on the received receiving start signal and the received end signal after receiving the anti-interference generation signal, and send the anti-interference enable signal to the anti-interference processing module.

[0100] It should be noted that the signal receiving module 82 in the embodiment of the present application is also provided with a second output terminal. The second output terminal of the signal receiving module 82 outputs a first external signal or a complete signal after anti-interference processing. For example, if the external signal is image data, the signal receiving module 82 processes the image data sent by the anti-interference processing module 81, and outputs the processed image data. The output processed image data will be filled in the display area in sequence.

[0101] In the embodiment of the present application, after the chip is powered on, the start signal and the external signal are received by the anti-interference processing module 81. At this time, the chip is in a non-anti-interference mode after power-on. Therefore, the anti-interference processing module 81, the signal receiving module 82 and the anti-interference detection module 83 are all in the non-anti-interference mode;

[0102] When the anti-interference processing module 81 is in the non-anti-interference mode, the received start signal and external signal are directly sent to the signal receiving module 82. When the signal receiving module 82 is in the state of receiving the anti-interference generation signal, after receiving the first start signal and the first external signal, an anti-interference detection signal is generated based on the first start signal and the first external signal, and the anti-interference detection signal is sent to the anti-interference detection module 83, wherein the anti-interference detection signal includes a receiving start signal, a receiving end signal and an anti-interference enable signal;

[0103] After receiving the anti-interference generation signal, the anti-interference detection module 83 generates an anti-interference processing signal based on the reception start signal in the received anti-interference detection signal and the reception end signal in the anti-interference detection signal. The anti-interference detection module 83 sends the anti-interference enable signal in the anti-interference detection signal to the anti-interference processing module 81. At this time, the anti-interference enable signal is valid.

[0104] After the anti-interference processing module 81 receives a valid anti-interference enable signal, the anti-interference function is turned on, and the anti-interference processing module 81 switches from the non-anti-interference mode to the anti-interference mode;

[0105] After the anti-interference processing module 81 is in the anti-interference mode, after receiving the start signal, the start signal is sent to the anti-interference detection module 83 through the signal receiving module 82. After receiving the start signal, the anti-interference detection module 83 sends the anti-interference processing signal to the anti-interference processing module 81. After receiving the anti-interference processing signal, the anti-interference processing module 81 regards the received external signal as a complete signal based on the anti-interference processing signal.

[0106] In a specific implementation, when the anti-interference processing module 81 is in a non-anti-interference mode, the received initial signal will not be ignored. When the anti-interference processing module 81 is in an anti-interference mode, if another anti-interference processing signal is received within the effective duration of the anti-interference processing signal, the anti-interference processing signal will be ignored. Since the other anti-interference processing signal is triggered by another initial signal, the anti-interference processing module 81 ignores the other initial signal.

[0107] The effective duration of the anti-interference processing signal generated by the anti-interference detection module 83 is the same as the duration of the complete signal.

[0108] The receiving start signal is generated when the signal receiving module 82 receives the first starting signal, and the receiving end signal is generated when the signal receiving module 82 completes receiving the first external signal. The anti-interference detection module 83 generates an anti-interference processing signal by receiving the receiving start signal and the receiving end signal.

[0109] In one embodiment, the signal receiving module is specifically used for:

[0110] At the end time of the first start signal, generating the receiving start signal;

[0111] At the end moment of the first external signal, generating the reception end signal;

[0112] And generating the anti-interference enable signal after receiving the first start signal and / or the first external signal.

[0113] Wherein, the receiving start signal and the receiving end signal include communication signals of a communication protocol.

[0114] In one embodiment, the anti-interference detection module is specifically used to:

[0115] When the receiving start signal is received, the original level signal is flipped to obtain a first level signal;

[0116] When the receiving end signal is received, the first level signal is flipped to obtain the first anti-interference processing signal.

[0117] In one embodiment, the anti-interference detection module is specifically used to:

[0118] If the original level signal is a low level signal, the moment of receiving the receiving start signal is used as the rising edge of the anti-interference processing signal, and the moment of receiving the receiving end signal is used as the falling edge of the anti-interference processing signal;

[0119] If the original level signal is a high level signal, the moment of receiving the start signal is used as the falling edge of the anti-interference processing signal, and the moment of receiving the end signal is used as the rising edge of the anti-interference processing signal.

[0120] In one embodiment, the anti-interference detection module is specifically used for:

[0121] treating a signal received between a rising edge of the first anti-interference processing signal and a falling edge of the first anti-interference processing signal as a complete signal; or

[0122] The signal received between the falling edge of the first anti-interference processing signal and the rising edge of the first anti-interference processing signal is regarded as a complete signal.

[0123] In one embodiment, the signal receiving module is further used for:

[0124] periodically sending the first anti-interference processing signal to the anti-interference detection module; or

[0125] After receiving the second start signal, the first anti-interference processing signal is sent to the anti-interference detection module.

[0126] In one embodiment, the signal receiving module is further used for:

[0127] After receiving the second start signal, the anti-interference detection module is triggered to send the first anti-interference processing signal.

[0128] In one embodiment, the anti-interference processing module is further used for:

[0129] In the process of receiving the second external signal based on the first anti-interference processing signal, if a second anti-interference processing signal is received, the second anti-interference processing signal is ignored, wherein the second anti-interference processing signal is a valid anti-interference processing signal.

[0130] The present application discloses a signal receiving method and chip, when the chip is in a non-anti-interference mode, based on the received first start signal and the first external signal, an anti-interference detection signal is generated, wherein the anti-interference detection signal includes an anti-interference enable signal, a receiving start signal and a receiving end signal; after receiving the anti-interference generation signal, an anti-interference processing signal is generated based on the receiving start signal and the receiving end signal; when the chip is in the anti-interference mode, based on the first anti-interference processing signal, the received second external signal is regarded as a complete signal, wherein the anti-interference mode is set when the anti-interference enable signal is valid, and the first anti-interference processing signal is a valid anti-interference processing signal. Since when the chip is in the anti-interference mode, based on the first anti-interference processing signal, the received second external signal is regarded as a complete signal, compared with receiving the external signal based on the start signal, the timing error of the start signal caused by interference can be reduced, resulting in the probability that the received external signal is an incomplete signal, thereby improving the stability and accuracy of the chip transmission signal.

[0131] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0132] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0133] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0134] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0135] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A signal receiving method, characterized in that: include: When the chip is in a non-anti-interference mode, an anti-interference detection signal is generated based on the received first start signal and the first external signal, wherein the anti-interference detection signal includes an anti-interference enable signal, a receiving start signal, and a receiving end signal; After receiving the anti-interference generation signal, generating an anti-interference processing signal based on the reception start signal and the reception end signal in the anti-interference detection signal; When the chip is in anti-interference mode, based on the first anti-interference processing signal, the received second external signal is regarded as a complete signal, wherein the anti-interference mode is set when the anti-interference enable signal is valid, and the first anti-interference processing signal is a valid anti-interference processing signal.

2. The method according to claim 1, characterized in that The step of generating an anti-interference detection signal based on the received first start signal and the first external signal comprises: At the end time of the first start signal, generating the receiving start signal; At the end moment of the first external signal, generating the reception end signal; and generating the anti-interference enable signal after receiving the first start signal and / or the first external signal; Wherein, the receiving start signal and the receiving end signal include communication protocol signals.

3. The method according to claim 1, characterized in that The generating the anti-interference processing signal based on the receiving start signal and the receiving end signal in the anti-interference detection signal comprises: When the receiving start signal is received, the original level signal is flipped to obtain a first level signal; When the receiving end signal is received, the first level signal is flipped to obtain the anti-interference processing signal.

4. The method according to claim 3, characterized in that If the original level signal is a low level signal, the moment of receiving the receiving start signal is used as the rising edge of the anti-interference processing signal, and the moment of receiving the receiving end signal is used as the falling edge of the anti-interference processing signal; If the original level signal is a high level signal, the moment of receiving the receiving start signal is used as the falling edge of the anti-interference processing signal, and the moment of receiving the receiving end signal is used as the rising edge of the anti-interference processing signal.

5. The method according to claim 4, characterized in that Based on the first anti-interference processing signal, the received second external signal is regarded as a complete signal, including: treating a signal received between a rising edge of the first anti-interference processing signal and a falling edge of the first anti-interference processing signal as a complete signal; or The signal received between the falling edge of the first anti-interference processing signal and the rising edge of the first anti-interference processing signal is regarded as a complete signal.

6. The method according to any one of claims 1 to 5, characterized in that: Before treating the received second external signal as a complete signal based on the first anti-interference processing signal, the method further includes: The anti-interference processing signal is controlled to be effective periodically, or after receiving a second start signal, the anti-interference processing signal is controlled to be effective.

7. The method according to claim 6, characterized in that The method further includes: In the process of treating the received second external signal as a complete signal based on the first anti-interference processing signal, if a second anti-interference processing signal is received, the second anti-interference processing signal is ignored, wherein the second anti-interference processing signal is a valid anti-interference processing signal.

8. A chip, characterized in that: include: Anti-interference processing module, signal receiving module and anti-interference detection module; The anti-interference processing module is configured to send the received first start signal and the first external signal to the signal receiving module in a non-anti-interference mode, and send the received second external signal to the signal receiving module based on the received first anti-interference processing signal in an anti-interference mode, wherein the anti-interference mode is set after receiving an anti-interference enable signal, and the first anti-interference processing signal is a valid anti-interference processing signal; The signal receiving module is used to generate an anti-interference detection signal based on the received first start signal and the first external signal after receiving the anti-interference generation signal, and in the anti-interference mode, regard the received second external signal as a complete signal, wherein the anti-interference detection signal includes an anti-interference enable signal, a receiving start signal and a receiving end signal; The anti-interference detection module is used to generate the anti-interference processing signal based on the received receiving start signal and the received end signal after receiving the anti-interference generation signal, and send the anti-interference enable signal to the anti-interference processing module.

9. The chip according to claim 8, characterized in that: The signal receiving module is specifically used for: At the end time of the first start signal, generating the receiving start signal; At the end moment of the first external signal, generating the reception end signal; and generating the anti-interference enable signal after receiving the first start signal and / or the first external signal; Wherein, the receiving start signal and the receiving end signal include communication signals of a communication protocol.

10. The chip according to claim 8, characterized in that: The anti-interference detection module is specifically used for: When the receiving start signal is received, the original level signal is flipped to obtain a first level signal; When the receiving end signal is received, the first level signal is flipped to obtain the anti-interference processing signal.

11. The chip according to claim 10, characterized in that: The anti-interference detection module is specifically used for: If the original level signal is a low level signal, the moment of receiving the receiving start signal is used as the rising edge of the anti-interference processing signal, and the moment of receiving the receiving end signal is used as the falling edge of the anti-interference processing signal; If the original level signal is a high level signal, the moment of receiving the start signal is used as the falling edge of the anti-interference processing signal, and the moment of receiving the end signal is used as the rising edge of the anti-interference processing signal.

12. The chip according to claim 11, characterized in that: The anti-interference detection module is specifically used for: treating a signal received between a rising edge of the first anti-interference processing signal and a falling edge of the first anti-interference processing signal as a complete signal; or The signal received between the falling edge of the first anti-interference processing signal and the rising edge of the first anti-interference processing signal is regarded as a complete signal.

13. The chip according to any one of claims 8 to 12, characterized in that: The signal receiving module is also used for: periodically sending the first anti-interference processing signal to the anti-interference detection module; or After receiving the second start signal, the first anti-interference processing signal is sent to the anti-interference detection module.

14. The chip according to claim 13, characterized in that: The anti-interference processing module is also used for: In the process of receiving the second external signal based on the first anti-interference processing signal, if a second anti-interference processing signal is received, the second anti-interference processing signal is ignored, wherein the second anti-interference processing signal is a valid anti-interference processing signal.

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